Standard Products
QCOTSTM UT8Q512K32 16Megabit SRAM MCM
Data Sheet
March, 2009
FEATURES
25ns maximum (3.3 volt supply) address access time
MCM contains four (4) 512K x 8 industry-standard
asynchronous SRAMs; the control architecture allows
operation as 8, 16, 24, or 32-bit data width
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krads
INTRODUCTION
The QCOTSTM UT8Q512K32 Quantified Commercial Off-theShelf product is a high-performance 2M byte (16Mbit) CMOS
static RAM multi-chip module (MCM), organized as four
individual 524,288 x 8 bit SRAMs with a common output
enable. Memory expansion is provided by an active LOW chip
enable (En), an active LOW output enable (G), and three-state
drivers. This device has a power-down feature that reduces
power consumption by more than 90% when deselected.
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = >10 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 5.0E-9
- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
Packaging options:
- 68-lead dual cavity ceramic quad flatpack
(CQFP) - (weight 7.37 grams)
Writing to each memory is accomplished by taking the chip
enable (En) input LOW and write enable (Wn) inputs LOW.
Data on the I/O pins is then written into the location specified
on the address pins (A0 through A18). Reading from the device
is accomplished by taking the chip enable (En) and output enable
(G) LOW while forcing write enable (Wn) HIGH. Under these
conditions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
Standard Microcircuit Drawing 5962-01533
- QML T and Q compliant part
E3
W3
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with
En a common input to any combination of the discrete memory
die.
E2
W2
E1
W1
E0
W0
A(18:0)
G
512K x 8
512K x 8
512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:3)
or
DQ1(7:0)
Figure 1. UT8Q512K32 SRAM Block Diagram
1
512K x 8
DQ(7:0)
or
DQ0(7:0)
DEVICE OPERATION
NC
A0
A1
A2
A3
A4
A5
E2
VSS
E3
W0
A6
A7
A8
A9
A10
VDD
Each die in the UT8Q512K32 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes IDD to rise to its active value, and decodes the 19 address
inputs to each memory die by selecting the 2,048,000 byte of
memory. Wn controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Top View
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ0(2)
DQ1(2)
DQ2(2)
DQ3(2)
DQ4(2)
DQ5(2)
DQ6(2)
DQ7(2)
VSS
DQ0(3)
DQ1(3)
DQ2(3)
DQ3(3)
DQ4(3)
DQ5(3)
DQ6(3)
DQ7(3)
Table 1. Device Operation Truth Table
VDD
A11
A12
A13
A14
A15
A16
E0
G
E1
A17
W1
W2
W3
A18
NC
NC
DQ0(0)
DQ1(0)
DQ2(0)
DQ3(0)
DQ4(0)
DQ5(0)
DQ6(0)
DQ7(0)
VSS
DQ0(1)
DQ1(1)
DQ2(1)
DQ3(1)
DQ4(1)
DQ5(1)
DQ6(1)
DQ7(1)
Figure 2. 25ns SRAM Pinout (68)
Address
DQ(7:0)
Data Input/Output
En
Device Enable
Wn
G
WriteEnable
Power
VSS
Ground
En
I/O Mode
Mode
X1
X
1
3-state
Standby
X
0
0
Data in
Write
1
1
0
3-state
Read2
0
1
0
Data out
Read
READ CYCLE
Output Enable
VDD
Wn
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
PIN NAMES
A(18:0)
G
A combination of Wn greater than VIH (min) with En and G less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQn(7:0)
after the specified tAVQV is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified tETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQn(7:0).
SRAM read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
2
TYPICAL RADIATION HARDNESS
WRITE CYCLE
The UT8Q512K32 SRAM incorporates features which allow
operation in a limited radiation environment.
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when Wn is less
than VIL(max).
Table 2. Typical Radiation Hardness
Design Specifications1
Write Cycle 1, the Write Enable-controlled Access is defined by
a write terminated by Wn going high, with En still active. The
write pulse width is defined by tWLWH when the write is initiated
by Wn, and by tETWH when the write is initiated by En. Unless
the outputs have been previously placed in the high-impedance
state by G, the user must wait tWLQZ before applying data to the
eight bidirectional pins DQn(7:0) to avoid bus contention.
Total Dose
50
krad(Si) nominal
Heavy Ion
Error Rate2
<1E-8
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by Wn, and by tETEF when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait tWLQZ before applying data to the eight
bidirectional pins DQn(7:0) to avoid bus contention.
3
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
PARAMETER
LIMITS
VDD
DC supply voltage
-0.5 to 4.6V
VI/O
Voltage on any pin
-0.5 to 4.6V
TSTG
Storage temperature
-65 to +150°C
PD
Maximum power dissipation
TJ
Maximum junction temperature2
+150°C
Thermal resistance, junction-to-case3
10°C/W
DC input current
±10 mA
ΘJC
II
1.0W (per byte)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
VDD
Positive supply voltage
3.0 to 3.6V
TC
Case temperature range
-40 to +125°C
VIN
DC input voltage
0V to VDD
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(-40°C to +125°C) (VDD = 3.3V + 0.3)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
VIH
High-level input voltage
(TTL)
VIL
Low-level input voltage
(TTL)
0.8
V
VOL1
Low-level output voltage
IOL = 8mA, VDD =3.0V (TTL)
0.4
V
VOL2
Low-level output voltage
IOL = 200μA,VDD =3.0V (CMOS)
0.08
V
VOH1
High-level output voltage
IOH = -4mA,VDD =3.0V (TTL)
VOH2
High-level output voltage
IOH = -200μA,VDD =3.0V (CMOS)
CIN1
Input capacitance
ƒ = 1MHz @ 0V
32
pF
CIO1
Bidirectional I/O capacitance
ƒ = 1MHz @ 0V
16
pF
IIN
Input leakage current
VSS < VIN < VDD, VDD = VDD (max)
-2
2
μA
IOZ
Three-state output leakage current
0V < VO < VDD
VDD = VDD (max)
G = VDD (max)
-2
2
μA
Short-circuit output current
0V < VO < VDD
-90
90
mA
IDD(OP)
Supply current operating
@ 1MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
125
mA
IDD1(OP)
Supply current operating
@40MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
180
mA
IDD2(SB)
Nominal standby supply current
@0MHz
(per byte)
Inputs: VIL = VSS
IOUT = 0mA
En = VDD - 0.5, VDD = VDD (max)
VIH = VDD - 0.5V
-40°C and
25°C
6
mA
+125°C
40
mA
IOS2, 3
2.0
UNIT
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
5
V
2.4
V
VDD-0.10
V
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
(-40°C to +125°C) (VDD = 3.3V + 0.3)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tAVAV1
Read cycle time
tAVQV
Read access time
tAXQX2
Output hold time
3
ns
tGLQX2
G-controlled Output Enable time
3
ns
tGLQV
G-controlled Output Enable time (Read Cycle 3)
10
ns
tGHQZ2
G-controlled output three-state time
10
ns
tETQX2,3
En-controlled Output Enable time
tETQV3
tEFQZ1,2,4
25
ns
25
3
ns
ns
En-controlled access time
25
ns
En-controlled output three-state time
10
ns
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 300mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.
4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.
High Z to Active Levels
Active to High Z Levels
VH - 300mV
VLOAD + 300mV
}
VLOAD
{
{
}
VLOAD - 300mV
VL + 300mV
Figure 3. 3-Volt SRAM Loading
6
tAVAV
A(18:0)
DQn(7:0)
Previous Valid Data
Valid Data
tAVQV
tAXQX
Assumptions:
1. En and G < VIL (max) and Wn > VIH (min)
Figure 4a. SRAM Read Cycle 1: Address Access
A(18:0)
En
tETQV
DQn(7:0)
tEFQZ
tETQX
DATA VALID
Assumptions:
1. G < VIL (max) and Wn > VIH (min)
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access
tAVQV
A(18:0)
G
tGHQZ
tGLQX
DATA VALID
DQn(7:0)
Assumptions:
1. En < VIL (max) and Wn > VIH (min)
tGLQV
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access
7
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
(-40°C to +125°C) (VDD = 3.3V + 0.3)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tAVAV1
Write cycle time
25
ns
tETWH
Device Enable to end of write
20
ns
tAVET
Address setup time for write (En - controlled)
1
ns
tAVWL
Address setup time for write (Wn - controlled)
0
ns
tWLWH
Write pulse width
20
ns
tWHAX
Address hold time for write (Wn - controlled)
2
ns
tEFAX
Address hold time for Device Enable (En - controlled)
2
ns
tWLQZ2
Wn- controlled three-state time
tWHQX2
Wn - controlled Output Enable time
5
ns
tETEF
Device Enable pulse width (En - controlled)
20
ns
tDVWH
Data setup time
15
ns
tWHDX2
Data hold time
2
ns
tWLEF
Device Enable controlled write pulse width
20
ns
tDVEF2
Data setup time
15
ns
tEFDX
Data hold time
2
ns
tAVWH
Address valid to end of write
20
ns
Write disable time
5
ns
tWHWL1
10
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disabled (G high).
2. Three-state is defined as 300mV change from steady-state output voltage.
8
ns
A(18:0)
tAVAV2
En
tAVWH
tETWH
tWHWL
Wn
tWLWH
tAVWL
tWHAX
Qn(7:0)
tWLQZ
Dn(7:0)
tWHQX
APPLIED DATA
Assumptions:
1. G < VIL (max). If G > VIH (min) then Qn(8:0) will be
in three-state for the entire cycle.
2. G high for tAVAV cycle.
tDVWH
tWHDX
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access
9
tAVAV3
A(18:0)
tETEF
tAVET
tEFAX
En
or
tAVET
En
tETEF
tEFAX
tWLEF
Wn
Dn(7:0)
APPLIED DATA
tWLQZ
tDVEF
Qn(7:0)
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle.
2. Either En scenario above can occur.
3. G high for tAVAV cycle.
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
CMOS
VDD-0.05V
90%
90%
300 ohms
10%
VLOAD = 1.55
10%
0.5V
< 5ns
50pF
< 5ns
Input Pulses
Notes:
1. 50pF including scope probe and test socket capacitance.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = VDD/2).
Figure 6. AC Test Loads and Input Waveforms
10
DATA RETENTION MODE
VDD
50%
50%
VDR > 2.0V
tR
tEFR
En
Figure 7. Low VDD Data Retention Waveform
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(1 Second Data Rentention Test)
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
VDD for data retention
2.0
--
V
IDDR 1,2
Data retention current (per byte)
--
2.0
mA
tEFR1,3
Chip select to data retention time
0
ns
tAVAV
ns
VDR
tR1,3
Operation recovery time
Notes:
1. En = VDD - .2V, all other inputs = VDR or VSS.
2. Data retention current (IDDR) Tc = 25oC.
3. Not guaranteed or tested.
4. VDR = T=-40oC and 125oC.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(10 Second Data Retention Test, TC=-40oC and +125oC)
SYMBOL
VDD1
tEFR2, 3
tR2, 3
PARAMETER
VDD for data retention
Chip select to data retention time
Operation recovery time
Notes:
1. Performed at VDD (min) and VDD (max).
2. En = VSS, all other inputs = VDR or VSS.
3. Not guaranteed or tested.
11
MINIMUM
MAXIMUM
UNIT
3.0
3.6
V
0
ns
tAVAV
ns
PACKAGING
Notes:
. Package shipped with non-conductive
strip (NCS). Leads are not trimmed.
2. Total weight approx. 7.37g.
Figure 8. 68-pin Ceramic FLATPACK
12
ORDERING INFORMATION
512K32 16Megabit SRAM MCM:
UT8Q512K32 -* *
*
*
Lead Finish:
(C) = Gold
Screening:
(P) = Prototype flow
(W) = Extended Industrial Temperature Range Flow (-40oC to +125oC)
Package Type:
(S) = 68-lead dual cavity CQFP
Device Type:
- = 25ns access, 3.3V operation
Aeroflex Core Part Number
Notes:
1. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY.
2. Extended Industrial Temperature Range Flow per Aeroflex Colorado Springs Manufacturing Flows document. Devices are tested at -40oC to +125oC.
Radiation neither tested nor guaranteed. Gold lead finish only.
13
512K32 16Megabit SRAM MCM: SMD
5962 - 01533 **
* * *
Lead Finish:
(C) = Gold
Case Outline:
(X) = 68-lead dual cavity CQFP
Class Designator:
(T) = QML Class T
(Q) = QML Class Q
Device Type
01 = 25ns access time, 3.3V operation, Extended Industrial Temp (-40oC to +125oC)
Drawing Number: 01533
Total Dose
(-) = none
(D) = 1E4 (10krad(Si))
(L) = 5E4 (50krad(Si)) (contact factory)
(P) = 3E4 (30krad(Si)) (contact factory)
Federal Stock Class Designator: No Options
Notes:
1. Total dose radiation must be specified when ordering. Gold lead finish only.
2. Only Extended Industrial Temperature -40C to +125C. No military temp. test available.
14
Aeroflex Colordo Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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reserves the right to make changes to any products and
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or an authorized sales representative to verify that the
information in this data sheet is current before using this
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