UT54ACS109/UT54ACTS109 Radiation-Hardened Dual J-K Flip-Flops FEATURES • • • • • • PINOUTS 16-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack CLR1 DESCRIPTION The UT54ACS109 and the UT54ACTS109 are dual J-K positive triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels. When preset and clear are inactive (high), data at the J and K input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the J and K input can be changed without affecting the levels at the outputs. The flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D flip-flops if J and K are tied together. The devices are characterized over full military temperature range of -55 C to +125 C. 1 16 VDD CLR2 J 2 15 K1 3 14 J2 CLK1 PRE1 4 5 13 12 K2 Q1 Q1 VSS 6 7 8 11 10 9 PRE2 Q2 Q2 CLK2 16-Lead Flatpack Top View CLR1 1 16 VDD J1 2 15 CLR2 K1 3 14 J2 CLK1 PRE1 4 5 13 12 K2 Q1 6 11 PRE2 Q1 7 8 10 9 Q2 VSS CLK2 Q2 FUNCTION TABLE INPUTS OUTPUT PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H1 H1 H H L L L H H H H L Toggle H H L H No Change H H H H H H X X L H PRE1 J1 CLK1 K1 CLR1 PRE2 L No Change Note: 1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near VIL maximum. In addition, this configuration is nonstable; that is, it will not persist when either preset or clear returns to its inactive (high) level. 61 LOGIC SYMBOL J2 CLK2 (5) (2) (4) (3) (1) S J1 C1 K1 R (6) (7) Q1 Q1 (11) (14) (10) Q2 (12) (13) K2 (15) CLR2 (9) Q2 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. RadHard MSI Logic UT54ACS109/UT54ACTS109 LOGIC DIAGRAM PRE Q CLK J Q K CLR RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 62 UT54ACS109/UT54ACTS109 RECOMMENDED OPERATING CONDITIONS 63 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS109/UT54ACTS109 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8 ,9 CL = 50pF 2.0 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 64 UT54ACS109/UT54ACTS109 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 65 RadHard MSI Logic UT54ACS109/UT54ACTS109 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1 , -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL CLK to Q, Q 5 27 ns tPLH CLK to Q, Q 4 23 ns tPLH PRE to Q 1 16 ns tPHL PRE to Q 1 19 ns tPHL CLR to Q 2 19 ns tPLH CLR to Q 2 16 ns fMAX Maximum clock frequency 62 MHz tSU1 PRE or CLR inactive Setup time before CLK 5 ns tSU2 Data setup time before CLK 5 ns t H3 Data hold time after CLK 3 ns tW Minimum pulse width PRE or CLR low CLK high CLK low 8 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). 3. Based on characterization, hold time (t H) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 66