PRELIMINARY DATA SHEET 3 V DUAL DOWNCONVERTER AND PLL FREQUENCY SYNTHESIZER UPB1005GS DESCRIPTION • INTEGRATED RF BLOCK: RF & IF Downconverter + PLL frequency synthesizer • DOUBLE-CONVERSION: f1stIF = 61.380 MHz f2ndIF = 4.092 MHz • LOW POWER CONSUMPTION: 46.4 mA @ 3 V The UPB1005GS is a Silicon RFIC designed for low cost GPS receivers. The IC combines a double-conversion RF/IF downconverter block and a PLL frequency synthesizer on one chip. The device operates on a 3 V supply voltage and is housed in a small 30 pin SSOP package, resulting in low power consumption and reduced board space. The device is manufactured using the NESAT™ III 20 GHz fT silicon bipolar process. • LOW CURRENT CONSUMPTION: ICC = 46.4 mA TYP @ VCC = 3.0 V NEC's stringent quality assurance and test procedures ensure the highest reliability and performance. UE • ADJUSTABLE GAIN: 20 dB range MIN • FIXED DIVISION PRESCALER • SMALL 30 PIN SSOP PACKAGE USAGE IN • TAPE AND REEL PACKAGING AVAILABLE D FEATURES • CONSUMER USE GPS RECEIVER OF REFERENCE FREQUENCY 16.368 MHz, 2ND IF FREQUENCY 4.092 MHz. ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3 V, unless otherwise specified) SYMBOLS ICC NT PART NUMBER PACKAGE OUTLINE PARAMETERS AND CONDITIONS Total Circuit Current, No Signals UNITS MIN mA UPB1005GS S30 TYP MAX 46.4 Circuit Current 1, No Signals mA CGRF RF Conversion Gain, PRFin = -40 dBm dB 15 NFRF RF SSB Noise Figure, PRFin = -40 dBm dB 12.5 SC O RF Downconverter Block (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLOin = -10 dBm, ZL = ZS = 50 Ω) ICC1 dBm -5 PO(sat)RF Maximum IF Output, PRFin = -10 dBm 10 IF Downconverter Block (f1stIFin = 61.38 MHz, f2ndLOin = 65.472 MHz, ZS = 50 Ω, ZL = 2 kΩ) Circuit Current 2, No Signals IF Conversion Gain at Max. Gain, P1stIFin = -50 dBm IF SSB Noise Figure at Max. Gain, P1stIFin = -50 dBm Maximum 2nd IF Output Level at Max. Gain, P1stIFin = -20 dBm VGC Gain Control Voltage, Voltage at Max. Gain of CGIF GCR Gain Control Range, P1stIFin = -20 dBm 2nd IF Amplifier (f2ndIF= 4.092 MHz, ZS = 50 Ω, ZL = 2 kΩ) ICC3 Circuit Current 3, No Signals |S21| Gain |S21|, ZL = 1 MΩ // 27 pF1 V2ndIFout Output Voltage Swing, ZL = 1MΩ // 27 pF1 PLL Synthesizer Block ICC4 Circuit Current 4, PLL, All Blocks Operating fPD Phase Comparison Frequency, PLL Loop VREFin Reference Input Minimum Level, ZL = 10 kΩ // 20pF1 VLP(H) Loop Filter Output Level (H) VLP(L) Loop Filter Output Level (L) VREFout Reference Output Swing, ZL = 1 MΩ // 27 pF1 DI ICC2 CGIF NFIF PO(sat)IF mA dB dB 5.3 37 15 dBm V dB 0 mA dB mVP-P mA MHz mVP-P V V VP-P 1.0 20 2.4 37 600 8.0 200 2.8 28.7 8.184 8.4 0.4 1.0 Note: 1. Impedance of measurement equipment. California Eastern Laboratories UPB1005GS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C) PARAMETERS VCC UNITS RATINGS V 3.6 Supply Voltage ICC Total Circuit Current mA SYMBOLS 62 PD Power Dissipation2 mW 433 TOP Operating Temperature °C -40 to +85 TSTG Storage Temperature °C -55 to +150 3.0 3.3 TOP Operating Temperature °C -40 +25 +85 fRFin RF Input Frequency 1540fo UPC2749TB MHz MHz 1616.8 1636.8 1656.8 1st IF Input Frequency MHz 61.38 f2ndLOin 2nd LO Input Frequency MHz 65.472 2nd IF Input/Output Frequency Reference Input/Output Frequency UE f2ndIFin f2ndIFout fTCXOin fTCXOout IN 4fo LPF IF MIX in IF MIX out VGC 4.092 MHz SC O 8fo DI Note: This diagram schematically shows only the UPB1005's internal functions on the system. This diagram does not represent the actual application circuit. Buffer to DSP 16.368 MHz P D 1/8 16fo 1/2 Buffer REF 1600fo 1stLO-OSC2 16.368 4fo OSC 1stLO-OSC1 MHz 2ndIF Amp IF MIX 1/25 4.092 2ndIFin1 2ndIFin2 2ndIF Bypass RF MIX 64fo MHz fo = 1.023 MHz UPB1005GS is in 1540fo BPF 1575.42 f1stIFIN NT LNA 1575.42 MHz from Antenna MAX 2.7 BPF RF MIX out TYP V 1st LO Oscillating Frequency APPLICATION EXAMPLE 60fo UNITS MIN Supply Voltage f1stLOin Notes: 1. Operation in excess of any one of these parameters may result in permanent damage. 2. Mounted on a 50 x 50 x 1.6 mm double-sided copper clad epoxy glass PWB (TA = +85°C). GPS Receiver RF Block PARAMETERS VCC D SYMBOLS LOOP 8fo AMP LOout VCC TCXO 16.368MHz to DSP UPB1005GS PIN FUNCTIONS Symbol Applied Voltage (V) Pin Voltage (V) 3 RF MIXout — 1.68 4 VCC (RF MIX) 2.7 to 3.3 — Function and Application Output pin of RF mixer. 1st IF filter must be inserted between pin 1 & 3. Supply voltage pin of RF mixer block. This pin must be decoupled with a capacitor (~1000 pF). Internal Equivalent Circuit 4 1st LO -OSC 3 5 5 RF MIXin — 1.20 6 GND (RF MIX) 0 — Ground pin of RF mixer. 7 VCC (1stLO-OSC) 2.7 to 3.3 — Supply voltage pin of differential amplifier for 1st LO oscillator circuit. 8 1stLO-OSC1 — 1.75 9 1stLO-OSC2 — 1.75 GND 11 VCC (phase detector) 2.7 to 3.3 12 PD-VOUT3 Pull-up with resistor 13 PD-Vout1 — GND — – Output in accordance with phase difference – UE Pins of active loop filter for tuning voltage output. The active transistors configured with darlington pair are built on-chip. Pin 14 should be connected to ground. Pin 12 to 13 should be equipped with external RC in order to adjust damping factor and cutoff frequency. This tuning voltage output must be connected to varactor diode of 1st LO-OSC. 15 GND (phase detector) GND — Ground pin of phase detector and active loop filter. 16 VCC (divider block) 2.7 to 3.3 — Supply voltage pin of prescalers. LOout — 1.98 18 GND (divider block) GND — DI 17 6 VCC 8 RF MIX or Prescaler Input 9 10 Supply voltage pin of phase detector and active loop filter. SC O 14 PD-VOUT2 — IN GND (1stLO-OSC) 7 Pins 8 & 9 are each base pins of the differential amplifier for 1st LO oscillator. These pins should be equipped with LC and varactor circuit to oscillate at 1636.8 MHz as VCO. Ground pin of differential amplifier for 1st LO oscillator circuit. NT 10 Input pin of RF mixer. 1 575.42 MHz band pass filter must be inserted between pin 5 and external LNA. D Pin No. Monitor pin of comparison frequency at phase detector. Ground pin of prescalers and LOout amplifier. 11 13 PD 12 15 16 1st LO OSC 18 14 IF MIX PD PD 17 ÷25 ÷8 ÷2 Ref. UPB1005GS PIN FUNCTIONS Symbol Applied Voltage (V) Pin Voltage (V) 19 REFin — 1.97 20 VCC (reference 2.7 to 3.3 block) — Function and Application Input pin of reference frequency. This pin should be equipped with external TCXO of 16.368 MHz. Internal Equivalent Circuit 20 Supply voltage pin of input/output amplifiers in reference block. 21 19 REFout — 1.75 Output pin of reference frequency. The frequency from pin 19 can be measured at 1 Vp-p swing. PD UE 21 D Pin No. 18 22 2ndIFout — 1.65 23 VCC (2ndIF AMP) 2.7 to 3.3 — 2ndIF bypass — Output pin of 2nd IF amplifier. This output is a 4.092 MHz clipped sinewave. This pin should be equipped with external inverter to adjust level to next stage on user's system. 23 IN 24 Supply voltage pin of 2nd IF amplifier. 24 2.25 Bypass pin of 2nd IF amplifier input 1. This pin should be grounded through a capacitor. 22 26 25 2ndIFin2 — 2.25 26 2ndIFin1 — 2.25 27 GND (2ndIF AMP) GND — 28 IF MIXout — NT 25 Pin of 2nd IF amplifier input 2. This pin should be grounded through capacitor. 29 VGC (IF MIX) 0 to 3.3 – 30 VCC (IF MIX) 2.7 to 3.3 — 1 IF MIXin — 1.18 2 GND (IF MIX) 0 — 27 Ground pin of 2nd IF amplifier. Output pin from IF mixer. IF mixer output signal goes through gain control amplifier before this emitter follower output port. SC O 1.80 Pin of 2nd IF amplifier input 1. 2nd IF filter must be inserted between pins 26 & 28. Gain control voltage pin of IF mixer output amplifier. This voltage performs forward control (VGC up➝Gain down). Supply voltage pin of IF mixer, gain control amplifier and emitter follower transistor. Input pin of IF mixer. 29 30 1 28 2nd LO 2 Ground pin of IF mixer. DI Note: Ground pattern on the board must be formed as wide as possible to minimize ground impedance. UPB1005GS TEST CIRCUIT 1 PIN Signal Generator 50Ω C1 50Ω 30 2 29 3 28 C2 VCC C23 C22 Target maximum gain. Apply 1.0V MAX. D Spectrum Analyzer 1 C21 Spectrum Analyzer R6 VCC Signal Generator 4 C3 27 50Ω (High impedance probe, 1 MΩ // 0.7 pF) UE 50Ω 5 26 C4 C20 ÷25 6 Signal Generator 25 C19 7 C5 C18 R1 8 23 C6 D1 L 24 ÷8 9 C7 10 R2 VCC C17 C16 Spectrum Analyzer or Oscilloscope 22 IN VCC R5 21 Spectrum Analyzer or Oscilloscope C15 11 VCC C8 20 C14 R3 12 C10 R4 ÷2 NT C9 PD 13 14 15 19 VCC 50Ω C13 Signal Generator 18 Spectrum Analyzer or Oscilloscope 17 C12 16 VCC C11 SC O NOTE: Spectrum Analyzer to measure frequency. Oscilloscope to measure voltage swing. COMPONENTS LIST FORM Chip Capacitor DI Ceramic capacitor Chip Resistor (High impedance probe, 1 MΩ // 0.7 pF) SYMBOL VALUE C1 to C5, C12, C13, C15, C17, C18, C22 1000 pF C8, C11, C14, C23 1 µF C6, C7 24 pF (NPO) C9 1800 pF C19 9900 pF C10 33 nF C16, C20 0.1 µF C21 0.01 µF R1, R2 4.7 kΩ R3 6.2 kΩ R4 1.2 kΩ R5, R6 1.95 kΩ Varactor Diode D1 HVU12 Chip Inductor L 2.7 nH UPB1005GS OUTLINE DIMENSIONS (Units in mm) ORDERING INFORMATION Package Outline S30 30 Part Number Package UPB1005GS-E1 30 Pin plastic SSOP Embossed tape 16 mm wide. Qty 2.5 kp/reel. Pin 1 is in tape pull-out direction. D 16 +7˚ 3˚ -3˚ 15 10.11 MAX 1.7±0.1 8.1±0.2 6.1±0.2 +0.10 0.15 -0.05 1.0±0.2 UE 1 2.0 MAX 0.125±0.075 0.65 (T.P.) +0.10 0.30 -0.05 0.10 0.5±0.2 0.51 MAX NT IN Note: Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. INTERNAL BLOCK DIAGRAM IF MIXin 1 30 VCC (IF MIX) GND(IF MIX) 2 29 VGC (IF MIX) RF MIXout 3 28 IF MIXout VCC (RF MIX) 4 27 GND (2ndIF Amp) RF MIXin 5 26 2ndIFin1 25 2ndIFin2 ÷25 6 VCC (1stLO-OSC) 7 24 2ndIF Bypass 1stLO-OSC1 8 23 VCC (2ndIF Amp) 1stLO-OSC2 9 22 2ndIFout GND (1stLO-OSC) 10 21 REFout VCC (phase detector) 11 20 PD-Vout3 12 PD-Vout2 13 18 GND (divider block) PD-Vout1 14 17 LOout 15 16 VCC (divider block) DI SC O GND (RF MIX) GND (phase detector) EXCLUSIVE NORTH AMERICAN AGENT FOR Quantity and Form PD ÷8 ÷2 19 VCC (reference block) REFin RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: http://WWW.CEL.COM PRINTED IN USA ON RECYCLED PAPER -1/99 DATA SUBJECT TO CHANGE WITHOUT NOTICE