NEC's LOW POWER UPB1008K GPS RF RECEIVER FEATURES BLOCK DIAGRAM • LOW POWER CONSUMPTION: 52 mW • DUAL-CONVERSION IQ DOWN CONVERTER1: Reference frequency: REFin = 27 MHz • PSEUDO-BASEBAND WITH 2-BIT DIGITIZED OUTPUT • ON-CHIP LNA, ON-CHIP FREQUENCY SYNTHESIZER, IF AGC AMPLIFIER: with 45 dB typical range of adjustable gain • SMALL 36 PIN QFN PACKAGE: Flat lead style for better RF performance AGC PIN 1 – OSC UPB1008K Dividers LNA IQ DEMO 1stMIX ADC PD Note: 1. Based on eRide's proprietary GPS DSP architecture 1/2 ADC APPLICATIONS DESCRIPTION • E911 ENABLED MOBILE PHONE NEC's UPB1008K is a Silicon RFIC especially designed for handheld low power/low cost GPS receivers. The IC combines an LNA, followed by a double-conversion RF/IF downconverter block and a PLL frequency synthesizer on one chip. The second IF Freqency is a pseudo- baseband signal into a on-chip 2-bit A/D converters.The device can operate on a supply voltage as low as 2.7 V, and is a housed in a small 36 pin QFN (Quad, Flat, No-lead) package, resulting in a very low power consumption and reduced board space. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance. • IN-VEHICLE NAVIGATION SYSTEMS • LOW POWER HANDHELD GPS RECEIVER • PC/PDA+GPS INTEGRATION • ASSET TRACKING RF APPLICATION DIAGRAM Nyquist Filters IF filter AGC ISign LNA 2-bit ADC IMag 2-bit ADC QSign QMag RF SAW TANK /2 Loop Filter /4 /6 /7 BASEBAND I C 1st Mixer /2 I/Q Balance PLL Frequency Counters /8 /2 REFin 27 MHz Regulator Circuitry Reference Clock California Eastern Laboratories UPB1008K ADVANCED GPS COMPLETE SOLUTION e 911 AUTOMOTIVE e YELLOW PAGES ASSET TRACKING PERSONAL GPS NETWORK TRACKING eRide NAVIGATION SOFTWARE & DRIVERS TEMP TIME FREQ UART GAIN CONTROL eRide SMART SERVER ADC OPUS ACQUISITION STATE MACHINE PLL TRACKING ADC UPB1008K Opus 1 eRide WORLDWIDE REFERENCE STATION NETWORK ADVANCED GPS COMPLETE SOLUTION "NEC Corporation and eRide, Inc. have teamed to provide an advanced positioning solution delivering high GPS performance, accuracy, integration and architecture flexibility. The chip set combines CEL's UPB1008K receiver IC with eRide's Opus One SOC (System-on-a-Chip) Baseband ASIC and is suitable for standard GPS products as well as Cellular Handset applications. Also provided are scalable client navigation software and drivers, plus location-aiding data from eRide's Smart Server. Together, they offer a complete hardware/infrastructure solution. The chip set's design allows it to operate independently of wireless interface standards - and independently of the host product's CPU and Operating System. This unique approach to system integration makes it easy to deploy the chip set into an wireless application, in any wireless network. A "Universal Hardware" solution, the design promises lower manufacturing costs and, ultimately lower cost to the consumer. The chip set's advanced positioning architecture offers unmatched sensitivity providing fast, accurate positioning architecture offers unmatched sensitivity providing fast and accurate position fixes, even when indoors or in deep in urban canyons." HIGH PERFORMANCE GPS OMNI MODE LI, C/A code receiver Performance Indoor Outdoor Time to First Fix w/ aiding Time to First Fix w/o aiding Accuracy Sensitivity 5-7sec 10-20sec 10-25m cep -155dBm in 1sec dwells 1-3sec 3-5sec 2-5m cep -142dBm in two 10msec dwells Superior performance in high reflection indoor environments and in urban canyon types of outdoor environments POWER DISSIPATION First Fix 400 mW Tracking 200-300 mW Stand By 30 mW UPB1008K ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3.0 V, unless otherwise specified) SYMBOLS ICC VCC ICC_PD PARAMETERS AND CONDITIONS Total Circuit Current, No Signals UNITS mA MIN 14 TYP 18 MAX 23.5 Supply Voltage V 2.7 3.0 3.3 Power down current, PIN 13 = VIL µA – 1 10 ICC rf RF Block Circuit Current (pin 3), No signal µA 0.4 0.5 0.7 ICC lo VCO Block Circuit Current (pin 7), No signal mA 4.1 5.6 7.2 ICC pll PLL Block Circuit Current (pin 9), No signal mA 2.7 3.6 4.7 ICC bb Baseband Block Circuit Current (pin 23), No signal, open load mA 2.5 3.4 4.3 ICC if ICC lna IF Block Circuit Current (pin 28) , No signal mA 2.7 3.7 4.7 Pre-Amplifier Open Connector Current (pin 36), No signal mA 1.0 1.4 1.8 LNA/RF DOWNCONVERTER (fRFin = 1575.42 MHz, f1stLOin = 1400 MHz, PLO = -10 dBm, f1stIF = 175 MHz, Pin 13: VIL = 3 V, ZL differential = 32Ω & ZS = Γopt) SYMBOLS CGLNA_MIX NFLNA_MIX P1dBLNA_MIX ZLNAin ZMIXout ALO-IF ALO-RF PARAMETERS AND CONDITIONS Power conversion gain from 2nd LNA/mixer to 1st IF, PRFin = -50 dBm Noise Figure of 2nd LNA/mixer(SSB), Input matched 1 dB Compression refer to source, Input matched RF Input Impedance of LNA IF Output Impedance of Mixer Local Signal Leak to IF, f1stLOin=1400 MHz, PLO = 0 dBm Local Signal Leak to RF, f1stLOin=1400 MHz, PLO = 0 dBm UNITS MIN TYP MAX dB 18 23 28 dB dBm Ohm Ohm dBm – – – – – – – 5 -38 31 32 -35 – dBm – -50 – PLL SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX ICPOH ICPOL fPD PLL Charge Pump High Side Current @ VCPout = VCC/2 PLL Charge Pump Low Side Current @ VCPout = VCC/2 Phase Comparison Frequency µA µA MHz – – – 200 -200 13.5 – – – UNITS MIN TYP MAX mVpp MHz V dBc/Hz 50 – 0.8 57 200 27 1.5 62 – – 2.2 – CRYSTAL OSCILLATOR/REVERENCE AMPLIFIER BLOCK SYMBOLS VREFin fREF VT C/N PARAMETERS AND CONDITIONS Reference input minimum level Input Frequency of Reference Input VCO Control Voltage, PLL Locked VCO C/N, 1kHz, Loop band width = 5 kHz AGC AMPLIFIER, I-Q DEMODULATOR, and ADC BLOCK(f1stIFin = 175 MHz, Zin = 600Ω) SYMBOLS CGAGC/MIX AAGC/MIX P1dBAGC VAGC PARAMETERS AND CONDITIONS Maximum voltage conversion gain of AGC amplifier/ I-Q mixer, Pin = -60 dBm, VAGC = 0.5 V, Unmatched Minimum voltage conversion gain of AGC amplifier/ I-Q mixer, Pin = -60 dBm, VAGC = 2.0 V, Unmatched AGC control range, VAGC = 0.5 V to 2 V 1 dB compression input to AGC amplifier, set voltage gain = 30 dB AGC control voltage BW 3dB Mixer Bandwidth IQ BalanceControl Voltage, Gain(Ich) = Gain (Qch) VIQ-C AIQ-C IQ Balance Control Gain Range, VIQ-C = 0 to 3 V Duty Ich Mag Bit Output Pulse Duty, P1stIFin = -84 dBm Ich VAGC = 0.5 V, VIQ-C = 0 V Duty Qch Mag Bit Output Pulse Duty, PIF2in = -88 dBm Qch VAGC = 0.5 V, VIQ-C = 0 V BASEBAND AMPLIFIER BLOCK (ZS = 2kΩ & ZL = 2 kΩ) SYMBOLS PARAMETERS AND CONDITIONS VBBOH Baseband output logic high, CL = 10 pF VBBOL Baseband output logic low, CL = 10 pF UNITS dB MIN – TYP 30 MAX – dB – -15 – dB 25 45 – dBm – -45 – V 0.5 – 2.0 MHz V dB % – – 4.0 50 10 2.1 6.5 – – 2.8 – – % 50 – – UNITS V V MIN 2.0 0 TYP – – MAX – 0.5 UPB1008K RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS1,2 (TA = 25°C) SYMBOLS VCC PD TOP TSTG ICC_total PARAMETERS Supply Voltage4 Total Power Dissipation3 Operating Temperature Storage Temperature Total Circuit Current4 UNITS VCC mW °C °C SYMBOLS VCC TOP fRFin fREFin f1stLO RATINGS 3.6 361 -40 to +85 -55 to +150 Notes: 1. Operation in excess of any one of these parameters may result in permanent damage. 2. More than two items must not be reached simultaneously. 3. TA = +85°C, mounted on a 50 x 50 x 1.6 mm double-sided copper clad epoxy glass PWB. 4. TA = 25°C PARAMETERS Supply Voltage Operating Temperature RF Input Frequency Reference Frequency 1st LO Oscillating Frequency 1st IF Input Frequency 2nd LO Input Frequency Power Down Control Voltage "High" Power Down Control Voltage "Low" f1stIFin f2ndLOin VIH VIL UNITS MIN V 2.7 °C -40 MHz MHz MHz MHz MHz TYP 3.0 +25 1575 27 MAX 3.3 +85 1400 175 175 V 2 VCC V 0 0.5 APPLICATION CIRCUIT 1:16 0.1uF 15pF IN SAW OUT INb VCC OUTb 15pF IFin2 VAGC VCC IFin1 GNDanalog Mixout2 Vref LNAbias 1.2nH Mixout1 200 0.1uF VCCanalog 100nF 36 35 34 33 32 31 30 29 28 VCC VCC 43K .1pF GND1na 300 AGC 1 SAW MATCHING FILTER NETWORK 21FoutI 150pF LNAin IQ_DEMO 6.8nH 1stMIX 2 VCC 12pF VCCrf NE662MO4 LNA 3 26 25 21Foutb DCoffsetI 100nF 100nF GNDIo 4 24 DCoffsetb VCC 1stLO-OSC1 1/2 5 23 VCCbb 12pF 1stLO-OSC2 12pF VCC VCCIo 100nF Vth 1/4 22 6 OSC 1/2 I_mag 2Bit ADC 21 7 I_sign I_mag 1/6.375 100nH PDout 8 20 PD 3.3nH D0 19 Q_mag Q_mag CP uPB1008K 15K 1.2K VCC Vagc 10 11 12 13 14 15 16 17 18 PD 100nF 150pF 1OOnF GNDbb DCoffsetQ 21FoutQb 21FoutQ PD Ic_cntl 100nF GNDdig 0.01uF Refin 22pF I_sign Q_sign 1/2 9 15K Q_sign 2Bit ADC DCoffsetQb 3.3nH Vccdig RF_in 27 3.3nH 12pF ic_cntl REFin UPB1008K PIN FUNCTIONS Pin No. Symbol 1 GNDlna Function and Application Internal Equivalent Circuit 3 Ground pin of LNA 36 2 Input pin of low noise amplifier. It is a single-ended open collector design. Capacitive coupling is required; external matching will improve gain or NF. VCC r=6.5k LNAin Bias 2 Regulator GND 1 3 VCCrf Supply voltage pin of LNA, RF mixer and VCO voltage regulator. 4 GNDlo Ground pin of 1st LO Oscillator circuit and RF Mixer. 5 6 1stLO-OSC1 1stLO-OSC2 7 r = 410 3 VCClo c=1.8p r=300 6 5 r=4.4k VCC r=4.4k Bias 7 c=1.8p r=300 Pin 5 & 6 are base pins of the differential amplifier for 1st LO oscillator. These pins require an LC (varacator) tank circuit to oscillate at around 1400 MHz. Supply voltage pin of oscillator circuit for 1st LO Oscillator and RF mixer Regulator idc=941u GND 4 8 PDout This is a current mode charge pump output. For connection to a passive RC loop filter for driving external varactor diode of 1stLO-OSC. 9 VCCdig Supply voltage pin of digital portion of the chip. FROM PFD 9 ESD Source PFD Source Control 8 Sink Control PFD Sink ESD 11 10 REFin Input pin of reference frequency buffer. This pin should be equipped with external 27 MHz oscillator (e.g. TCXO). 9 r=20k r=20k idc=9.7u ESD GNDdig Ground pin of digital portion of the chip. 10 ESD r=500 r=500 r=50k 11 r=30k idc=22u 11 c=5.4p UPB1008K PIN FUNCTIONS Pin No. Symbol 12 I/Q Balance Control Function and Application Internal Equivalent Circuit 28 The voltage on this pin controls the Q channel IF Amplifier Gain. Gain control of ±2 dB can be achieved for 0~3 V. Leave open-circuited if not used. idc=23.5u idc=23.5u Iref CCCS r=200k Qgain +2dB r=12k 12 –2dB r=7.1k r=7.1k r=7.1k 0V 1.5 V 3V r=7.1k V 32 VCC 13 PD1 Standby mode control. Low=whole chip OFF & High=Whole chip ON. ESD 13 r=28k ESD 11 2IFout-Q 2IFout-Qb Differential ouptut pins of quadrature demodulator Q output. Adding a lowpass shunt capacitor between these pins will define the IF Bandwidth. 28 r=2k ESD ESD r=2k From 2nd Mixer r=2k r=2k 15,(26) To channel amp 14 15 14,(27) idc=86u idc=86u ESD ESD 32 28 r=4k ESD r=4k ESD 17,(24) r=20k c=9p 16,(25) idc=84u idc=84u ESD 32 ESD To offset amp DC offset Qb r=150k 17 DC offset compensation pin for C arm. A low pass capacitor shunt to Pin 17 is required. DC offset compensation pin for Q-bar arm. A low pass capacitor shunt to Pin 16 is required. r=150k DC offset Q From 2nd Mixer 16 UPB1008K PIN FUNCTIONS Symbol 18 19 20 21 22 23 GNDbb Qmag Qsign Isign Imag VCCbb Function and Application Internal Equivalent Circuit Ground pin of CMOS output driver. Digitized Q signal. Magnitude bit of 2-bit ADC output. Digitized Q signal. Sign bit of 2-bit ADC output Digitized I signal. Sign bit of 2-bit ADC output. Digitized I signal. Magnitude bit of 2-bit ADC output. Supply voltage pin of CMOS output driver. 23 r=21.5 From Comparator Pin No. r=21.5 r=5k ESD 19, (20,21,22) ESD 18 24 DCoffsetIb 25 DCoffsetI 26 27 2IFout-Ib 2IFout-I 28 29 VCC if VAGC DC offset compensation pin for I-bar arm. A low pass capacitor shunt to Pin 25 is required. DC offset compensation pin for I arm. A low pass capacitor shunt to Pin 24 is required. Differential output pins of quadrature demodulator I output. Adding a lowpass shunt capacitor between these pins will define the IF bandwidth. Supply voltage pin of analog portion of the chip. Gain control voltage pin of IF amplifier. This voltage performs reverse control,(i.e., VAGC up → gain down). If this pin is left open, then it is default at maximum gain. See pin 16 & 17 schematic See pin 14 & 15 schematic 28 r=300 ESD To AGC Amp r=44k 30 Typical AGC Gain Response 29 r=3k ESD 0 -15 0.5 32 VAGC (V) Differential input pins of 1st IF AGC amplifier 28 r=4k Ground pin of analog portion of the chip. r=2k r=2k r=4k Bias From VAGC IF-in1 IF-in2 GNDanalog 2 AGC amp out 30 31 32 1.5 Regulator ESD ESD r=4k r=4k 31 r=40 30 ESD ESD r=1.42k r=1.42k 32 7 Differential output pins of RF mixer. This is an emitter follower output buffer, provide a 50Ω output load. ESD 34 ESD c=1.67p r=4k 33 Regulator ESD r=4k Mixout2 Mixout1 From Mixer 33 34 c=1.67p ESD r=111 r=111 4 UPB1008K PIN FUNCTIONS Pin No. Symbol 35 Vref Function and Application Internal Equivalent Circuit Base-emitter junction voltage wth respect to ground. May be used for biasing an external discrete transistor. Regulation will develop PTAT current. 3 r=500 Bias VCC ESD Regulator GND 35 r=40k ESD 4 36 LNAbias LNA output pin. External bias (VCC) and matching for gain is required. 1 See pin 2 schematic UPB1008K LNA bias Vref Mixout1 Mixout2 GNDanalog IFin2 IFin1 VAGC VCC if 36 35 34 33 32 31 30 29 28 INTERNAL BLOCK DIAGRAM GND LNA 1 27 2ndIFoutl LNAin 2 26 2ndIFoutlb VCCrf 3 25 DCoffsetl GNDLO 4 24 DCoffsetlb 23 VCCbb 22 Imag 21 Isign 20 Qsign 19 Qmag /2 1stLO-OSC1 /4 5 Vth /2 1stLO-OSC2 6 VCCLO 7 PDout 8 PD /6/7 VCCdig 9 /2 8 2-bit ADC 2-bit ADC 17 18 DCoffsetQb GNDbb 14 2IFoutQ 36 Pin plastic QFN 16 13 PD Package UPB1008K DCoffsetQ 12 I/Q Balance Part Number 15 11 GNDdig ORDERING INFORMATION 2IFoutQb 10 REFin Vth OUTLINE DIMENSIONS (Units in mm) 6.2±0.2 Package Outline QFN-36 6.0±0.2 Actual size 6.0±0.2 6.2±0.2 6.2±0.2 6.0±0.2 6.4 6.0 3.8 0.5 Pin 36 Pin 1 4 -CO.5 0.22±0.05 0.14 -0.05 +0.10 6.2±0.2 6.0±0.2 1.0 MAX 0.55±0.2 0.5 Caution: The island pins located on the corners are needed to fabricate products in our plant, but do not serve any other function. Consequently the island pins should not be soldered and should remain non-connection pins. Life Support Applications These NEC products are not intended for use in life support devices, appliances, or systems where the malfunction of these products can reasonably be expected to result in personal injury. The customers of CEL using or selling these products for use in such applications do so at their own risk and agree to fully indemnify CEL for all damages resulting from such improper use or sale. 05/27/04 A Business Partner of NEC Compound Semiconductor Devices, Ltd.