NEC’s LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT UPB1009K DESCRIPTION The µPB1009K is a silicon monolithic IC developed for GPS receivers. This IC integrates a full VCO, second IF filter, 4-bit ADC, and digital control interface to reduce cost and mounting space. In addition, its power consumption is low. Moreover, use of a TCXO with frequency of 16.368 MHz/16.384 MHz, 14.4 MHz, 19.2 MHz, or 26 MHz switchable with an on-chip divider is possible. NEC’s stringent quality assurance and test procedures ensure the highest reliability and performance. FEATURES • Double conversion : fREFin = 16.368 MHz, f1stIFin = 61.380 MHz, f2ndIFin = 4.092 MHz • Multiple system clocks : On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096) : fREFin = 14.4, 16.384, 19.2, 26 MHz, f1stIFin = 62.980 MHz, f2ndIFin = 2.556 MHz • A/D converter : On-chip 4-bit A/D converter • High-density RF block : On-chip VCO tank circuit and 2ndIF filter • Supply voltage : VCC = 2.7 to 3.3 V • Low current consumption : ICC = 26.0 mA TYP. @ VCC = 3.0 V, N = 100 • High-density surface mountable : 44-pin plastic QFN APPLICATIONS • Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz • Consumer use GPS receiver of reference frequency 14.4, 16.384, 19.2, 26 MHz, 2ndIF frequency 2.556 MHz Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge. UPB1009K ORDERING INFORMATION Part Number µPB1009K-E1 Package 44-pin plastic QFN Supplying Form • 12 mm wide embossed taping • Pin 1 indicates pull-out direction of tape • Qty 1.5 kpcs/reel, Dry pack specification Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: µPB1009K 2 UPB1009K PRODUCT LINE-UP (TA = +25°C, VCC = 3.0 V) Type Part Number VCC (V) ICC (mA) 2.7 to 3.3 26.0 µPB1008K 2.7 to 3.3 LNA + Pre-amplifier + RF/IF down-converter + PLL synthesizer REF = 27.456 1stIF = 175.164/2ndIF = 0.132 On-chip 2-bit ADC 18.0 100 to 120 36-pin plastic QFN µPB1007K Pre-amplifier + RF/IF downconverter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 2.7 to 3.3 25.0 100 to 120 36-pin plastic QFN µPB1005K REF = 16.368 1stIF = 61.380/2ndIF = 4.092 Clock µPB1009K Frequency Specific 1 chip IC Functions (Frequency unit: MHz) Pre-amplifier + RF/IF downconverter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 REF = 14.4, 16.384, 19.2, 26 1stIF = 62.980/2ndIF = 2.556 On-chip 4-bit ADC CG (dB) Package Status 44-pin plastic QFN New Device Available 36-pin plastic QFN Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. SYSTEM APPLICATION EXAMPLE GPS receiver RF block diagram PD1 and PD2 in the figure are Power Save Mode control pins. MS1 and MS2 in the figure are TXCO (GPS, W-CDMA, PDC, GSM) control pins. RF LNA SAW 1stLo = 1636.8 MHz 1638.4 MHz 2ndIF = 4.092 MHz 2.556 MHz IF SAW Pre- 1st. amp mix 2nd MIX AGC LPF IF Amp – + DC trim + – RF 4bit ADC IF Para Data PD2 Regulator ÷25 PD1 ÷N Tank Cont. – + Samp Clk AGC cont GPS baseband RF = 1575.42 MHz 1stIF = 61.38 MHz 62.98 MHz PLL MS1 MS2 TCXO Caution This diagram schematically shows only the µPB1009K’s internal functions on the system. This diagram does not present the actual application circuits. 3 UPB1009K AGCout AGCin SCKin D3 D2 D1 D0 GNDsub VDDbuf VDDana GNDbuf PIN CONNECTION AND INTERNAL BLOCK DIAGRAM 33 32 31 30 29 28 27 26 25 24 23 VDDlogi 34 22 GNDana + + – GNDlogi 35 21 DCOFFin + – PD1 36 PD2 37 – 4bit ADC 20 DCOFFout Pwdctrl Logic 19 2ndIFin VGC IFamp LPF 1stIFin 38 18 2ndIFout 1/4 16 CLKout 3/64 1st IFout 41 9/256 1stMIXVCC 40 65/1024 17 IFGND 1/25 IFVCC 39 15 PLLGND PLL PD Fref 14 PLLVCC LNAVCC 42 LNAGND 43 13 Refin OSC 1stMIX PreAmp LNAin 44 4 12 MS2 1 2 3 4 5 6 7 8 9 10 11 LNAout Rext RegGND 1stMIXin GND (1st-MIX) MS1 LOVCC VCO1 VCO2 LOGND CPout CP UPB1009K PIN EXPLANATION Pin Name Function and Application 1 PreAMPout Output pin of preamplifier. 2 Rext Connect a resistor for the reference constant-current power supply to this pin. Ground this pin at 22 kΩ. 3 RegGND Ground pin for regulator. 42 PreAmpVCC Power supply voltage pin for preamplifier. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 43 PreAmpGND Ground pin of preamplifier. 44 PreAmpin Input pin of preamplifier. Internal Equivalent Circuit 1 44 43 4 1stMIXin 1stMIX input pin. 5 1stMIXGND Ground pin for first MIX. 40 1stMIXVCC Power supply voltage pin for RF mixer. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 41 1stIFout Output pin of RF mixer. Insert an IFSAW filter between this pin and pin 37. The VCO oscillation signal can be monitored on this pin. 42 Regulator Pin No. 2 3 40 Gibert Cell 41 4 Bias 5 5 UPB1009K 6 12 Pin Name MS1 MS2 Function and Application Low : 0 to 0.3 (V) MS1 : L MS2 : L High : VCC − 0.3 to MS1 : L TCXO : 19.2 MHz MS2 : H VCC (V) MS1 : H TCXO : 14.4 MHz MS2 : L Internal Equivalent Circuit 14 TCXO : 16.368, 16.384 MHz Bias Pin No. 12 6 11 CPout Bias MS1 : H TCXO : 26 MHz MS2 : H Output pin of charge pump. Connect external R and C to this pin to set a dumping factor and natural angular frequency (Isink = Isource = 0.45 mA). 15 Refin Reference frequency input pin. Connect an external reference transmitter (such as TCXO) to this pin. Bias 13 Source 14 11 PLLVCC Power supply voltage pin of PLL. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. Sink 14 15 PLLGND Ground pin of PLL. 16 CLKout Clock (fTCXO) output pin (IC test pin). 14 from divider 15 15 6 16 UPB1009K 7 8 9 10 Pin Name LoVCC VCO1 VCO2 LoGND Function and Application Internal Equivalent Circuit Power supply voltage pin of VCO. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 7 IC test pin. Leave this pin open when the µPB1009K is mounted on board. 8 VCO out VCO cont To divider Pin No. 9 Ground pin of VCO. 10 17 IFGND Ground pin of IF block. 18 2ndIFout Output pin of IF amplifier. 38 1stIFin Input pin of second IF mixer. 39 IFVCC Power supply voltage pin of IF block. 39 38 18 Bias 17 7 UPB1009K Pin No. Pin Name Function and Application 2ndIFin Input pin of ADC buffer amplifier. 20 DCOFFout Output pin of DC trimming OP amplifier. 21 DCOFFin DC trimming pulse input pin. Connect this pin to pin 20 via a capacitor to convert an input pulse signal into DC. 24 4.7 kΩ 6.8 kΩ 19 Internal Equivalent Circuit 1.8 kΩ 6.8 kΩ 19 22 22 23 GNDana GNDbuf Ground pin for OP amplifier and ADC power supply. 24 VDDana Power supply pin for OP amplifier and ADC comparator. 24 31 25 VDDbuf Power supply pin for output driver amplifier of ADC. Connect this pin to the ground pin of the A/D converter via a bypass capacitor to reduce the high-frequency impedance. PB 22 25 26 GNDsub Ground pin of CMOS substrate. A 27 28 29 30 D0 D1 D2 D3 Digital signal output pins. LSB = D0, MSB = D3 31 SCKin Sampling clock signal input pin. 32 AGCin AGC control pulse signal input pin. 33 AGCout AGC control signal output pin. 27 29 Y 28 30 inv 23 21 32 22 8 Bias 24 20 33 UPB1009K Pin No. Pin Name Function and Application 34 VDDlogi Power supply voltage pin for power control logic. 35 GNDlogi Ground pin for power control logic. 36 37 PD1 PD2 Low : 0 to 0.3 (V) PD1 : L PD2 : L High : VCC − 0.3 to PD1 : L Warm-up mode PD2 : H (PLL on). VCC (V) PD1 : H Calibration mode PD2 : L (PLL + IF + ADC on). Sleep mode (all circuits off). PD1 : H Active mode PD2 : H (all circuits on). Internal Equivalent Circuit 34 36 37 35 9 UPB1009K ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Symbol Test Conditions Ratings Unit VCC TA = +25°C 3.6 V ICCTotal TA = +25°C 100 mA Power Dissipation PD TA = +25°C 266 mW Operating Ambient Temperature TA −40 to +85 °C Storage Temperature Tstg −55 to +125 °C Total Circuit Current Note Note Mounted on double-sided copper-clad 50 × 50 × 1.6 mm epoxy glass PWB RECOMMENDED OPERATING RANGE Parameter Symbol MIN. TYP. MAX. Unit Supply Voltage VCC 2.7 3.0 3.3 V Operating Ambient Temperature TA −30 +25 +85 °C RF Input Frequency fRFin − 1 575.42 − MHz 1st LO Oscillating Frequency f1stLOin − 1 636.8/1 638.4 − MHz 1st IF Input Frequency f1stIFin − 61.38/62.98 − MHz 2nd LO Input Frequency f2ndLOin − 65.472/65.536 − MHz 2nd IF Input Frequency f2ndIFin − 4.092/2.556 − MHz Reference Input/Output Frequency fREFin fREFout − TCXO − MHz Clock mode control voltage (Low Level) VIL1 0 − 0.3 V Clock mode control voltage (High Level) VIH1 VCC − 0.3 − VCC V Power-down control voltage (Low Level) VIL2 0 − 0.3 V Power-down control voltage (High Level) VIH2 VCC − 0.3 − VCC V 10 UPB1009K POWER-DOWN CONTROL MODE The µPB1009K consists of an RF block, an IF block, and a PLL block. By controlling reduction of power to each block (by applying a voltage to the PD1 and PD2 pins), the following four modes can be used. Mode No. Mode Name 1 Test Conditions RF Block IF Block (IF + ADC) PLL Block PD1 PD2 Active mode L H ON ON ON 2 Calibration mode H H OFF ON ON 3 Warm-up mode H L OFF OFF ON 4 Sleep mode L L OFF OFF OFF Caution To use only the active mode and sleep mode, fix PD1 to L and select the desired mode with PD2. REFERENCE CLOCK CONTROL MODE The divided frequency can be selected as follows so that it can be shared with the TCXO of each system. TCXO Frequency Test Conditions 1/N Phase Comparison Frequency PD1 PD2 16.368 MHz (GPS) 16.384 MHz (GPS) L L 1/100 16.368 MHz 16.384 MHz 19.2 MHz (W-CDMA) L H 3/256 19.2 MHz 14.4 MHz (PDC) H L 9/1024 14.4 MHz 26 MHz (GSM) H H 65/4096 26 MHz Caution When the reference clock frequency is 16.368 MHz, the 1stIF frequency and 2ndIF frequency are 61.38 MHz and 4.092 MHz, respectively. They are respectively 62.98 MHz and 2.556 MHz in all other cases. 11 UPB1009K ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V) Parameter Rest current of overall IC in each mode Sleep mode Note Symbol Test Conditions MIN. TYP. MAX. Unit Rest status without input signal, including sampling clock. MS1 = L, MS2 = L Is PD1 = L, PD2 = L 1.3 2.2 3.5 mA Warm-up mode Iw PD1 = H, PD2 = L 10.5 13.0 15.5 mA Calibration mode Ic PD1 = H, PD2 = H 18.0 22.0 25.3 mA Active mode Ia PD1 = L, PD2 = H 22.1 26.0 30.0 mA Rest current of PLL block in each clock mode Current of PLL block. Overall current in calibration mode and active mode increases from that in basic mode (MS1 = L, MS2 = L). PD1 = H, PD2 = L. Current when 1/100 divider is used Iw1 MS1 = L, MS2 = L 5.3 6.5 7.6 mA Current when 256/3 divider is used Iw2 MS1 = L, MS2 = H 9.7 11.3 12.6 mA Current when 1024/9 divider is used Iw3 MS1 = H, MS2 = L 10.2 12.1 13.5 mA Current when 4096/65 divider is used Iw4 MS1 = H, MS2 = H 10.4 12.3 13.9 mA H application − − 20 µA L application −20 − − µA H application − − 20 µA L application −20 − − µA H application − − 1 µA L application −1 − − µA H application − − 1 µA L application −1 − − µA Maximum mode control pin current 6 pin MS1 12 pin MS2 36 pin PD1 37 pin PD2 <Pre-amplifier> fRFin = 1 575.42 MHz Circuit Current 1 ICC1 No Signals, 1-pin current 1.9 2.3 2.7 mA Power Gain GLNA PRFin = −40 dBm 12.5 15.0 17.5 dB Noise Figure NFLNA fRFin = 1 575 MHz − 3.0 3.5 dB −4.0 −2.7 − dBm Saturated Output Power PO(SAT)LNA PRFin = −10 dBm Input 1dB Compression Level PLNA−1 fRFin = 1 575.42 MHz −25 −21.8 − dBm Input 3rd Order Intercept Point IIP3LNA fRFin = 1 575.42 MHz, 1 576.42 MHz −12 −9.5 − dBm Input Inpedance ZinLNA − 11.2 − j21.5 − Ω Output Inpedance ZoutLNA Calculated from S-parameter where input DC cut capacitance = 1 nF, output load L = 100 n, and DC cut capacitance = 1 nF − 16.4 − j136.6 − Ω Note Most of the current flows into the ADC ladder resistor (VDDana → GNDana) in the sleep mode, and the sleep mode current between other VCC (VDD) and GND is 10 µA maximum. 12 UPB1009K ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V) Parameter <RF mixer> Circuit Current 2 RF Conversion Gain Symbol Test Conditions MIN. TYP. MAX. Unit fRF = 1 575.42 MHz, f1stLOin = 1 636.80 MHz, f1stIF = 61.38 MHz ICC2 CGRF No Signals, 40 pin current 2.0 2.5 3.0 mA PRFMIXin = −40 dBm 14.0 16.1 19.0 dB − 12.8 16.0 dB −4.0 −0.8 − dBm Noise Figure SSBNFRFMIX SSBNF = 10*log (2*DSBNF (Linear value) −1) MHz Maximum IF Output PO (SAT) RFMIX PRFMIXin = −10 dBm Input 1dB Compression Level PRFMIX-1 fRFMIXin = 1 575.42 MHz −29.0 −25.5 − dBm Input 3rd Order Intercept Point IIP3RFMIX fRFMIXin = 1 575.42 MHz, 1 576.42 MHz f1stLO = 1 636.8 MHz −19.0 −17.2 − dBm − −34.5 −30 dBm − −54.7 −30 dBm − 50.1 − j22.3 − Ω − 57.3 + j2.6 − Ω 6.3 7.3 8.5 mA CG (GV) IF VAGC = 0.5 V 66.0 70.3 75.0 dB VAGC = 1.5 V 45.0 51.2 58.0 dB VAGC = 2.5 V 19.5 26.4 33.5 dB − 0.7 1.0 dB LO Leakage to IF Pin LOIF LO Leakage to RF Pin LORF Input Inpedance ZinMIX Output Inpedance ZoutMIX <IF mixer, LPF, IFamp> Circuit Current 3 IF Conversion Gain Leakage of 1 636.8 MHz frequency when VCO oscillates correctly. Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 1 nF f1stFin = 61.38 MHz, f2ndLOin = 65.472 MHz, ZL = 2 kΩ ICC3 No Signals, 39 pin current In Band Gain Fluctuation ∆CG1 3.092 to 5.092 MHz Out Of Band Attenuation ∆CG2 Gain difference at 4.092 MHz and 9.092 MHz, VAGC = 0.5 V 20.0 25.0 − dB Conversion Gain Range CGRange VAGC = 0 to 2.5 V 32.5 43.9 − dB − 13.7 17.5 dB 1.0 1.3 − VPP VAGC = 0.5 V −70.5 −64.4 − dBm VAGC = 1.5 V −53.5 −44.9 − dBm VAGC = 2.5 V −37.0 −30.6 − dBm f1stIFin1 = 61.28 MHz VAGC = 0.5 V −56.0 −51.3 − dBm f1stIFin2 = 61.38 MHz VAGC = 1.5 V −38.0 −30.7 − dBm f2ndLO = 65.472 MHz VAGC = 2.5 V −27.0 −21.4 − dBm − 69.3 − j4.8 − Ω − 163 + j3.8 − Ω IF ⋅ SSB Noise Figure Maximum 2ndIF Output Input 1dB Compression Level Input 3rd Order Intercept Point NFIF VO (SAT) IF PIF-1 IIP3IF Input Inpedance ZinIF Output Inpedance ZoutIF VAGC = 0.5 V (at maximum gain) Pin = −50 dBm, VAGC = 0.5 V f1stIFin = 61.38 MHz Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 100 nF 13 UPB1009K ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 8.0 9.5 10.6 mA −0.55 −0.45 −0.35 mA Icpsource 0.35 0.45 0.55 mA Loop Filer Output (High Level) VOH VCC−0.3 − − V Loop Filer Output (Low Level) VOL − − 0.2 V VREFin − 0.2 1.6 VPP − 100 − MHz <PLL Synthesizer> Circuit Current 4 ICC4 PLL, VCO current, MS1 = L, MS2 = L Charge Pump Output Current Icpsink V13 pin = VCC/2 Reference Input Level VCO Modulation Sensitivity KV Center frequency VCO Control Voltage VT When PLL is Locked 0.5 1.3 2.0 V C/N C/N ∆10 kHz 70.0 81.0 − dBc/Hz ICC5 3.1 4.1 5.4 mA ResAD − 4 − bits fs − − 20 MHz ADBW 5.1 − − MHz − 0.2 1.0 LSB <A/D Converter> Circuit Current 5 Resolution Sampling Clock Input Band Width Integral Non-linear Error INL DC characteristics Signal-to-noise Ratio SNR IF = 5.17 MHz, fs = 20.48 MHz 22.0 25.3 − dB Signal-to-noise + Distortion Ratio SINAD IF = 5.17 MHz, fs = 20.48 MHz 20.0 25.1 − dB Number ENOB ENOB = (SINAD−1.763)/6.02 3.0 3.9 − bits − −40 −30 dBc Total Harmonic Distortion Ratio THD IF = 5.17 MHz, fs = 20.48 MHz Second-degree to fifth-degree distortion components Remarks 1. Timing characteristics of ADC during normal operation A buffer amplifier is internally inserted before the ADC core of the µPB1009K. The bias of this buffer amplifier is controlled by the signal input from the DC trim pin, and is used to eliminate the DC offset of the ADC. Because the ladder resistor of the ADC is directly connected between VDDana and GNDana, changes in VDDana affect the resolution of the ADC. 14 UPB1009K As illustrated in the operation timing chart below, the data of SampleN is pipeline delayed by 1.5 clocks during normal operation, and is output at the rising edge of the sample clock with output delay time Tod. When the operation is changed from normal operation to power-down operation, the status of the output data immediately before the power-down operation is retained (drive status). (a) Normal Operation SampleN SampleN+2 SampleN+1 2ndIFin SampleN+3 SampleN+4 SampleN+5 Tclk Tds Tch Tcl SCKin Tpld Tds Toh D0-D3 N-2 N-1 N N+1 N+2 N+3 : Analog signal sampling timing The following table shows each timing parameter for reference purposes. Symbol Parameter Test Conditions MIN. TYP. MAX. Unit CL = 10 pF, fclk = 19.2 MHz − − 12 ns Tod Output Delay Tpld Pipeline Delay − 1.5 − clock Tds Sampling Delay (Aperture Delay) − 2 − ns Toh Output Hold Time 2 − − ns 15 UPB1009K Remarks 2. Power-down timing characteristics of ADC The output code of the ADC of the µPB1009K is undefined for 7.5 clocks after the power-down signal is cleared when the ADC returns from the power-down status to normal operation. (b) Power-down Operation PDB N N+1 2ndIFin SCKin D0-D3 N undefined Note N+1 : Analog signal sampling timing Note The output data is undefined from the start of the power-down operation to the 7.5th clock from the falling edge of the clock at which the power-down operation is cleared. 16 UPB1009K TYPICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V, unless otherwise specified) ⎯ IC TOTAL CHARACTERISTICS ⎯ TOTAL CIRCUIT CURRENT vs. SUPPLY VOLTAGE Total Circuit Current ICCTotal (mA) 35 30 25 TA = +85˚C +25˚C –40˚C 20 15 10 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Supply Voltage VCC (V) Remark The graphs indicate nominal characteristics. 17 UPB1009K ⎯ PRE-AMPLIFIER BLOCK CHARACTERISTICS ⎯ PREAMP GAIN vs. FREQUENCY OUTPUT POWER vs. INPUT POWER –10 –15 –20 –25 –30 –50 Noise Figure NFLNA (dB) 10 Power Gain GLNA (dB) –5 20 TA = +85˚C +25˚C –40˚C –40 –30 –20 –10 –10 –20 TA = +85˚C +25˚C –40˚C –40 100 300 500 700 900 1 100 1 300 1 500 1 700 1 900 2 000 0 Input Power Pin (dBm) Frequency f (MHz) PREAMP NOISE FIGURE vs. FREQUENCY PREAMP IM CHARACTERISTICS 5.0 0 4.5 –10 4.0 TA = +85˚C 3.5 +25˚C 3.0 –40˚C 2.5 2.0 –20 –30 –40 –50 –60 1.5 –70 1.0 1 545 1 555 1 565 1 575 1 585 1 595 1 605 1 615 –80 –45 –40 Frequency f (MHz) Remark The graphs indicate nominal characteristics. 18 0 –30 Output Power Pout (dBm) Output Power Pout (dBm) 0 TA = +85˚C +25˚C –40˚C –35 –30 –25 –20 –15 –10 Input Power Pin (dBm) –5 UPB1009K ⎯ RF MIX BLOCK CHARACTERISTICS ⎯ OUTPUT POWER vs. INPUT POWER RF MIX IM CHARACTERISTICS 0 –10 –5 Output Power Pout (dBm) Output Power Pout (dBm) 0 –10 –15 –20 TA = +85˚C +25˚C –40˚C –25 –30 –45 –35 –25 –15 –5 –40 –50 –60 –80 –50 –45 5 TA = +85˚C +25˚C –40˚C –40 –35 –30 –25 –20 –15 –10 Input Power Pin (dBm) Input Power Pin (dBm) RF CONVERSION GAIN vs. FREQUENCY CHARACTERISTICS RF NOISE FIGURE vs. FREQUENCY CHARACTERISTICS 25 20 RF Noise Fingure SSBNFRFMIX (dB) RF Conversion Gain CGRF (dB) –30 –70 25 TA = +85˚C +25˚C 15 –40˚C 10 5 30 –20 40 50 60 70 80 90 Frequency f (MHz) 20 15 TA = +85˚C +25˚C –40˚C 10 5 30 40 50 60 70 80 90 Frequency f (MHz) Remark The graphs indicate nominal characteristics. 19 UPB1009K ⎯ IF BLOCK CHARACTERISTICS ⎯ 10 10 0 Output Power Pout (dBm) 15 5 0 –5 TA = +85˚C +25˚C –40˚C –10 –15 –85 –80 –75 –70 –65 –60 –55 IF-SSB Noise Figure NFIF (dB) –70 –65 –55 –60 –50 IF CONVERSION VOLTAGE GAIN vs. 2ndIF FREQUENCY 30 20 10 2 6 4 8 10 12 2ndIF Frequency f (MHz) 80 70 60 50 40 30 20 TA = +85˚C +25˚C –40˚C 10 0.5 1.0 1.5 2.0 2.5 80 70 60 50 40 30 20 TA = +85˚C +25˚C –40˚C 10 0 0.5 2.5 4.5 6.5 8.5 2ndIF Frequency f (MHz) IF CONVERSION VOLTAGE GAIN vs. AGC VOLTAGE IF Conversion Voltage Gain CG (GV) IF (dB) TA = +85˚C +25˚C –40˚C IF-SSB NOISE FIGURE vs. 2ndIF FREQUENCY 40 0 –40 Input Power Pin (dBm) 50 0 –30 –60 –75 –50 TA = +85˚C +25˚C –40˚C 0 –20 Input Power Pin (dBm) 60 0 –10 –50 70 3.0 3.5 AGC Voltage VAGC (V) Remark The graphs indicate nominal characteristics. 20 IF IM CHARACTERISTICS IF Conversion Voltage Gain CG (GV) IF (dB) Output Power Pout (dBm) OUTPUT POWER vs. INPUT POWER 10.5 11.5 UPB1009K ⎯ VCO MODULATION SENSITIVITY CHARACTERISTICS ⎯ VCO CONTROL VOLTAGE vs. VCO FREQUENCY VCO Control Voltage VT (V) 3.0 2.5 TA = +85˚C +25˚C –40˚C 2.0 1.5 1.0 0.5 0 1 300 1 400 1 500 1 600 1 700 1 800 1 900 VCO Frequency fVCO (MHz) ⎯ C/N CHARACTERISTICS ⎯ Ref = –10 dBm Atten 5 dB Center = 1.637 GHz Res BW 1 kHz Ref = –10 dBm VBW 1 kHz Atten 5 dB Center = 1.637 GHz Res BW 1 kHz VBW 1 kHz Mkr1 = 10.0 kHz Noise –81.78 dB/Hz Span 100 kHz Sweep 300 ms (401 pts) Ref = –10 dBm Atten 5 dB Center = 1.637 GHz Res BW 1 kHz VBW 1 kHz Mkr1 = 10.0 kHz Noise –81.92 dB/Hz Span 100 kHz Sweep 300 ms (401 pts) Mkr1 = 10.0 kHz Noise –81.23 dB/Hz Span 100 kHz Sweep 300 ms (401 pts) Remark The graphs indicate nominal characteristics. 21 UPB1009K ⎯ SINAD CHARACTERISTICS OF A/D CONVERTOR (IFin = 5.17 MHz, SCLKin = 20.48 MHz) ⎯ +10 +10 0 AMPLITUDE (dB) –10 –20 –30 –40 –50 –30 –40 –50 –70 –70 2 4 6 8 10 12 TA = +85˚C SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 43.7 dB ENOB = 3.92 bit THD = –42.1 dBc 0 –10 –20 –30 –40 –50 –60 –70 –80 0 2 4 6 8 10 –80 0 2 4 6 8 10 ANALOG INPUT FREQUENCY (MHz) +10 AMPLITUDE (dB) –20 –60 ANALOG INPUT FREQUENCY (MHz) 12 ANALOG INPUT FREQUENCY (MHz) Remark The graphs indicate nominal characteristics. 22 –10 –60 –80 0 TA = –40˚C SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 41.1 dB ENOB = 3.91 bit THD = –40.4 dBc 0 AMPLITUDE (dB) TA = +25˚C SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 42.3 dB ENOB = 3.91 bit THD = –40.9 dBc 12 UPB1009K 21 20 19 18 17 16 15 AGCout AGCin SCKin D3 D2 D1 D0 MEASUREMENT CIRCUIT 100 kΩ 100 nF VCC 100 kΩ 82 pF 100 nF 32 33 31 30 29 28 27 26 25 24 23 VCC 34 22 82 pF 35 22 PD1 + – + 100 nF 50 Ω 19 IFamp LPF 38 39 17 40 16 9/256 1 nF 65/1024 41 3/64 25 1stIFout VCC CLKout 10 1 nF 15 PLL PD 82 pF 100 nF VCC Fref 14 42 100 nF 2ndIFout 11 2 kΩ 100 nF 82 pF 1/25 100 nF 2ndIFin 12 100 nF 18 1/4 1 nF VCC DCOFFout 13 20 Pwdctrl Logic VGC 24 1stIFin DCOFFin 14 100 nF 100 kΩ + – 37 100 kΩ 21 4bit ADC 36 23 PD2 – 82 pF 43 13 OSC 1stMIX PreAmp 1 PreAmpin 44 12 CP 1 nF 7 pF REFin 9 1 nF MS2 8 3.9 nH 1 2 3 4 5 6 7 9 8 10 100 pF VCC 22 kΩ VCC 1 nF 1 nF 100 nF 100 nF 1 nF 100 pF 3.9 nH 750 F 82 pF 1 nF 1 kΩ 8.2 nF 1.5 kΩ 10 kΩ 1stMIXin MS1 Presin VCOc CPout 10 kΩ 100 nF PreAmpout 1 nF 11 2 3 4 5 6 7 23 UPB1009K DESCRIPTION OF PINS OF TEST CIRCUIT Pin No. 24 Pin Function Pin Name Pin No. Pin Function Pin Name 1 Preamplifier Input PreAmpin 14 DC Offset Input DCOFFin 2 Preamplifier Output PreAmpout 15 Digital Signal Output Pin D0 3 RF Mixer Input 1stMIXin 16 D1 4 MS1 MS1 17 D2 5 Prescaler Input Presin 18 D3 6 VCO Power Control Pin VCOc 19 Sampling Signal Input SCKin 7 VT Measurement Pin (Charge Pump CPout Output) 20 AGC Input AGCin 8 MS2 MS2 21 AGC Control Voltage Output AGCout 9 Reference Clock Input REFin 22 PD1 Output (Default onboard : GND) PD1 10 Clock Output CLKout 23 PD1 Output (Default on board : VCC) PD2 11 2ndIF Output 2ndIFout 24 1stIF Input 1stIFin 12 2ndIF Input 2ndIFin 25 1stIF Output 1stIFout 13 DC Offset Output DCOFFout UPB1009K DCOFF D0 D1 D2 D3 AGCout SCLKout APPLICATION CIRCUIT 100 kΩ 100 nF VCC 100 nF 33 82 pF 32 31 30 29 28 27 26 25 24 23 100 kΩ VCC 34 22 82 pF 35 RFPD1 36 RFPD2 37 + – + 100 nF 19 IFamp LPF 100 nF 18 1/4 39 17 40 16 9/256 65/1024 41 3/64 1/25 82 pF 1 nF VCC 20 Pwdctrl Logic 1 nF 100 nF 100 nF + – 38 VCC CLKout 1 nF 15 PLL PD 82 pF 100 nF VCC Fref 14 42 100 nF 21 4bit ADC VGC IFSAW – 82 pF 43 13 OSC 1stMIX PreAmp 44 REFin 1 nF MS2 12 CP 7 pF 1 3.9 nH 2 3 4 5 6 7 11 10 100 pF VCC 1 nF 9 8 82 pF 4.7 nH 22 kΩ 1 nF 100 nF RFSAW 1 nF 8.2 nF 100 nF 500 F 1 pF 1.5 kΩ VCC 510 Ω VCC in AMP MS1 out 5.6 nH 3.9 nH 100 nF 100 nF 10 nF RFin TopSAW PD1 PD2 0 0 1 Power-down mode MS1 MS2 TCXO N Sleep mode (full off) 0 0 16.368/16.384 MHz 100 0 Warm-up mode (PLL on) 0 1 19.2 MHz 256/3 1 1 Calibration mode (PLL on) 1 0 14.4 MHz 1024/9 0 1 Active mode (full on) 1 1 26.0 MHz 4096/65 25 UPB1009K PACKAGE DIMENSIONS 44-PIN PLASTIC QFN (UNIT: mm) 6.2±0.2 6.0±0.2 6.2±0.2 6.0±0.2 6.2±0.2 6.0±0.2 44 Pin 1 Pin (Bottom View) 6.2±0.2 6.0±0.2 0.55±0.2 1.0MAX. 0.14+0.10 –0.05 0.18±0.05 0.4 Caution The island pins located on the corners are needed to fabricate products in our plant, but do not serve any other function. Consequently the island pins should not be soldered and should remain non-connection pins. 26 UPB1009K NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent abnormal oscillation). (3) Keep the wiring length of the ground pins as short as possible. (4) Connect a bypass capacitor to the VCC pin. (5) High-frequency signal I/O pins must be coupled with the external circuit using a coupling capacitor. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your nearby sales office. Soldering Method Soldering Conditions Condition Symbol Infrared Reflow Peak temperature (package surface temperature) Time at peak temperature Time at temperature of 220°C or higher Preheating time at 120 to 180°C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) : 260°C or below : 10 seconds or less : 60 seconds or less : 120±30 seconds : 3 times : 0.2%(Wt.) or below IR260 VPS Peak temperature (package surface temperature) Time at temperature of 200°C or higher Preheating time at 120 to 150°C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) : 215°C or below : 25 to 40 seconds : 30 to 60 seconds : 3 times : 0.2%(Wt.) or below VP215 Wave Soldering Peak temperature (molten solder temperature) Time at peak temperature Preheating temperature (package surface temperature) Maximum number of flow processes Maximum chlorine content of rosin flux (% mass) : 260°C or below : 10 seconds or less : 120°C or below : 1 time : 0.2%(Wt.) or below WS260 Partial Heating Peak temperature (pin temperature) Soldering time (per side of device) Maximum chlorine content of rosin flux (% mass) : 350°C or below : 3 seconds or less : 0.2%(Wt.) or below HS350 Caution Do not use different soldering methods together (except for partial heating). Life Support Applications These NEC products are not intended for use in life support devices, appliances, or systems where the malfunction of these products can reasonably be expected to result in personal injury. The customers of CEL using or selling these products for use in such applications do so at their own risk and agree to fully indemnify CEL for all damages resulting from such improper use or sale. 12/04/2003 A Business Partner of NEC Compound Semiconductor Devices, Ltd. 27