EN6360QI

Enpirion® Power Datasheet
EN6360QI 8A PowerSoC
Highly Integrated Synchronous
DC-DC Buck with Integrated Inductor
Description
Features
The EN6360QI is a Power System on a Chip
(PowerSoC) DC to DC converter with an integrated
inductor,
PWM
controller,
MOSFETs
and
compensation to provide the smallest solution size in
an 8x11x3mm 68 pin QFN module. It offers high
efficiency, excellent line and load regulation over
temperature and up to the full 8A load range. The
EN6360QI is specifically designed to meet the
precise voltage and fast transient requirements of
high-performance, low-power processor, DSP, FPGA,
memory boards and system level applications in
distributed power architecture. The EN6360QI
features switching frequency synchronization with an
external clock or other EN6360QIs for parallel
operation. Other features include precision enable
threshold, pre-bias monotonic start-up, and
programmable soft-start. The device’s advanced
circuit techniques, ultra high switching frequency, and
proprietary integrated inductor technology deliver
high-quality, ultra compact, non-isolated DC-DC
conversion.
The Altera Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity by
offering greatly simplified board design, layout and
manufacturing requirements. All Altera Enpirion
products are RoHS compliant and lead-free
manufacturing environment compatible.
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High Efficiency (Up to 96%)
Excellent Ripple and EMI Performance
Up to 8A Continuous Operating Current
Input Voltage Range (2.5V to 6.6V)
Frequency Synchronization (Clock or Primary)
1.5% VOUT Accuracy (Over Load and Temperature)
Optimized Total Solution Size (190mm2)
Precision Enable Threshold for Sequencing
Programmable Soft-Start
Master/Slave Configuration for Parallel Operation
Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltage Protection
• RoHS Compliant, MSL Level 3, 260°C Reflow
Applications
• Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
• Blade Servers, RAID Storage and LAN/SAN
Adapter Cards, Wireless Base Stations, Industrial
Automation, Test and Measurement, Embedded
Computing, and Printers
• High Efficiency 12V Intermediate Bus Architectures
• Beat Frequency/Noise Sensitive Applications
Efficiency vs. Output Current
VOUT
VIN
2x
47µF
1206
ENABLE
EN6360QI
2x
22µF
1206
AVIN
SS
RA
VFB
15nF
90
CA
R1
PGND
PGND
100
VOUT
AGND
FQADJ
RB
80
EFFICIENCY (%)
PVIN
70
Actual Solution Size
190mm2
60
CONDITIONS
VIN = 5.0V
50
40
30
VOUT = 3.3V
20
VOUT = 1.2V
10
RFQADJ
0
0
Figure 1. Simplified Applications Circuit
1
2
3
4
5
OUTPUT CURRENT (A)
6
7
8
Figure 2. Highest Efficiency in Smallest Solution Size
www.altera.com/enpirion
06489
March 24, 2015
Rev G
EN6360QI
Ordering Information
Part Number
EN6360QI
EVB-EN6360QI
Package Markings
EN6360QI
EN6360QI
Temp Rating (°C)
-40 to +85
Package Description
68-pin (8mm x 11mm x 3mm) QFN T&R
QFN Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
NC
NC(SW)
EN_PB
FQADJ
NC
VSENSE
SS
EAOUT
VFB
M/S
AGND
AVIN
61
60
59
58
57
56
55
54
53
52
S_OUT
NC(SW)
63
62
49
NC
64
ENABLE
NC
65
POK
NC
51
NC
67
66
50
NC
68
Pin Assignments (Top View)
48
KEEP OUT
1
S_IN
BGND
NC
2
47
NC
3
46
VDDB
NC
4
45
NC
44
NC
43
PVIN
42
PVIN
5
NC
6
NC
7
NC
8
NC
9
NC
NC
KEEP OUT
KEEP OUT
NC
69
PGND
34
PGND
PGND
PGND
32
31
PGND
33
30
PGND
PGND
28
29
PGND
27
NC(SW)
NC(SW)
26
NC
VOUT
24
PVIN
25
35
VOUT
14
23
NC
22
PVIN
VOUT
36
VOUT
13
21
NC
20
PVIN
VOUT
12
19
NC
VOUT
PVIN
37
18
38
VOUT
11
VOUT
PVIN
16
39
17
10
VOUT
PVIN
15
PVIN
40
NC
41
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 11 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN
NAME
1-15, 25,
44-45,
59, 64-68
NC
16-24
VOUT
FUNCTION
NO CONNECT: These pins must be soldered to PCB but not electrically connected to each
other or to any external signal, voltage, or ground. These pins may be connected internally.
Failure to follow this guideline may result in device damage.
Regulated converter output. Connect to the load and place output filter capacitor(s) between
these pins and PGND pins 28 to 31.
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EN6360QI
PIN
NAME
26-27,
62-63
NC(SW)
28-34
PGND
35-43
PVIN
46
VDDB
47
BGND
48
S_IN
49
S_OUT
50
POK
51
ENABLE
52
AVIN
53
AGND
54
M/S
55
VFB
56
EAOUT
57
SS
58
VSENSE
60
FQADJ
61
EN_PB
69
PGND
FUNCTION
NO CONNECT: These pins are internally connected to the common switching node of the
internal MOSFETs. They must be soldered to PCB but not be electrically connected to any
external signal, ground, or voltage. Failure to follow this guideline may result in device damage.
Input and output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. Refer to VOUT, PVIN descriptions and Layout Recommendation for
more details.
Input power supply. Connect to input power supply and place input filter capacitor(s) between
these pins and PGND pins 32 to 34.
Internal regulated voltage used for the internal control circuitry. Decouple with an optional
0.1µF capacitor to BGND for improved efficiency. This pin may be left floating if board space is
limited.
Ground for VDDB. Refer to pin 46 description.
Digital input. A high level on the M/S pin will make this EN6360QI a Slave and the S_IN will
accept the S_OUT signal from another EN6360QI for parallel operation. A low level on the M/S
pin will make this device a Master and the switching frequency will be phase locked to an
external clock. Leave this pin floating if it is not used.
Digital output. A low level on the M/S pin will make this EN6360QI a Master and the internal
switching PWM signal is output on this pin. This output signal is connected to the S_IN pin of
another EN6360QI device for parallel operation. Leave this pin floating if it is not used.
POK is a logic level high when VOUT is within -10% to +20% of the programmed output
voltage (0.9VOUT_NOM ≤ VOUT ≤ 1.2VOUT_NOM). This pin has an internal pull-up resistor to AVIN
with a nominal value of 94kΩ.
Device enable pin. A high level or floating this pin enables the device while a low level disables
the device. A voltage ramp from another power converter may be applied for precision enable.
Refer to Power Up Sequencing
Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)
at a quiet point. Can also be connected to an auxiliary supply within a voltage range that is
sequencing.
The quiet ground for the control circuits. Connect to the ground plane with a via right next to the
pin.
Ternary (three states) input pin. Floating this pin disables parallel operation. A low level
configures the device as Master and a high level configures the device as a Slave. A REXT
resistor is recommended to pulling M/S high. Refer to Ternary Pin description in the Functional
Description section for REXT values. Also refer to S_IN and S_OUT pin descriptions.
This is the external feedback input pin. A resistor divider connects from the output to AGND.
The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor (CA) and
resistor (R1) are required parallel to the upper feedback resistor (RA). The output voltage
regulation is based on the VFB node voltage equal to 0.600V. For Slave devices, leave VFB
floating.
Error amplifier output. Allows for customization of the control loop. May be left floating.
A soft-start capacitor is connected between this pin and AGND. The value of the capacitor
controls the soft-start interval. Refer to Soft-Start in the Functional Description for more details.
This pin senses output voltage when the device is in pre-bias (or back-feed) mode. Connect
VSENSE to VOUT when EN_PB is high or floating. Leave floating when EN_PB is low.
Frequency adjust pin. This pin must have a resistor to AGND which sets the free running
frequency of the internal oscillator.
Enable pre-bias input. When this pin is pulled high, the device will support monotonic start-up
under a pre-biased load. VSENSE must be tied to VOUT for EN_PB to function. This pin is
pulled high internally. Enable pre-bias feature is not available for parallel operations.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heatsinking purposes. Refer to Layout Recommendation section.
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06489
March 24, 2015
Rev G
EN6360QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Voltages on : PVIN, AVIN, VOUT
-0.3
7.0
V
Voltages on: EN, POK, M/S
-0.3
VIN+0.3
V
Voltages on: VFB, EXTREF, EAOUT, SS, S_IN, S_OUT, FQADJ
-0.3
2.5
V
-65
150
°C
150
°C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
ESD Rating (based on CDM)
500
V
Storage Temperature Range
TSTG
Maximum Operating Junction Temperature
TJ-ABS Max
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
2.5
6.6
V
Output Voltage Range (Note 1)
VOUT
0.60
VIN – VDO
V
Output Current
IOUT
8
A
Input Voltage Range
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Thermal Characteristics
SYMBOL
TYP
UNITS
Thermal Resistance: Junction to Ambient (0 LFM) (Note 2)
PARAMETER
θJA
15
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
1.0
°C/W
Thermal Shutdown
TSD
150
°C
Thermal Shutdown Hysteresis
TSDH
20
°C
Note 1: VDO (dropout voltage) is defined as (ILOAD x Dropout Resistance). Please refer to Electrical Characteristics Table.
Note 2: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
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06489
March 24, 2015
Rev G
EN6360QI
Electrical Characteristics
NOTE: VIN=6.6V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
Operating Input
Voltage
VIN
VFB Pin Voltage
VVFB
TEST CONDITIONS
MIN
TYP
2.5
MAX
UNITS
6.6
V
Internal Voltage Reference at:
VIN = 5V, ILOAD = 0, TA = 25°C
0.594
0.600
0.606
V
VFB Pin Voltage (Load
VVFB
and Temperature)
0A ≤ ILOAD ≤ 8A
Starting Date Code: X501 or greater
0.591
0.600
.609
V
VFB Pin Voltage
(Line, Load and
Temperature)
2.5V ≤ VIN ≤ 6.6V
0A ≤ ILOAD ≤ 8A
0.588
0.600
0.612
V
10
nA
VVFB
VFB Pin Input Leakage
IVFB
Current
VFB Pin Input Leakage Current
(Note 4)
Shut-Down Supply
Current
IS
Power Supply Current with
ENABLE=0
1.5
mA
Under Voltage Lockout – VIN Rising
VUVLOR
Voltage Above Which UVLO is Not
Asserted
2.2
V
Under Voltage Lockout – VIN Falling
VUVLOF
Voltage Below Which UVLO is
Asserted
2.1
V
VINMIN – VOUT at Full Load
400
800
mV
Input to Output Resistance
50
100
mΩ
8
A
Drop Out Voltage
VDO
Drop Out Resistance
RDO
Continuous Output
Current
IOUT_SRC
Over Current Trip
Level
IOCP
Sourcing Current
Switching Frequency
FSW
RFADJ = 4.42 kΩ, VIN = 5V
External SYNC Clock
Frequency Lock
Range
FPLL_LOCK
SYNC Clock Input Frequency
Range
S_IN Clock Amplitude
– Low
VS_IN_LO
SYNC Clock Logic Low
S_IN Clock Amplitude
– High
VS_IN_HI
-10
0
16
A
0.9
1.2
1.5
MHz
0.9*Fsw
Fsw
1.1*Fsw
MHz
0
0.8
V
SYNC Clock Logic High
1.8
2.5
V
S_IN Clock Duty Cycle
DCS_INPLL
(PLL)
M/S Pin Float or Low
20
80
%
S_IN Clock Duty Cycle
DCS_INPWM
(PWM)
M/S Pin High
10
90
%
Pre-Bias Level
VPB
Allowable Pre-bias as a Fraction of
Programmed Output Voltage for
Monotonic start up. Minimum Prebias Voltage = 300mV.
20
75
%
Non-Monotonicity
VPB_NM
Allowable Non-monotonicity Under
Pre-bias Startup
VOUT Range for POK =
High
Range of Output Voltage as a
Fraction of Programmed Value
When POK is Asserted. (Note 3)
100
90
mV
120
%
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06489
March 24, 2015
Rev G
EN6360QI
PARAMETER
SYMBOL
TEST CONDITIONS
POK Deglitch Delay
Falling Edge Deglitch Delay After
Output Crossing 90% level.
FSW=1.2 MHz
VPOK Logic Low level
With 4mA Current Sink into POK Pin
MIN
TYP
MAX
213
UNITS
µs
0.4
V
VPOK Logic high level
VIN
V
POK Internal pull-up
resistor
94
kΩ
+/-10
%
Current Balance
VOUT Rise Time
Accuracy
∆IOUT
∆TRISE
(Note 4)
With 2 to 4 Converters in Parallel,
the Difference Between Nominal
and Actual Current Levels.
∆VIN<50mV; RTRACE< 10 mΩ,
Iload= # Converter * IMAX
tRISE [ms] = CSS [nF] x 0.065;
10nF ≤ CSS ≤ 30nF;
(Note 5 and Note 6)
-25
+25
%
2.5V ≤ VIN ≤ 6.6V;
1.2
VIN
V
0
0.8
V
ENABLE Logic High
VENABLE_HIGH
ENABLE Logic Low
VENABLE_LOW
ENABLE Pin Current
IEN
VIN = 6.6V
M/S Ternary Pin Logic
Low
VT-LOW
Tie M/S Pin to GND
M/S Ternary Pin Logic
Float
VT-FLOAT
M/S Ternary Pin Logic
Hi (Note 7)
µA
50
0
0.7
V
M/S Pin is Open
1.1
1.4
V
VT-HIGH
Pull Up to VIN through an external
resistor REXT . Refer to Figure 7.
1.8
Ternary Pin Input
Current
ITERN
2.5V ≤ VIN ≤ 4V, REXT = 15kΩ
4V < VIN ≤ 6.6V, REXT = 51kΩ
117
88
µA
Binary Pin Logic Low
Threshold
VB-LOW
ENABLE, S_IN
0.8
V
Binary Pin Logic High
Threshold
VB-HIGH
ENABLE, S_IN
S_OUT Low Level
VS_OUT_LOW
S_OUT High Level
VS_OUT_HIGH
V
1.8
V
0.4
2.0
V
V
Note 3: POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing
the 90% level, there is a 256 clock cycle (~213µs at 1.2 MHz) delay before POK is de-asserted. The 90% and 92% levels
are nominal values. Expect these thresholds to vary by ±3%.
Note 4: Parameter not production tested but is guaranteed by design.
Note 5: Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH.
Note 6: VOUT Rise Time Accuracy does not include soft-start capacitor tolerance..
Note 7: M/S pin is ternary. Ternary pins have three logic levels: high, float, and low. This pin is meant to be strapped to
VIN through an external resistor, strapped to GND, or left floating. The state cannot be changed while the device is on.
www.altera.com/enpirion, Page 6
06489
March 24, 2015
Rev G
EN6360QI
Typical Performance Curves
Efficiency vs. Output Current
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs. Output Current
100
70
60
VOUT = 2.5V
50
VOUT = 1.8V
40
30
VOUT = 1.2V
20
VOUT = 1.0V
10
CONDITIONS
VIN = 3.3V
0
70
60
VOUT = 3.3V
50
VOUT = 2.5V
40
30
VOUT = 1.8V
20
VOUT = 1.2V
10
VOUT = 1.0V
0
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
0
Output Voltage vs. Output Current
6
7
8
1.020
1.815
1.015
VOUT = 1.8V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2
3
4
5
OUTPUT CURRENT (A)
1
Output Voltage vs. Output Current
1.820
1.810
1.805
1.800
1.795
1.790
CONDITIONS
VIN = 3.3V
1.785
VOUT = 1.0V
1.010
1.005
1.000
0.995
0.990
CONDITIONS
VIN = 3.3V
0.985
0.980
1.780
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
0
8
Output Voltage vs. Output Current
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
Output Voltage vs. Output Current
3.320
1.820
3.315
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
CONDITIONS
VIN = 5.0V
VOUT = 3.3V
3.310
3.305
3.300
3.295
3.290
CONDITIONS
VIN = 5.0V
3.285
1.815
VOUT = 1.8V
1.810
1.805
1.800
1.795
1.790
CONDITIONS
VIN = 5.0V
1.785
1.780
3.280
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
www.altera.com/enpirion, Page 7
06489
March 24, 2015
Rev G
EN6360QI
Typical Performance Curves (Continued)
Output Voltage vs. Input Voltage
Output Voltage vs. Output Current
1.820
1.015
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.020
VOUT = 1.0V
1.010
1.005
1.000
0.995
0.990
CONDITIONS
VIN = 5.0V
0.985
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
0.980
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
2.4
8
Output Voltage vs. Input Voltage
1.820
1.815
1.815
1.810
1.805
1.800
1.795
1.790
CONDITIONS
Load = 4A
1.785
3
3.6
4.2
4.8
5.4
INPUT VOLTAGE (V)
6.6
1.810
1.805
1.800
1.795
1.790
CONDITIONS
Load = 8A
1.785
1.780
1.780
2.4
3
6
3.6
4.2
4.8
5.4
INPUT VOLTAGE (V)
6.6
2.4
Output Voltage vs. Temperature
3
4.2
4.8
5.4
3.6
INPUT VOLTAGE (V)
6
6.6
Output Voltage vs. Temperature
1.802
1.802
LOAD = 0A
1.801
LOAD = 0A
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
6
Output Voltage vs. Input Voltage
1.820
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
CONDITIONS
Load = 0A
LOAD = 2A
LOAD = 4A
1.800
LOAD = 6A
1.799
LOAD = 8A
1.798
1.797
CONDITIONS
VIN = 6.6V
VOUT_NOM = 1.8V
1.796
1.795
1.801
LOAD = 2A
LOAD = 4A
1.800
LOAD = 6A
1.799
LOAD = 8A
1.798
1.797
CONDITIONS
VIN = 5V
VOUT_NOM = 1.8V
1.796
1.795
1.794
1.794
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
www.altera.com/enpirion, Page 8
06489
March 24, 2015
Rev G
EN6360QI
Typical Performance Curves (Continued)
Output Voltage vs. Temperature
Output Voltage vs. Temperature
1.802
1.802
LOAD = 0A
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
LOAD = 0A
1.801
LOAD = 2A
LOAD = 4A
1.800
LOAD = 6A
1.799
LOAD = 8A
1.798
1.797
CONDITIONS
VIN = 3.6V
VOUT_NOM = 1.8V
1.796
1.795
1.801
LOAD = 2A
LOAD = 4A
1.800
LOAD = 6A
LOAD = 8A
1.799
1.798
1.797
CONDITIONS
VIN = 2.5V
VOUT_NOM = 1.8V
1.796
1.795
1.794
1.794
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
-40
85
9
8
7
6
5
4
3
CONDITIONS
Conditions
VIN
VIN
==
5.0V
5.0V
= 3.3V
= 3.3V
VOUT
VOUT
2
1
0
-40
-15
10
35
60
AMBIENT TEMPERATURE( C)
85
10
9
8
7
6
5
4
3
CONDITIONS
Conditions
VIN
VIN
==
5.0V
5.0V
= 1.0V
= 3.3V
VOUT
VOUT
2
1
0
-40
-15
10
35
60
AMBIENT TEMPERATURE( C)
85
EMI Performance (Vertical Scan)
EMI Performance (Horizontal Scan)
100.0
100.0
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.5V
LOAD = 0.2Ω
80.0
70.0
80.0
60.0
50.0
CISPR 22 Class B 3m
40.0
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.5V
LOAD = 0.2Ω
90.0
LEVEL (dBµV/m)
90.0
LEVEL (dBµV/m)
85
No Thermal Derating
10
GUARANTEED OUTPUT CURRENT (A)
GUARANTEED OUTPUT CURRENT (A)
No Thermal Derating
35
60
-15
10
AMBIENT TEMPERATURE ( C)
70.0
60.0
50.0
30.0
30.0
20.0
20.0
10.0
CISPR 22 Class B 3m
40.0
10.0
30
300
FREQUENCY (MHz)
30
300
FREQUENCY (MHz)
www.altera.com/enpirion, Page 9
06489
March 24, 2015
Rev G
EN6360QI
Typical Parallel Performance Curves
Parallel Efficiency
vs. Output Current
100
90
80
70
60
50
40
30
20
10
0
EFFICIENCY (%)
EFFICIENCY (%)
Parallel Efficiency
vs. Output Current
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
0
2
CONDITIONS
VIN = 3.3V
2x EN6360QI
4
6
8
10
12
OUTPUT CURRENT (A)
14
100
90
80
70
60
50
40
30
20
10
0
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
0
16
3
2
1
0
-1
CONDITIONS
EN6360QI
VIN = 5V
VOUT = 3.3V
-3
-4
-5
2
4
6
8
10
12
OUTPUT CURRENT (A)
14
16
INDIVIDUAL OUTPUT CURRENT (A)
CURRENT MIS-MATCH (%)
Mis-match (%) = (I_Master - I_Slave ) / I_Average x 100
-2
4
6
8
10
12
OUTPUT CURRENT (A)
14
16
PARALLEL OUTPUT VOLTAGE (V)
PARALLEL OUTPUT VOLTAGE (V)
CONDITIONS
VIN = 5.0V
2x EN6360QI
2
16
9
8
Master Device
7
Slave Device
6
5
4
CONDITIONS
EN6360QI
VIN = 5V
VOUT = 3.3V
3
2
1
0
2
4
6
14
8
10
12
TOTAL OUTPUT CURRENT (A)
16
Parallel Output Voltage
vs. Output Current
VOUT = 3.3V
0
14
10
Parallel Output Voltage
vs. Output Current
3.4
3.38
3.36
3.34
3.32
3.3
3.28
3.26
3.24
3.22
3.2
4
6
10
12
8
OUTPUT CURRENT (A)
Parallel Current Share Breakdown
Parallel Current Share Mis-Match
5
4
2
CONDITIONS
VIN = 5.0V
2x EN6360QI
1.1
1.08
1.06
1.04
1.02
1
0.98
0.96
0.94
0.92
0.9
VOUT = 1.0V
CONDITIONS
VIN = 3.3V
2x EN6360QI
0
2
4
6
8
10
12
OUTPUT CURRENT (A)
14
16
www.altera.com/enpirion, Page 10
06489
March 24, 2015
Rev G
EN6360QI
Typical Performance Characteristics
Output Ripple at 500MHz Bandwidth
Output Ripple at 20MHz Bandwidth
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 1V
IOUT = 8A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
Output Ripple at 20MHz Bandwidth
VOUT
(AC Coupled)
VOUT
(AC Coupled)
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 2.4V
IOUT = 8A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 2.4V
IOUT = 8A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
Enable Power Up/Down
Enable Power Up/Down
ENABLE
VOUT
CONDITIONS
VIN = 5V
VOUT = 1V
IOUT = 8A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
ENABLE
CONDITIONS
VIN = 5V
VOUT = 1.0V
IOUT = 8A
Css = 15nF
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
CONDITIONS
VIN = 5V
VOUT = 2.4V
IOUT = 8A
Css = 15nF
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
www.altera.com/enpirion, Page 11
06489
March 24, 2015
Rev G
EN6360QI
Typical Performance Characteristics (Continued)
Load Transient from 0 to 8A
Enable/Disable with POK
CONDITIONS
VIN = 6.2V
VOUT = 1.5V
CIN = 2 x 22µF (1206)
COUT = 2 x 47µF (1206)
ENABLE
VOUT
VOUT
(AC Coupled)
POK
LOAD
CONDITIONS
VIN = 5V, VOUT = 1.0V
LOAD = 5A, Css = 15nF
LOAD
Parallel Operation Current Sharing
Parallel Operation SW Waveforms
MASTER VSW
TOTAL LOAD = 18A
SLAVE 2 VSW
MASTER LOAD = 6A
SLAVE 1 VSW
SLAVE 2 LOAD = 6A
COMBINED LOAD(18A)
CONDITIONS
VIN = 5V
VOUT = 1.8V
LOAD = 18A
SLAVE 1 LOAD = 6A
CONDITIONS
VIN = 5V
VOUT = 1.8V
LOAD = 18A
www.altera.com/enpirion, Page 12
06489
March 24, 2015
Rev G
EN6360QI
Functional Block Diagram
S_OUT
M/S
S_IN
PVIN
Digital I/O
To PLL
VDDB
Eff
UVLO
BGND
Thermal Limit
P-Drive
Current Limit
NC(SW)
VOUT
N-Drive
(-)
PWM
Comp
(+)
PGND
24k
AVIN
Compensation
Network
PLL/Sawtooth
Generator
FQADJ
EAOUT
(-)
Error
Amp
(+)
ENABLE
SS
Reference
Voltage
Selector
Soft Start
MUX
VFB
Power
Good
Logic
POK
AVIN
94k
MUX
Bandgap
Reference
AVIN
VSENSE
AVIN
24k
EN_PB
EAOUT
AGND
Figure 4: Functional Block Diagram
www.altera.com/enpirion, Page 13
06489
March 24, 2015
Rev G
EN6360QI
Functional Description
The EN6360QI is a synchronous, programmable
buck power supply with integrated power MOSFET
switches and integrated inductor. The switching
supply uses voltage mode control and a low noise
PWM topology. This provides superior impedance
matching to ICs processed in sub 90nm process
technologies. The nominal input voltage range is
2.5 - 6.6 volts. The output voltage is programmed
using an external resistor divider network. The
feedback control loop incorporates a type IV
voltage mode control design. Type IV voltage mode
control maximizes control loop bandwidth and
maintains excellent phase margin to improve
transient performance. The EN6360QI is designed
to support up to 8A continuous output current
operation. The operating switching frequency is
between 0.9MHz and 1.5MHz and enables the use
of small-size input and output capacitors.
The power supply has the following features:
capacitor between this pin and AGND provides a
soft-start function to limit in-rush current during
device power-up. When the part is initially powered
up, the output voltage is gradually ramped to its
final value. The gradual output ramp is achieved by
increasing the reference voltage to the error
amplifier. A constant current flowing into the softstart capacitor provides the reference voltage ramp.
When the voltage on the soft-start capacitor
reaches 0.60V, the output has reached its
programmed voltage. Once the output voltage has
reached nominal voltage the soft-start capacitor will
continue to charge to 1.5V (Typical). The output
rise time can be controlled by the choice of softstart capacitor value.
The rise time is defined as the time from when the
ENABLE signal crosses the threshold and the input
voltage crosses the upper UVLO threshold to the
time when the output voltage reaches 95% of the
programmed value. The rise time (tRISE) is given by
the following equation:
tRISE [ms] = Css [nF] x 0.065
•
Precision Enable Threshold
•
Soft-Start
•
Pre-bias Start-Up
•
Resistor Programmable Switching Frequency
•
Phase-Lock Frequency Synchronization
•
Parallel Operation
Pre-Bias Start-up
•
Power OK
•
Over-Current/Short Circuit Protection
•
Thermal Shutdown with Hysteresis
•
Under-Voltage Lockout
The EN6360QI supports startup into a pre-biased
load. A proprietary circuit ensures the output
voltage rises up from the pre-bias value to the
programmed output voltage. Start-up is guaranteed
to be monotonic for pre-bias voltages in the range
of 20% to 75% of the programmed output voltage
with a minimum pre-bias voltage of 300mV. Outside
of the 20% to 75% range, the output voltage rise
will not be monotonic. The Pre-Bias feature is
automatically engaged with an internal pull-up
resistor. For this feature to work properly, VIN must
be ramped up prior to ENABLE turning on the
device. Tie VSENSE to VOUT if Pre-Bias is used.
Tie EN_PB to ground and leave VSENSE floating
to disable the Pre-Bias feature. Pre-Bias is
supported for external clock synchronization, but
not supported for parallel operations.
Precision Enable
The ENABLE threshold is a precision analog
voltage rather than a digital logic threshold. A
precision voltage reference and a comparator
circuit are kept powered up even when ENABLE is
de-asserted. The narrow voltage gap between
ENABLE Logic Low and ENABLE Logic High
allows the device to turn on at a precise enable
voltage level. With the enable threshold pinpointed,
a proper choice of soft-start capacitor helps to
accurately sequence multiple power supplies in a
system as desired. There is an ENABLE lockout
time of 2ms that prevents the device from reenabling immediately after it is disabled.
Soft-Start
The SS pin in conjunction with a small external
The rise time (tRISE) is in milliseconds and the softstart capacitor (CSS) is in nano-Farads. The softstart capacitor should be between 10nF and 100nF.
Resistor Programmable Frequency
The operation of the EN6360QI can be optimized
by a proper choice of the RFQADJ resistor. The
frequency can be tuned to optimize dynamic
performance and efficiency. Refer to Table 1 for
recommended RFQADJ values.
www.altera.com/enpirion, Page 14
06489
March 24, 2015
Rev G
EN6360QI
together with the Master by connecting the S_OUT
of the Master to the S_IN of all other Slave devices.
Refer to Figure 5 for details.
Table 1: Recommended RFQADJ (kΩ)
VOUT
VIN
3.3V ±10%
5.0V ±10%
6.0V ±10%
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
3.57
3.57
3.57
3.57
3.57
3.57
4.99
4.99
4.99
5.49
5.49
5.49
5.49
5.49
5.49
NA
4.99
5.49
Phase-Lock Operation:
The EN6360QI can be phase-locked to an external
clock signal to synchronize its switching frequency.
The M/S pin can be left floating or pulled to ground
to allow the device to synchronize with an external
clock signal using the S_IN pin. When a clock
signal is present at S_IN, an activity detector
recognizes the presence of the clock signal and the
internal oscillator phase locks to the external clock.
The external clock could be the system clock or the
output of another EN6360QI. The phase locked
clock is then output at S_OUT. Refer to Table 2 for
recommended clock frequencies.
Careful attention is needed in the layout for parallel
operation. The VIN, VOUT and GND of the
paralleled devices should have low impedance
connections between each other. Maximize the
amount of copper used to connect these pins and
use as many vias as possible when using multiple
layers. Place the Master device between all other
Slaves and closest to the point of load.
GND
EN6360QI
SLAVE3
S_IN
VOUT
M/S
VIN
VFB
REXT
OPEN
GND
EN6360QI
SLAVE2
S_IN
VOUT
M/S
VIN
VFB
REXT
OPEN
GND
Table 2: Recommended Clock fsw (MHz)±10%
S_OUT
VOUT
VIN
3.3V ±10%
5.0V ±10%
6.0V ±10%
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
1.15
1.15
1.15
1.15
1.15
1.15
1.30
1.30
1.30
1.35
1.35
1.35
1.35
1.35
1.35
NA
1.30
1.35
EN6360QI
MASTER
VOUT
VOUT
VFB
VIN M/S
VIN
Feedback &
Compensation
GND
Master / Slave (Parallel) Operation and
Frequency Synchronization
S_IN
Multiple EN6360QI devices may be connected in a
Master/Slave configuration to handle larger load
currents. The device is placed in Master mode by
pulling the M/S pin low or in Slave mode by pulling
M/S pin high. When the M/S pin is in float state,
parallel operation is not possible. In Master
mode, a version of the internal switching PWM
signal is output on the S_OUT pin. This PWM
signal from the Master is fed to the Slave device at
its S_IN pin. The Slave device acts like an
extension of the power FETs in the Master and
inherits the PWM frequency and duty cycle. The
inductor in the Slave prevents crow-bar currents
from Master to Slave due to timing delays. The
Master device’s switching clock may be phaselocked to an external clock source or another
EN6360QI to move the entire parallel operation
frequency away from sensitive frequencies. The
feedback network for the Slave device may be left
open. Additional Slave devices may be paralleled
EN6360QI
SLAVE1
VOUT
VIN M/S
REXT
VFB
OPEN
Figure 5: Master/Slave Parallel Operation Diagram
POK Operation
The POK signals that the output voltage is within
the specified range. The POK signal is asserted
high when the rising output voltage crosses 92%
(nominal) of the programmed output voltage. If the
output voltage falls outside the range of 90% to
120%, POK remains asserted for the de-glitch time
(213µs at 1.2MHz). After the de-glitch time, POK is
de-asserted. POK is also de-asserted if the output
voltage exceeds 120% of the programmed output
voltage.
Over Current Protection
The current limit function is achieved by sensing
www.altera.com/enpirion, Page 15
06489
March 24, 2015
Rev G
EN6360QI
the current flowing through a sense P-FET. When
the sensed current exceeds the current limit, both
power FETs are turned off for the rest of the
switching cycle. If the over-current condition is
removed, the over-current protection circuit will reenable PWM operation. If the over-current condition
persists, the circuit will continue to protect the load.
The OCP trip point is nominally set as specified in
the Electrical Characteristics table. In the event the
OCP circuit trips consistently in normal operation,
the device enters a hiccup mode. The device is
disabled for 27ms and restarted with a normal softstart. This cycle can continue indefinitely as long as
the over current condition persists.
Thermal Overload Protection
Temperature sensing circuits in the controller will
disable operation when the junction temperature
exceeds approximately 150ºC. Once the junction
temperature drops by approx 20ºC, the converter
will re-start with a normal soft-start.
Input Under-Voltage Lock-Out
When the input voltage is below a required voltage
level (VUVHI ) for normal operation, the converter
switching is inhibited. The lock-out threshold has
hysteresis to prevent chatter. Thus when the device
is operating normally, the input voltage has to fall
below the lower threshold (VUVLO) for the device to
stop switching.
www.altera.com/enpirion, Page 16
06489
March 24, 2015
Rev G
EN6360QI
Application Information
Output Voltage Programming and loop
Compensation
Calculate the external feedback and compensation
network values with the equations below.
The EN6360QI output voltage is programmed using
a simple resistor divider network. A phase lead
capacitor plus a resistor are required for stabilizing
the loop. Figure 6 shows the required components
and the equations to calculate their values.
RA [Ω] = 48,400 x VIN [V]
The EN6360QI output voltage is determined by the
voltage presented at the VFB pin. This voltage is
set by way of a resistor divider between VOUT and
AGND with the midpoint going to VFB.
The EN6360QI uses a type IV compensation
network. Most of this network is integrated.
However, a phase lead capacitor and a resistor are
required in parallel with upper resistor of the
external feedback network (Refer to Figure 6). Total
compensation is optimized for use with two 47μF
output capacitance and will result in a wide loop
bandwidth and excellent load transient performance
for most applications. Additional capacitance may
be placed beyond the voltage sensing point outside
the control loop. Voltage mode operation provides
high noise immunity at light load. Furthermore,
voltage mode control provides superior impedance
matching to ICs processed in sub 90nm
technologies.
In some cases modifications to the compensation
or output capacitance may be required to optimize
device performance such as transient response,
ripple, or hold-up time. The EN6360QI provides the
capability to modify the control loop response to
allow for customization for such applications. For
more information, contact Power Applications
support.
*Round RA up to closest standard value
RB[Ω] = (VFB x RA) / (VOUT – VFB) [V]
VFB = 0.6V nominal
*Round RB to closest standard value
CA [F] = 3.83 x 10-6 / RA [Ω]
*Round CA down to closest standard value
R1 = 15kΩ
The feedback resistor network should be sensed at
the last output capacitor close to the device. Keep
the trace to VFB pin as short as possible.
Whenever possible, connect RB directly to the
AGND pin instead of going through the GND plane.
Input Capacitor Selection
The EN6360QI has been optimized for use with two
1206 22µF input capacitors. Low ESR ceramic
capacitors are required with X5R or X7R dielectric
formulation.
Y5V or equivalent dielectric
formulations must not be used as these lose
capacitance with frequency, temperature and bias
voltage.
In some applications, lower value ceramic
capacitors may be needed in parallel with the larger
capacitors in order to provide high frequency
decoupling. The capacitors shown in the table
below are typical input capacitors. Other capacitors
with similar characteristics may also be used.
Table 3: Recommended Input Capacitors
VOUT
RA
CA
R1
Description
MFG
P/N
22µF, 10V, 20%
X5R, 1206
(2 capacitors needed)
Murata
GRM31CR61A226ME19L
Taiyo Yuden
LMK316BJ226ML-T
Output Capacitor Selection
VFB
RB
Figure 6: External Feedback/Compensation Network
The feedback and compensation network values
depend on the input voltage and output voltage.
The EN6360QI has been optimized for use with two
1206 47µF output capacitors. Low ESR, X5R or
X7R ceramic capacitors are recommended as the
primary choice. Y5V or equivalent dielectric
formulations must not be used as these lose
capacitance with frequency, temperature and bias
voltage.
The
capacitors shown
in the
Recommended Output Capacitors table are typical
output capacitors. Other capacitors with similar
characteristics may also be used. Additional bulk
www.altera.com/enpirion, Page 17
06489
March 24, 2015
Rev G
EN6360QI
Table 5: Recommended REXT Resistor
capacitance from 100µF to 1000µF may be placed
beyond the voltage sensing point outside the
control loop. This additional capacitance should
have a minimum ESR of 6mΩ to ensure stable
operation. Most tantalum capacitors will have more
than 6mΩ of ESR and may be used without special
care. Adding distance in layout may help increase
the ESR between the feedback sense point and the
bulk capacitors.
VIN (V)
IMAX (µA)
REXT (kΩ)
2.5 – 4.0
4.0 – 6.6
117
88
15
51
2.5V
Table 4: Recommended Output Capacitors
Description
47µF, 10V, 20%
X5R, 1206
(2 capacitors needed)
47µF, 6.3V, 20%
X5R, 1206
(2 capacitors needed)
10µF, 6.3V, 10%
X7R, 0805
(Optional 1 capacitor in
parallel with 2x47µF)
P/N
Taiyo Yuden
LMK316BJ476ML-T
Murata
GRM31CR60J476ME19L
Taiyo Yuden
JMK316BJ476ML-T
Murata
GRM21BR70J106KE76L
Taiyo Yuden
JMK212B7106KG-T
M/S
Output ripple voltage is primarily determined by the
aggregate output capacitor impedance. Placing
multiple capacitors in parallel reduces the
impedance and hence will result in lower ripple
voltage.
1
Z Total
=
Typical Output Ripple (mVp-p)
2 x 47 µF
<10mV
†
20 MHz bandwidth limit measured on Evaluation Board
M/S - Ternary Pin
M/S is a ternary pin. This pin can assume 3 states
– A low state (0V to 0.7V), a high state (1.8V to
VIN) and a float state (1.1V to 1.4V). Device
operation is controlled by the state of the pin. The
pins may be pulled to ground or left floating without
any special care. When pulling high to VIN, a series
resistor is recommended. The resistor value may
be optimized to reduce the current drawn by the
pin. The resistance should not be too high as in that
case the pin may not recognize the high state. The
recommend resistance (REXT) value is given in the
following table.
To Gates
REXT
D1
Vf ≈ 2V
R2
134k
AGND
Inside EN6360QI
Figure 7: Selection of REXT to Connect M/S pin to VIN
Table 6: M/S (Master/Slave) Pin States
1
1
1
+
+ ... +
Z1 Z 2
Zn
Table 5: Typical Ripple Voltages
Output Capacitor
Configuration
R3
319
To VIN
MFG
R1
134k
M/S Pin
Function
Low
(0V to 0.7V)
M/S pin is pulled to ground directly. This is
the Master mode. Switching PWM phase
will lock onto S_IN external clock if a signal
is available. S_OUT outputs a version of
the internal switching PWM signal.
M/S pin is left floating. Parallel operation is
not feasible. Switching PWM phase will
Float
lock onto S_IN external clock if a signal is
(1.1V to 1.4V)
available. S_OUT outputs a version of the
internal switching PWM signal.
High
(>1.8V)
M/S pin is pulled to VIN with REXT. This is
the Slave mode. The S_IN signal of the
Slave should connect to the S_OUT of the
Master device. This signal synchronizes
the switching frequency and duty cycle of
the Master to the Slave device.
Power-Up Sequencing
During power-up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. Tying all three pins together meets
these requirements.
Technical Support
Contact Altera for additional support regarding the
use of this product (www.altera.com/support).
www.altera.com/enpirion, Page 18
06489
March 24, 2015
Rev G
EN6360QI
Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
For VIN = 5V, VOUT = 3.3V at 8A, η ≈ 94%
η = POUT / PIN = 94% = 0.94
PIN = POUT / η
PIN ≈ 26.4W / 0.94 ≈ 28.085W
The power dissipation (PD ) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
The Altera Enpirion EN6360QI DC-DC converter is
packaged in an 8x11x3mm 68-pin QFN package.
The QFN package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
150°C.
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN6360QI has
a θJA value of 15 ºC/W without airflow.
The EN6360QI is guaranteed to support the full 8A
output current up to 85°C ambient temperature.
The following example and calculations illustrate
the thermal performance of the EN6360QI.
Example:
ΔT ≈ 1.685W x 15°C/W = 25.28°C ≈ 25.3°C
The junction temperature (T J ) of the device is
approximately the ambient temperature (T A) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
VIN = 5V
T J = T A + ΔT
VOUT = 3.3V
T J ≈ 25°C + 25.3°C ≈ 50.3°C
With 1.685W dissipated into the device, the T J will
be 50.3°C.
IOUT = 8A
First calculate the output power.
POUT = 3.3V x 8A = 26.4W
Next, determine the input power based on the
efficiency (η) shown in Figure 8.
Efficiency vs. Output Current
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
The maximum operating junction temperature
(T JMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (T AMAX) allowed can
be calculated.
≈ 125°C – 25.3°C ≈ 99.7°C
94%
80
EFFICIENCY (%)
≈ 28.085W – 26.4W ≈ 1.685W
T AMAX = T JMAX – PD x θJA
100
90
PD = PIN – POUT
70
60
50
40
30
20
VOUT = 3.3V
10
CONDITIONS
VIN = 5.0V
0
0
1
2
3
4
5
OUTPUT CURRENT (A)
6
7
8
The ambient temperature can actually rise by
another 74.7°C, bringing it to 99.7°C before the
device will reach T JMAX. This indicates that the
EN6360QI can support the full 8A output current
range up to approximately 99.7°C ambient
temperature given the input and output voltage
conditions. This allows the EN6360QI to guarantee
full 8A output current capability at 85°C with room
for margin. Note that the efficiency will be slightly
lower at higher temperatures and this estimate will
be slightly lower.
Figure 8: Efficiency vs. Output Current
www.altera.com/enpirion, Page 19
06489
March 24, 2015
Rev G
EN6360QI
Engineering Schematic
Figure 9: Engineering Schematic with Engineering Notes
www.altera.com/enpirion, Page 20
06489
March 24, 2015
Rev G
EN6360QI
Layout Recommendation
Figure 10: Top Layout with Critical Components Only
(Top View). See Figure 9 for corresponding schematic.
This layout only shows the critical components and
top layer traces for minimum footprint in singlesupply mode with ENABLE tied to AVIN. Alternate
circuit configurations & other low-power pins need
to be connected and routed according to customer
application. Please see the Gerber files at
http://www.altera.com/enpirion for details on all
layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN6360QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes. The +V and
GND traces between the capacitors and the
EN6360QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to provide some
separation between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The thermal pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 10 this connection is made at the input
capacitor.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure 10.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC converter, try not to run sensitive signal or
control lines underneath the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output filter capacitor. Keep the
sense trace short in order to avoid noise coupling
into the node.
Recommendation 9: Keep RA, CA, RB, and R1
close to the VFB pin (Refer to Figure 10). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND pin
instead of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance.
Not
following
layout
recommendations can complicate designs and
create anomalies different than the expected
operation of the product.
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EN6360QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 11.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EN6360QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 11 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult EN6360QI
Application Notes - Soldering Guidelines for more details and recommendations.
Figure 11: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
www.altera.com/enpirion, Page 22
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EN6360QI
Recommended PCB Footprint
Figure 12: EN6360QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing
specifications.
www.altera.com/enpirion, Page 23
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March 24, 2015
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EN6360QI
Package and Mechanical
Figure 13: EN6360QI Package Dimensions (Bottom View)
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2014 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS,
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www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's
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www.altera.com/enpirion, Page 24
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March 24, 2015
Rev G