EN23F0QI

Enpirion® Power Datasheet
EN23F0QI 15A PowerSoC
Voltage Mode Synchronous Buck
With Integrated Inductor
Not Recommended for New Designs
Description
Features
The EN23F0QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal control circuits, compensation
and an integrated inductor in an advanced
12x13x3mm QFN module. It offers high efficiency,
excellent line and load regulation. The EN23F0QI
operates over a wide input voltage range and is
specifically designed to meet the precise voltage and
fast transient requirements of high-performance
products. The EN23F0QI features frequency
synchronization to an external clock, power OK
output voltage monitor, programmable soft-start along
with thermal and short circuit protection. The device’s
advanced circuit design, ultra high switching
frequency and proprietary integrated inductor
technology delivers high-quality, ultra compact, nonisolated DC-DC conversion.
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The Altera Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, overall system level
reliability is improved given the small number of
components required with the Altera Enpirion
solution.
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Applications
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All Altera Enpirion products are RoHS compliant and
lead-free manufacturing environment compatible.
0.1µF
Integrated Inductor, MOSFETs, Controller
Total Solution Size Estimate 308mm2
Wide Input Voltage Range: 4.5V – 14V
1% Initial Output Voltage Accuracy
Master/Slave Configuration for Parallel Operation
Up to 4 Devices with 48A capability
Frequency Synchronization (External Clock)
Output Enable Pin and Power OK Signal
Programmable Soft-Start Time
Under Voltage Lockout Protection (UVLO)
Short Circuit Protection
Thermal Shutdown Protection
RoHS compliant, MSL level 3, 260oC reflow
Space Constrained Applications
Distributed Power Architectures
Output Voltage Ripple Sensitive Applications
Beat Frequency Sensitive Applications
Servers, Embedded Computing Systems,
LAN/SAN Adapter Cards, RAID Storage Systems,
Industrial Automation, Test and Measurement,
and Telecommunications
Efficiency vs. Output Current
0.47µF
100
BTMP VDDB
PVIN
4.75k
OFF
ENABLE
EAIN
AVINO
1µF
REA
3x
47µF
1206
RA
AVIN
1µF
47nF
CA
RCA
VFB
SS
M/S
CGND
PGND
PGND
FQADJ AGND
90
80
EN23F0QI
ON
3x
22µF
1206
VOUT
BGND
VOUT
RCLX
RB
EFFICIENCY (%)
PG
VIN
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
VOUT = 1.0V
10
0
0
RFS
100k
Figure 1. Simplified Applications Circuit
(Footprint Optimized)
07512
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
1
2
3
4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
Figure 2. Highest Efficiency in Smallest Solution Size
June 2, 2015
Rev D
EN23F0QI
Ordering Information
Part Number
EN23F0QI
EVB-EN23F0QI
Package Markings
EN23F0QI
EN23F0QI
TAMBIENT Rating (°C)
-40 to +85
Package Description
92-pin (12mm x 13mm x 3mm) QFN T&R
QFN Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
AVIN
POK
71
AGND
74
ENABLE
M/S
75
73
VFB
76
72
SS
EAIN
78
RCLX
79
77
NC
FQADJ
CGND
82
81
NC(SW)
80
NC(SW)
83
NC(SW)
87
84
NC(SW)
88
NC(SW)
NC(SW)
89
NC(SW)
NC(SW)
90
85
NC(SW)
91
86
NC(SW)
92
Pin Assignments (Top View)
NC
1
NC
2
69
S_IN
NC
3
68
BGND
NC
4
67
VDDB
NC
5
66
BTMP
NC
6
65
PG
NC
7
64
AVINO
KEEP OUT
70
S_OUT
8
63
PVIN
9
62
PVIN
NC
10
61
PVIN
NC
11
60
PVIN
NC
12
59
PVIN
NC
13
58
PVIN
NC
14
57
PVIN
NC
15
56
PVIN
NC
16
55
PVIN
NC
17
54
PVIN
PVIN
KEEP OUT
NC
NC
93
PGND
KEEP OUT
43
44
PGND
PGND
PGND
46
42
PGND
PGND
41
PGND
45
40
NC(SW)
PGND
38
39
NC(SW)
36
37
NC
VOUT
NC(SW)
35
VOUT
VOUT
34
PVIN
33
PVIN
47
32
48
24
31
23
NC
VOUT
NC
VOUT
PVIN
30
PVIN
49
VOUT
50
22
VOUT
21
NC
29
NC
28
PVIN
VOUT
51
26
20
27
PVIN
NC
VOUT
52
VOUT
53
19
25
18
VOUT
NC
NC
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. All pins
including NC pins must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 16 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
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07512
June 2, 2015
Rev D
EN23F0QI
Pin Description
I/O Legend:
PIN
P=Power
NAME
G=Ground
NC=No Connect
I/O
1-24,
36, 81
NC
NC
25-35
VOUT
O
37-39,
83-92
NC(SW)
NC
40-46
PGND
G
47-63
PVIN
P
64
AVINO
O
65
66
PG
BTMP
I/O
I/O
67
VDDB
O
68
BGND
G
69
S_IN
I
70
S_OUT
O
71
POK
O
72
ENABLE
I
73
AVIN
P
74
AGND
G
75
M/S
I
76
VFB
I/O
77
EAIN
I
78
SS
I/O
79
RCLX
I/O
80
FQADJ
I/O
82
CGND
G
93
PGND
G
I=Input O=Output
I/O=Input/Output
FUNCTION
NO CONNECT – These pins may be internally connected. Do not connect them to each
other or to any other electrical signal. Failure to follow this guideline may result in device
damage.
Regulated converter output. Connect these pins to the load and place output capacitors
between these pins and PGND pins 40-43.
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground,
or voltage. Failure to follow this guideline may result in damage to the device.
Input/Output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
Input power supply. Connect to input power supply. Decouple with input capacitor to PGND
pins 44-46.
Internal 3.4V linear regulator output. Connect this pin to AVIN for applications where
operation from a single input voltage (PVIN) is required. If AVINO is being used, place a
1µF, X5R/X7R, capacitor between AVINO and AGND as close as possible to AVINO.
Place a 0.1µF, X7R, capacitor between this pin and BTMP.
See pin 65 description.
Internal regulated voltage used for the internal control circuitry. Place a 0.47µF, X7R,
capacitor between this pin and BGND.
Ground for VDDB. Do not connect BGND to any other ground. See pin 67 description.
Digital Input. This pin accepts either an input clock to phase lock the internal switching
frequency or a S_OUT signal from another EN23F0QI. Leave this pin floating if not used.
Digital Output. PWM signal is output on this pin. Leave this pin floating if not used.
Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power
system state indication. POK is logic high when VOUT is -10% of VOUT nominal. Leave
this pin floating if not used.
Output enable. Applying a logic high to this pin enables the output and initiates a soft-start.
Applying a logic low disables the output. ENABLE logic cannot be higher than AVIN (refer to
Absolute Maximum Ratings). Do not leave floating. See Power Up/Down Sequencing
section for details.
3.3V Input power supply for the controller. Place a 1µF, X7R, capacitor between AVIN and
AGND.
Analog ground. This is the ground return for the controller. All AGND pins need to be
connected to a quiet ground.
A logic level low configures the device as Master and a logic level high configures the
device as a Slave. Connect to ground in standalone mode.
External feedback input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A
phase lead network from this pin to VOUT is also required to stabilize the loop.
Optional error amplifier input. Allows for customization of the control loop for performance
optimization. Leave this pin floating if not used.
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The
value of this capacitor determines the startup time. See Soft-Start Operation in the
Functional Description section for details.
Short circuit protection. Connect a 100k resistor from RCLX to ground.
Adding a resistor (RFS) to this pin will adjust the switching frequency of the EN23F0QI. See
Table 1 for suggested resistor values on RFS for various PVIN/VOUT combinations to
maximize efficiency. Do not leave this pin floating.
Connect to GND plane at all times.
Not a perimeter pin. This device thermal pad must be connected to the system GND plane
for heat-sinking purposes. See Layout Recommendations section.
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07512
June 2, 2015
Rev D
EN23F0QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
MIN
MAX
UNITS
Pin Voltages – PVIN, VOUT, PG
PARAMETER
SYMBOL
-0.5
15
V
Pin Voltages – ENABLE, S_IN, M/S, POK
-0.5
AVIN + 0.3
V
Pin Voltages – AVINO, AVIN, ENABLE, S_IN, S_OUT, M/S
-0.5
6.0
V
Pin Voltages – VFB, SS, EAIN, RCLX, FQADJ, VDDB, BTMP
-0.5
2.75
V
Dual Supply PVIN Rising and Falling Slew Rate (Note 1)
0.3
25
V/ms
Single Supply PVIN Rising and Falling Slew Rate (Note 1)
0.3
6
V/ms
20
A
150
°C
150
°C
260
°C
2000
V
500
V
Maximum Continuous Output Current
IOUT_CONT_MAX
Storage Temperature Range
TSTG
Maximum Operating Junction Temperature
-65
TJ-ABS Max
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
ESD Rating (based on CDM)
Recommended Operating Conditions
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
PARAMETER
PVIN
4.5
14.0
V
AVIN: Controller Supply Voltage
AVIN
2.5
5.5
V
Output Voltage Range (Note 2)
VOUT
0.75
3.3
V
Output Current (Note 3)
IOUT
0
15
A
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Thermal Characteristics
SYMBOL
TYP
UNITS
Thermal Shutdown
PARAMETER
TSD
160
°C
Thermal Shutdown Hysteresis
TSDH
35
°C
Thermal Resistance: Junction to Ambient (0 LFM) (Note 3)
θJA
13
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
1
°C/W
Note 1: PVIN rising and falling slew rates cannot be outside of specification. For accurate power up sequencing, use a
fast ENABLE logic (>3V/100µs) after both AVIN and PVIN are high.
Note 2: Dropout: Maximum VOUT ≤ VIN - 2.5V
Note 3: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
www.altera.com/enpirion Page 4
07512
June 2, 2015
Rev D
EN23F0QI
Electrical Characteristics
NOTE: VIN=12V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
MAX
UNITS
Operating Input Voltage
SYMBOL
PVIN
TEST CONDITIONS
MIN
4.5
TYP
14.0
V
Controller Input Voltage
AVIN
2.5
5.5
V
AVIN Under Voltage
Lock-out rising
AVINUVLOR
Voltage above which UVLO is not
asserted
1.7
2.3
2.4
V
AVIN Under Voltage
Lock-out falling
AVINOVLOF
Voltage below which UVLO is
asserted
1.7
2.1
2.3
V
AVIN Pin Input Current
Internal Linear Regulator
Output Voltage
Shut-Down Supply
Current
IAVIN
14
mA
AVINO
3.4
V
IPVINS
PVIN=12V, AVIN=3.3V, ENABLE=0V
1
mA
IAVINS
PVIN=12V, AVIN=3.3V, ENABLE=0V
75
µA
Feedback Pin Voltage
VFB
Feedback Pin Voltage
VFB
Feedback Pin Input
Leakage Current
IFB
VOUT Rise Time
tRISE
Feedback Node Voltage at:
PVIN = 12V, ILOAD = 0, TA = 25°C
Feedback Node Voltage at:
4.5V ≤ PVIN ≤ 14V
0A ≤ ILOAD ≤ 15A, TA = -40 to 85°C
VFB Pin Input Leakage Current
(Note 4)
CSS = 47nF
(Note 4, Note 5 and Note 6)
Soft Start Capacitor
Range
CSS_RANGE
Note 4
Continuous Output
Current
IOUT_CONT
Subject to thermal derating
0.594
0.60
0.606
V
0.588
0.60
0.612
V
5
nA
-5
1.96
2.8
3.64
ms
10
47
68
nF
0
15
A
ENABLE Logic High
VENABLE_HIGH
4.5V ≤ VIN ≤ 14V;
1.25
AVIN
V
ENABLE Logic Low
VENABLE_LOW
4.5V ≤ VIN ≤ 14V;
0
0.95
V
ENABLE Lockout Time
TENLOCKOUT
fsw = 1MHz (Note 4)
ENABLE Pin Input
Current
Switching Frequency
IENABLE
FSW
AVIN = 5.5V
ENABLE = 1.8V;
ENABLE = 3.3V;
ENABLE = 5.5V;
5
11
23
RFS =3.01kΩ
1.0
External SYNC Clock
Frequency Lock Range
FPLL_LOCK
Range of SYNC clock frequency (See
Table 1)
S_IN Threshold – Low
VS_IN_LO
S_IN Clock Logic Low Level (Note 4)
S_IN Threshold – High
VS_IN_HI
S_IN Clock Logic High Level (Note 4)
S_OUT Threshold – Low
VS_OUT_LO
S_OUT Clock Logic Low Level
(Note 4)
S_OUT Threshold –
High
VS_OUT_HI
S_OUT Clock Logic High Level
(Note 4)
POKLT
Percentage of Nominal Output
Voltage for POK to be Low
POK Lower Threshold
8
0.8
1.8
1.8
90
ms
8
18
32
µA
MHz
1.8
MHz
0.8
V
2.5
V
0.8
V
2.5
V
%
www.altera.com/enpirion Page 5
07512
June 2, 2015
Rev D
EN23F0QI
PARAMETER
SYMBOL
POK Output Low
Voltage
VPOKL
POK Output Hi Voltage
VPOKH
POK pin VOH leakage
current
IPOKL
TEST CONDITIONS
MAX
UNITS
With 4mA Current Sink into POK
0.4
V
PVIN range: 4.5V ≤ PVIN ≤ 15V
AVIN
V
1
µA
0.8
V
VT-LOW
Tie Pin to GND (Master Mode)
M/S Pin Logic High
VT-HIGH
Pull up to AVIN Through an External
Resistor REXT (Slave Mode)
IM/S
TYP
POK High (Note 4)
M/S Pin Logic Low
M/S Pin Input Current
MIN
REXT = 15kΩ;
AVIN = 3.4V;
AVIN = 5.5V;
1.8
V
65
175
µA
Note 4: Parameter not production tested but is guaranteed by design.
Note 5: Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH.
Note 6: VOUT Rise Time Accuracy does not include soft-start capacitor tolerance.
www.altera.com/enpirion Page 6
07512
June 2, 2015
Rev D
EN23F0QI
Typical Performance Curves
Efficiency vs. Output Current
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs. Output Current
100
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
10
VOUT = 1.0V
CONDITIONS
VIN = 12.0V
Single Supply
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
0
0
0
1
2
3
0
4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
Output Current De-rating
16
15
14
13
12
11
10
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 13°C/W
13x12x3mm QFN
No Air Flow
9
8
7
6
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
5
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
3
4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 10.5°C/W
13x12x3mm QFN
Air Flow (200fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
Output Current De-rating
with Heat Sink
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
2
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
Output Current De-rating
with Air Flow (400fpm)
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 9°C/W
13x12x3mm QFN
Air Flow (400fpm)
1
Output Current De-rating
with Air Flow (200fpm)
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
VOUT = 1.0V
10
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 12°C/W
13x12x3mm QFN
No Air Flow
Heat Sink - Wakefield
Thermal Solutions
P/N 651-B
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
www.altera.com/enpirion Page 7
07512
June 2, 2015
Rev D
EN23F0QI
Typical Performance Curves
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 9.5°C/W
13x12x3mm QFN
Air Flow (200fpm)
Heat Sink - Wakefield
Thermal Solutions
P/N 651-B
Output Current De-rating
w/ Heat Sink and Air Flow (400fpm)
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
Output Current De-rating
w/ Heat Sink and Air Flow (200fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 8°C/W
13x12x3mm QFN
Air Flow (400fpm)
Heat Sink - Wakefield
Thermal Solutions
P/N 651-B
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
Output Voltage vs. Output Current
Max VOUT at 15A vs. Temperature
1.005
OUTPUT VOLTAGE (V)
MAXIMUM OUTPUT VOLTAGE (V)
VOUT = 1.2V
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
3.50
3.00
2.50
2.00
CONDITIONS
VIN = 12V
LOAD = 15A
No Air Flow
No Heat Sink
1.50
1.00
1.004
VIN = 8V
1.003
VIN = 10V
1.002
VIN = 12V
1.001
1.000
0.999
0.998
0.997
CONDITIONS
CONDITIONS
VOUT_NOM
VIN ==5.0V
1.0V
0.996
0.50
0.995
40
45
50
55
60
65
70
AMBIENT TEMPERATURE (°C)
75
80
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.205
1.805
1.204
VIN = 8V
1.203
VIN = 10V
1.202
VIN = 12V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT = 1.0V
1.201
1.200
1.199
1.198
1.197
1.196
1.804
VIN = 8V
1.803
VIN = 10V
1.802
VIN = 12V
1.801
1.800
1.799
1.798
1.797
CONDITIONS
CONDITIONS
VOUT_NOM
VIN ==5.0V
1.2V
1.796
1.195
CONDITIONS
VOUT_NOM = 1.8V
Note: Air flow or heat sink may be required for
higher currents. See derating curves.
1.795
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
www.altera.com/enpirion Page 8
07512
June 2, 2015
Rev D
EN23F0QI
Typical Performance Curves
Output Voltage vs. Output Current
Output Voltage vs. Temperature
1.204
2.504
VIN = 8V
2.503
VIN = 10V
2.502
VIN = 12V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.505
2.501
2.500
2.499
2.498
CONDITIONS
VOUT_NOM = 2.5V
Note: Air flow or heat sink may be required for
higher currents. See derating curves.
2.497
2.496
CONDITIONS
VIN = 8V
VOUT_NOM = 1.2V
1.203
1.202
1.201
1.200
LOAD = 0A
1.199
LOAD = 4A
1.198
LOAD = 8A
1.197
LOAD = 12A
1.196
2.495
-40
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
Output Voltage vs. Temperature
1.204
1.202
OUTPUT VOLTAGE (V)
CONDITIONS
VIN = 10V
VOUT_NOM = 1.2V
1.203
1.201
1.200
LOAD = 0A
1.199
LOAD = 4A
1.198
CONDITIONS
VIN = 12V
VOUT_NOM = 1.2V
1.203
1.202
1.201
1.200
LOAD = 0A
1.199
LOAD = 4A
1.198
LOAD = 8A
1.197
LOAD = 8A
1.197
LOAD = 12A
1.196
LOAD = 12A
1.196
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
-40
1.202
1.201
1.200
LOAD = 0A
1.199
LOAD = 4A
1.198
LOAD = 8A
1.197
LOAD = 12A
1.196
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
INDIVIDUAL OUTPUT CURRENT (A)
CONDITIONS
VIN = 14V
VOUT_NOM = 1.2V
1.203
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
Parallel Current Share Breakdown
Output Voltage vs. Temperature
1.204
OUTPUT VOLTAGE (V)
85
Output Voltage vs. Temperature
1.204
OUTPUT VOLTAGE (V)
-15
10
35
60
AMBIENT TEMPERATURE ( C)
20
17.5
MASTER
15
SLAVE
12.5
IDEAL
10
7.5
CONDITIONS
EN23F0QI
VIN = 12V
VOUT = 1.2V
5
2.5
0
0
5
10
15
20
TOTAL OUTPUT CURRENT (A)
25
www.altera.com/enpirion Page 9
07512
June 2, 2015
Rev D
EN23F0QI
Typical Performance Characteristics
Enable Startup/Shutdown Waveform (0A)
Enable Startup/Shutdown Waveform (5A)
ENABLE
ENABLE
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V, Load = 0A, Css = 47nF
CIN = 3x22µF(1206), COUT = 100µF(1206) + 3x47µF(1206)
CONDITIONS
VIN = 12V, VOUT = 3.3V, Load = 5A, Css = 47nF
CIN = 3x22µF(1206), COUT = 100µF(1206) + 3x47µF(1206)
Enable Startup/Shutdown Waveform (10A)
Enable Startup/Shutdown Waveform (15A)
ENABLE
ENABLE
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V, Load = 10A, Css = 47nF
CIN = 3x22µF(1206), COUT = 100µF(1206) + 3x47µF(1206)
CONDITIONS
VIN = 12V, VOUT = 3.3V, Load = 15A, Css = 47nF
CIN = 3x22µF(1206), COUT = 100µF(1206) + 3x47µF(1206)
Power Up Waveform (0A)
Power Up Waveform (15A)
PVIN
PVIN
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V, Load = 15A, Css = 47nF,
CIN = 3x22µF(1206), COUT = 100µF(1206) + 3x47µF(1206)
CONDITIONS
VIN = 12V, VOUT = 3.3V, Load = 0A, Css = 47nF,
CIN = 3x22µF(1206), COUT = 100µF(1206) + 3x47µF(1206)
www.altera.com/enpirion Page 10
07512
June 2, 2015
Rev D
EN23F0QI
Typical Performance Characteristics
Output Ripple at 20MHz Bandwidth
VOUT = 1V
(AC Coupled)
Output Ripple at 20MHz Bandwidth
VOUT = 1V
(AC Coupled)
LOAD = 0A
VOUT = 1.8V
(AC Coupled)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
20mV / DIV
20mV / DIV
CONDITIONS
VIN = 12V, CIN = 3x22µF (1206), COUT = 3x47µF + 100µF (1206)
CONDITIONS
VIN = 12V, CIN = 3x22µF (1206), COUT = 3x47µF + 100µF (1206)
Output Ripple at 500MHz Bandwidth
Output Ripple at 500MHz Bandwidth
VOUT = 1V
(AC Coupled)
VOUT = 1V
(AC Coupled)
LOAD = 0A
LOAD = 2A
VOUT = 1.8V
(AC Coupled)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
20mV / DIV
20mV / DIV
CONDITIONS
VIN = 12V, CIN = 3x22µF (1206), COUT = 3x47µF + 100µF (1206)
CONDITIONS
VIN = 12V, CIN = 3x22µF (1206), COUT = 3x47µF + 100µF (1206)
Output Ripple at 500MHz Bandwidth
VOUT = 1V
(AC Coupled)
LOAD = 10A
Output Ripple at 500MHz Bandwidth
VOUT = 1V
(AC Coupled)
LOAD = 6A
VOUT = 1.8V
(AC Coupled)
LOAD = 10A
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
20mV / DIV
20mV / DIV
CONDITIONS
VIN = 12V, CIN = 3x22µF (1206), COUT = 3x47µF + 100µF (1206)
CONDITIONS
VIN = 12V, CIN = 3x22µF (1206), COUT = 3x47µF + 100µF (1206)
www.altera.com/enpirion Page 11
07512
June 2, 2015
Rev D
EN23F0QI
Typical Performance Characteristics
Load Transient from 0 to 5A (VOUT =3.3V)
Load Transient from 0 to 10A (VOUT =3.3V)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 3 x 22µF (1206)
COUT = 3 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
Load Transient from 0 to 5A (VOUT =1V)
Load Transient from 0 to 15A (VOUT =3.3V)
VOUT
(AC Coupled)
LOAD
VOUT
(AC Coupled)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 3 x 22µF (1206)
COUT = 3 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
Load Transient from 0 to 10A (VOUT =1V)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 3 x 22µF (1206)
COUT = 3 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
Load Transient from 0 to 15A (VOUT =1V)
VOUT
(AC Coupled)
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 3 x 22µF (1206)
COUT = 3 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
VOUT
(AC Coupled)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 3 x 22µF (1206)
COUT = 3 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 3 x 22µF (1206)
COUT = 3 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
www.altera.com/enpirion Page 12
07512
June 2, 2015
Rev D
EN23F0QI
Functional Block Diagram
M/S S_OUT S_IN
UVLO
Digital I/O
BTMP
PVIN
PG
Linear
Regulator
To PLL
AVINO
Thermal Limit
Short Circuit
Protection
NC(SW)
Gate Drive
VOUT
5k
BGND
(-)
PWM
Comp
(+)
PGND
PLL/Sawtooth
Generator
FADJ
VDDB
Compensation
Networkr
EAIN
Compensation
Network
(-)
Error
Amp
(+)
VFB
Power
Good
Logic
ENABLE
POK
300k
R
SS
Soft Start
Voltage Reference Generator
Band Gap
Reference
EN23F0QI
AVIN
AGND
Figure 4: Functional Block Diagram
Functional Description
small size input and output capacitors, as well as a
wide loop bandwidth within a small foot print.
Synchronous Buck Converter
The EN23F0QI is a highly integrated synchronous,
buck converter with integrated controller, power
MOSFET switches and integrated inductor. The
nominal input voltage (PVIN) range is 4.5V to 14V
and can support up to 15A of continuous output
current. The output voltage is programmed using
an external resistor divider network. The control
loop utilizes a Type IV Voltage-Mode compensation
network and maximizes on a low-noise PWM
topology. Much of the compensation circuitry is
internal to the device. However, a phase lead
capacitor is required along with the output voltage
feedback resistor divider to complete the Type IV
compensation network. The high switching
frequency of the EN23F0QI enables the use of
Protection Features:
The power supply has the following protection
features:
• Short Circuit Protection
• Thermal Shutdown with Hysteresis
• Under-Voltage Lockout Protection
Additional Features:
•
•
•
Switching Frequency Synchronization
Programmable Soft-Start
Power OK Output Monitoring
www.altera.com/enpirion Page 13
07512
June 2, 2015
Rev D
EN23F0QI
Power Up Sequence
The EN23F0QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN. The
EN23F0QI is not “hot pluggable.” Refer to the PVIN
Slew Rate specification on page 4.
Single Input Supply Application (PVIN):
then to ground can be used to enable and disable
the device at a programmed PVIN voltage level.
The lower resistor (2.26k) can be adjusted to set
startup and shutdown at a specific PVIN voltage
level. In this operating mode the minimum PVIN is
6.8V due to the ENABLE threshold. See ENABLE
and DISABLE thresholds in the Electrical
Characteristics table.
Dual Input Supply Application (PVIN and AVIN):
0.1µF
PG
VIN
0.47µF
BTMP VDDB
PVIN
3x
22µF
1206
EAIN
ENABLE
2.26k
AVINO
1µF
1µF
47nF
REA
3x
47µF
1206
RA
CA
VFB
RFS
3x
22µF
1206
OFF
ENABLE
REA
1µF
47nF
RB
M/S
PVIN slew rate limitations
as per datasheet
PVIN – Recommended
to be ramped down
after the Vout softshutdown occurs
VOUT
RB
100k
In this application, place a 1µF, X5R/X7R, capacitor
between AVIN and AGND as close as possible to
AVIN. Refer to Figure 7 for a recommended
schematic for a dual input supply application.
For dual input supply applications, the sequencing
of the two input supplies, PVIN and AVIN, is very
important. There are two common acceptable turnon sequences for the device. AVIN can always
come up before PVIN. If PVIN comes up before
AVIN, then ENABLE must be toggled last, after
AVIN is asserted. Do not turn off AVIN before PVIN
and ENABLE during shutdown. Doing so will
disable the internal controller while there may still
be energy in the system. The device will not softshutdown properly and damage may occur. See
diagram below for a recommended startup and
shutdown sequencing.
12V
PVIN
3.3V
Delay from ENABLE rising
edge to soft start begin
~ 1ms
RCLX
Figure 7: Dual Input Supply Schematic
12V
0V
CA
PGND
FQADJ AGND
100k
The EN23F0QI has an internal linear regulator that
converts PVIN to 3.4V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN on the EN23F0QI. In this application, the
following external components are required: Place
a 1µF, X5R/X7R capacitor between AVINO and
AGND as close as possible to AVINO. Place a 1µF,
X5R/X7R capacitor between AVIN and AGND as
close as possible to AVIN. In addition, place a
resistor (RVB) between VDDB and AVIN, as shown
in Figure 5. Altera recommends RVB=4.75kΩ. In this
application, ENABLE cannot be asserted before
PVIN. See diagram below for a recommended
startup and shutdown sequencing.
ENABLE
RA
RCA
CGND
PGND
Figure 5: Single Input Supply Schematic
0V
3x
47µF
1206
VFB
SS
RFS
PVIN
EAIN
AVIN
M/S
RCLX
VOUT
BGND
VOUT
AVINO
VAVIN
PGND
FQADJ AGND
BTMP VDDB
EN23F0QI
ON
RCA
CGND
PGND
0.47µF
PVIN
AVIN
SS
PG
VIN
EN23F0QI
10k
4.75k
0.1µF
VOUT
BGND
VOUT
0V
PVIN slew rate limitations
as per datasheet
PVIN powered
down before AVIN
3.3V
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Start Time ≈ 2ms
w/Css=47nF
AVIN
AVIN powered up before PVIN
0V
3.3V
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
ENABLE
Figure 6: Single Supply Startup/Shutdown Sequence
If no external enable signal is used, a resister
divider (see Figure 5) from PVIN to ENABLE and
0V
Delay from ENABLE rising
edge to soft start begin
~ 1ms
VOUT
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Start Time ≈ 2ms
w/Css=47nF
PVIN/AVIN –
Recommended
to be ramped down
after the Vout softshutdown occurs
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
Figure 8: Dual Supply Startup/Shutdown Sequencing
www.altera.com/enpirion Page 14
07512
June 2, 2015
Rev D
EN23F0QI
Enable Operation
Pre-Bias Precaution
The EN23F0QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN23F0QI is not pre-biased when the EN23F0QI is
first enabled.
Frequency Synchronization
The switching frequency of the EN23F0QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN23F0QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the presence of
an external clock signal and automatically phaselocks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.8MHz to 1.8MHz. The
external clock frequency must be within ±10% of
the nominal switching frequency set by the RFS
resistor. It is recommended to use a synchronized
clock frequency close to the typical frequency
recommendations in Table 1. A 3.01kΩ resistor
from FQADJ to ground is recommended for clock
frequencies within ±10% of 1MHz. When no clock
is present, the device reverts to the free running
frequency of the internal oscillator set by the RFS
resistor.
The efficiency performance of the EN23F0QI for
various PVIN/VOUT combinations can be optimized
by adjusting the switching frequency. Table 1
shows recommended RFS values for various
PVIN/VOUT combinations in order to optimize
performance of the EN23F0QI.
Rfs vs. SW Frequency
1.800
SWITCHING FREQUENCY (MHz)
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft-start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Time (8ms) in order for the device to be reenabled. To ensure accurate startup sequencing
the ENABLE/DISABLE signal should be faster than
1V/100µs. A slower ENABLE/DISABLE signal may
result in a delayed startup and shutdown response.
Do not leave ENABLE floating.
1.600
1.400
1.200
1.000
CONDITIONS
VIN = 6V to 12V
VOUT = 0.8V to 3.3V
0.800
0.600
0
2
4
6
8 10 12 14 16 18 20 22
RFS RESISTOR VALUE (kΩ)
Figure 9. RFS versus Switching Frequency
The efficiency performance of the EN23F0QI for
various VOUTs can be optimized by adjusting the
switching frequency. Table 1 shows recommended
RFS values for various VOUTs in order to optimize
performance of the EN23F0QI.
PVIN
12V
5V
VOUT
3.3V
2.5V
1.8V
1.5V
1.2V
<1.0V
2.5V
1.8V
1.5V
1.2V
<1.0V
RFS
22k
10k
4.87k
3.01k
1.65k
1.3k
22.1k
10k
6.65k
4.87k
3.01k
Typical fsw
1.42 MHz
1.3 MHz
1.15 MHz
1.0 MHz
0.95 MHz
0.8 MHz
1.4 MHz
1.3 MHz
1.25 MHz
1.15 MHz
1.0 MHz
Table 1: Recommended RFS Values
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin and
the AGND pin. During start-up of the converter, the
reference voltage to the error amplifier is linearly
increased to its final level by an internal current
source of approximately 10µA. The soft-start time is
measured from when VIN > VUVLOR and ENABLE pin
voltage crosses its logic high threshold to when
VOUT reaches its programmed value. The total softstart time can be calculated by:
Soft Start Time (ms): T SS ≈ Css [nF] x 0.06
www.altera.com/enpirion Page 15
07512
June 2, 2015
Rev D
EN23F0QI
POK Operation
The POK signal is an open drain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Short Circuit Protection
The short circuit protection feature will protect the
device if the output is shorted to ground. Short
circuit protection is achieved by sensing the current
flowing through a sense PFET. When the sensed
current exceeds the threshold for more than 32
cycles, both power FETs are turned off for the rest
of the switching cycle. If the short circuit condition
is removed, the device will reactivate soft-start and
resume PWM operation. In the event the short
circuit trips consistently in normal operation, the
device enters a hiccup mode. While in hiccup
mode, the device is disabled for a short while and
restarted with a normal soft-start. The hiccup time
is approximately 32ms. This cycle can continue
indefinitely as long as the short circuit condition
persists. Use a resistor value of 100k from the
RCLX pin to ground to enable this feature.
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the junction temperature exceeds
approximately 160ºC. After a thermal shutdown
event, when the junction temperature drops by
approx 35ºC, the converter will re-start with a
normal soft-start.
AVIN Under-Voltage Lock-Out (UVLO)
Internal circuits ensure that the converter will not
start switching until the input voltage is above the
specified minimum voltage. Hysteresis, input deglitch and output leading edge blanking ensures
Master / Slave (Parallel) Operation:
Up to four EN23F0QI devices may be connected in
a Master/Slave configuration to handle larger load
currents. The maximum output current for each
parallel device will need to be de-rated by 20
percent so that no devices will over current due to
current mis-match. The Master device’s switching
clock may be phase-locked to an external clock
source via the S_IN pin or left open and use its
default switching frequency. The device is placed in
Master mode by pulling the M/S pin low or in Slave
mode by pulling M/S pin high. Note that the M/S pin
is also pulled low for standalone mode. In Master
mode, the internal PWM signal is output on the
S_OUT pin. This PWM signal from the Master is
fed to the Slave device at its S_IN input. The Slave
device acts like an extension of the power FETs in
the Master. The inductor in the Slave prevents
crow-bar currents from Master to Slave due to
timing delays. Parallel operation in dual supply
mode is shown in Figure 11. Single supply mode
operation may also be implemented, but be sure
not to tie AVINs together. Note that only critical
components are shown. The red text and red lines
indicate
the important parallel operation
connections and care should be taken in layout to
ensure low impedance between those paths. The
parallel current matching is illustrated in Figure 10
Parallel Current Share Breakdown
INDIVIDUAL OUTPUT CURRENT (A)
Typical soft-start time is approximately 2.8ms with
SS capacitor value of 47nF.
high noise immunity and prevents false UVLO
triggers.
20
17.5
MASTER
15
SLAVE
12.5
IDEAL
10
7.5
CONDITIONS
EN23F0QI
VIN = 12V
VOUT = 1.2V
5
2.5
0
0
5
10
15
20
TOTAL OUTPUT CURRENT (A)
25
Figure 10. Parallel Current Matching
www.altera.com/enpirion Page 16
07512
June 2, 2015
Rev D
EN23F0QI
Note 2:
The Master and Slave VOUTs should
be connected with very low
iµpedance as shown by the double
red line connections in parallel.
Note 1:
The Master and Slave VINs should be connected
with very low iµpedance as shown by the double
red line connections in parallel.
VIN
PVIN
ENA
3x
22µF
1206
AVIN
AVIN
3x
47µF
1206
EN23F0QI
(MASTER)
RA CA
VFB
SS
47nF
VOUT
VOUT
R1
M/S
PGND
PGND
S_OUT AGND
RB
FQADJ
S_IN
PVIN
AVIN
3x
22µF
1206
15k
VOUT
ENA
3x
47µF
1206
EN23F0QI
(SLAVE)
AVIN
VFB
M/S
open
SS
PGND
PGND
FQADJ
AGND
47nF
Slave #1
Note 4:
Up to 3 Slaves µay
be used in parallel
with the Master
Note 3:
The Master and Slave PGNDs should be
connected with very low iµpedance as shown by
the double red line connections in parallel.
Figure 11. Parallel Operation Illustration
www.altera.com/enpirion Page 17
07512
June 2, 2015
Rev D
EN23F0QI
Application Information
Output Voltage Programming and Loop
Compensation
The EN23F0QI uses a Type IV Voltage Mode
compensation network. Type IV Voltage Mode
control is a proprietary Altera Enpirion control
scheme that maximizes control loop bandwidth to
deliver excellent load transient responses and
maintain output regulation with pin point accuracy.
For ease of use, most of this network has been
customized and is integrated within the device
package. The EN23F0QI output voltage is
programmed using a simple resistor divider network
(RA and RB). The feedback voltage at VFB is
nominally 0.6V. RA is predetermined based on
Table 4 and RB can be calculated based on Figure
12. The values recommended for COUT, CA, RCA and
REA make up the external compensation of the
EN23F0QI. It will vary with each PVIN and VOUT
combination to optimize on performance. The
EN23F0QI solution can be optimized for either
smallest size or highest performance. Please see
Table 4 for a list of recommended RA, CA, RCA, REA
and COUT values for each solution. Since VFB is a
sensitive node, do not touch the VFB node while
the device is in operation as doing so may
introduce parasitic capacitance into the control loop
that causes the device to behave abnormally and
damage may occur.
VOUT
COUT
RA
CA
REA
RCA
VFB
VFB = 0.6V
PGND
RB =
EN23F0QI
Recommended Input Capacitors
Description
MFG
P/N
22µF, 16V, X5R,
10%, 1206
Murata
GRM31CR61C226ME15
22µF, 16V, X5R,
20%, 1206
Taiyo
Yuden
EMK316ABJ226ML- T
22µF, 25V, X5R,
10%, 1210
Murata
GRM32ER61E226KE15L
22µF, 25V, X5R,
20%, 1210
Taiyo
Yuden
TMK325BJ226MM- T
Table 2: Recommended Input Capacitors
Output Capacitor Selection
As seen from Table 4, the EN23F0QI has been
optimized for use with one 100µF/1206 plus three
47µF/1206 output capacitors for best performance.
For smallest solution size, various combinations of
output capacitance may be used. See Table 4 for
details. Low ESR ceramic capacitors are required
with X5R or X7R rated dielectric formulation. Y5V
or equivalent dielectric formulations must not
be used as these lose too much capacitance
with frequency, temperature and bias voltage.
Table 3 contains a list of recommended output
capacitors.
Output ripple voltage is determined by the
aggregate output capacitor impedance. Capacitor
impedance, denoted as Z, is comprised of
capacitive reactance, effective series resistance,
ESR, and effective series inductance, ESL
reactance.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
VOUT
EAIN
capacitors are needed in parallel with the larger,
capacitors in order to provide high frequency
decoupling. Table 2 contains a list of recommended
input capacitors.
VFB x RA
1
VOUT - VFB
Figure 12: VOUT Resistor Divider & Compensation
Components. See Table 4 for details.
Input Capacitor Selection
The EN23F0QI requires three 22µF/1206 input
capacitor. Low-cost, low-ESR ceramic capacitors
should be used as input capacitors for this
converter. The dielectric must be X5R or X7R
rated. Y5V or equivalent dielectric formulations
must not be used as these lose too much
capacitance with frequency, temperature and
bias voltage. In some applications, lower value
Z Total
=
1
1
1
+
+ ... +
Z1 Z 2
Zn
Recommended Output Capacitors
Description
47µF, 6.3V, X5R,
20%, 1206
47µF, 10V, X5R,
20%, 1206
22µF, 10V, X5R,
20%, 0805
100µF, 6.3V,
X5R, 20%, 1206
MFG
P/N
Murata
GRM31CR60J476ME19L
Taiyo Yuden
LMK316BJ476ML- T
Taiyo Yuden
LMK212BJ226MG- T
Murata
GRM31CR60J107ME39L
Taiyo Yuden
JMK316BJ107ML-T
Table 3: Recommended Output Capacitors
www.altera.com/enpirion Page 18
07512
June 2, 2015
Rev D
EN23F0QI
Best Performance
Smallest Solution Size
CIN = 3 x 22µF/1206
CIN = 3 x 22µF/1206
VOUT ≤ 1.8V, COUT = 22µF/0805 + 2x47µF/0805
3.3V > VOUT> 1.8V, COUT = 3x47µF/1206
RA = 100 kΩ
COUT = 3x47µF (1206) + 100µF(1206)
RA = 200 kΩ
PVIN VOUT
(V)
(V)
14V
12V
10V
8V
6.6V
5V
CA RCA REA
(pF) (kΩ) (kΩ)
Ripple
(mV)
Deviation
(mV)
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
27
27
27
15
15
15
27
27
27
15
15
15
27
27
27
15
15
15
27
27
27
15
15
15
27
27
27
15
15
15
27
27
15
15
15
15
15
15
15
15
15
15
15
15
5
5
5
15
15
15
5
5
5
5
5
5
1
1
1
5
5
5
1
1
200
200
200
86
86
86
200
200
200
86
86
86
86
86
86
86
86
86
86
86
86
86
86
86
86
86
86
86
86
86
86
86
25.6
24
26.4
28.4
31.6
37.3
21.6
22.7
25.2
25.8
30
30.8
18.8
20.4
22
23.6
26.5
28.9
17.2
18.7
20.1
20.9
23.6
22.8
13.8
15.2
16.4
19.6
20.4
21.1
12.4
13.4
40
42
60
70
86
96
42
48
70
72
82
110
46
54
60
78
92
132
64
64
70
100
120
156
74
76
88
116
148
204
92
100
1.5V
1.8V
2.5V
27
15
15
1
5
5
86
86
86
14.3
15.4
15.5
120
160
204
PVIN
(V)
14V
12V
10V
8V
6.6V
5V
VOUT
(V)
CA RCA
(pF) (kΩ)
REA
(kΩ)
Ripple
(mV)
Deviation
(mV)
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
1.0V
1.2V
12
12
12
12
15
10
22
22
18
18
22
15
56
47
39
33
33
22
200
200
150
82
68
39
200
200
200
150
100
56
200
200
36
36
36
36
27
27
27
27
27
27
27
27
20
20
20
20
20
20
10
10
10
10
10
10
10
10
10
10
10
10
10
10
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
15
18
22
25
32
46
15
18
21
24
30
43
15
17
20
22
29
41
14
16
19
20
27
36
13
15
17
19
24
32
12
13
78
93
104
130
162
200
84
97
118
130
172
213
85
100
120
140
177
230
83
90
107
138
178
239
99
105
118
138
183
250
123
132
1.5V
1.8V
2.5V
200
200
100
10
10
10
Open
Open
Open
16
17
20
145
156
216
3.3V
15
5
86
12.9
300
3.3V 100
10
Open
21
253
Table 4: RA, CA, RCA and REA Values for Various PVIN/VOUT Combinations: Best Performance vs. Smallest Solution
Size. Use the equations in Figure 12 to calculate RB. Output ripple is measured at no load and nominal deviation is for a
15A load transient step. For compensation values of output voltage in between the specified output voltages, choose
compensation values of the lower output voltage setting.
www.altera.com/enpirion Page 19
07512
June 2, 2015
Rev D
EN23F0QI
Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
η = POUT / PIN = 80% = 0.8
The Altera Enpirion EN23F0QI DC-DC converter is
packaged in a 13x12x3mm 92-pin QFN package.
The QFN package is constructed with copper lead
frames that have an exposed thermal pad. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
160°C.
PD = PIN – POUT
The following example and calculations illustrate
the thermal performance of the EN23F0QI.
Example:
VIN = 12V
VOUT = 1.2V
PIN ≈ 18W / 0.8 ≈ 22.5W
The power dissipation (PD ) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
≈ 22.5W – 18W ≈ 4.5W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN23F0QI has
a θJA value of 13 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 4.5W x 13°C/W = 58.5°C ≈ 59°C
The junction temperature (T J ) of the device is
approximately the ambient temperature (T A) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
T J = T A + ΔT
T J ≈ 25°C + 59°C ≈ 84°C
IOUT = 15A
First calculate the output power.
POUT = 1.2V x 15A = 18W
Next, determine the input power based on the
efficiency (η) shown in Figure 13.
Efficiency vs. Output Current
100
80
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
VOUT = 1.0V
10
The maximum operating junction temperature
(T JMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (T AMAX) allowed can
be calculated.
T AMAX = T JMAX – PD x θJA
≈ 125°C – 59°C ≈ 66°C
The maximum ambient temperature the device can
reach is 66°C given the input and output conditions.
Note that the efficiency will be slightly lower at
higher temperatures and this calculation is an
estimate. Check De-rating Curves for guaranteed
maximum output current over temperature.
90
EFFICIENCY (%)
PIN = POUT / η
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
0
0
1
2
3
4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
Figure 13: Efficiency vs. Output Current
For VIN = 12V, VOUT = 1.2V at 15A, η ≈ 80%
www.altera.com/enpirion Page 20
07512
June 2, 2015
Rev D
EN23F0QI
Engineering Schematic
A single through-hole test point connects
the AGND pin to the GND plane.
An optional resistor (Rea) may be
connected from VFB to EAIN
for control loop optimization
Css
0402
47n
X7R
Rclx
0402
100k
Rf s
22k
M/S must be tied to
the ground plane for
stand alone operation
Cav in
1u
0402
X7R
EAIN
Rfs values chosen
for 12Vin/3.3Vout
Enable can also be
driven with an external
logic signal depending
on the application.
POK
AGND
71
POK
72
73
AVIN
ENABLE
75
76
74
AGND
M/S
VFB
77
78
SS
EAIN
80
79
RCLX
FQADJ
81
NC81
83
82
PVIN
{
PVIN
70
69
68
67
66
65
Cin1
Cout2
Cin2
Rv b
4.75k
0402
Cpg
0.1u
0402
X5R
64
63
Cav ino
1u
0402
X7R
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
PVIN = 12V
}
Cin1--Cin3: 22u
1206
25V
X5R
Cin3
Output capacitors & compensation
network optimized for 12Vin to
3.3Vout. See datasheet for other
Vin/Vout cases.
Cb
0.47u
0402
X5R
PVIN
Cout1
Cout3
Choose RPOK so that
the max sink current
is not exceeded.
46
45
44
43
42
41
40
34
33
32
31
PGND
NC23
PGND
PVIN
PGND
PVIN
NC22
PGND
NC21
PGND
PVIN
PGND
PVIN
NC20
PGND
NC19
NC(SW)39
PVIN
VOUT
NC18
NC24
Cout1-Cout3: 47u
1206
6.3V
X5R
CGND
NC(SW)83
85
84
NC(SW)84
NC(SW)85
PVIN
VOUT
PVIN
NC17
VOUT
NC16
25
0402
86
PVIN
VOUT
PVIN
NC15
VOUT
24
NC14
VOUT
23
PVIN
30
22
PVIN
NC13
29
21
0201
87
U1
EN23F0
VOUT
20
0402
NC(SW)86
PVIN
VOUT
19
0402
88
PVIN
NC11
28
18
Rb
22.1k
NC(SW)87
NC10
27
17
27k
NC(SW)88
PVIN
VOUT
16
Rca
89
NC9
VOUT
15
Ra
100k
90
PVIN
26
14
Ca
15p
91
AVINO
NC8
NC12
13
VOUT
NC7
39
12
PG
NC(SW)38
11
NC6
NC(SW)37
10
BTMP
38
9
VDDB
NC5
NC36
8
NC4
37
7
S_IN
36
6
S_OUT
BGND
VOUT
5
0402
100k
NC3
35
4
NC(SW)89
NC2
3
NC(SW)90
NC1
2
NC(SW)91
1
NC(SW)92
92
RPOK
Connect input and output caps
to GND plane through mulitple
vias. (See the Gerber files.)
Figure 14: Engineering Schematic for Smallest Solution Size
www.altera.com/enpirion Page 21
07512
June 2, 2015
Rev D
EN23F0QI
Layout Recommendation
Figure 15: Top Layer Layout with Critical Components
(Top View). See Figure 14 for corresponding schematic.
This layout only shows the critical components and top
layer traces for minimum footprint in single-supply mode.
Alternate circuit configurations & other low-power pins
need to be connected and routed according to customer
application. Please see the Gerber files at
www.altera.com/enpirion for details on all layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of the
PCB, and as close to the EN23F0QI package as
possible. They should be connected to the device with
very short and wide traces. Do not use thermal reliefs
or spokes when connecting the capacitor pads to the
respective nodes. The +V and GND traces between
the capacitors and the EN23F0QI should be as close
to each other as possible so that the gap between the
two nodes is minimized, even under the capacitors.
Recommendation 2: The PGND connections for the
input and output capacitors on layer 1 need to have a
slit between them in order to provide some separation
between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The thermal pad underneath
the component must be connected to the system
ground plane through as many vias as possible. The
drill diameter of the vias should be 0.33mm, and the
vias must have at least 1 oz. copper plating on the
inside wall, making the finished hole size around 0.200.26mm. Do not use thermal reliefs or spokes to
connect the vias to the ground plane. This connection
provides the path for heat dissipation from the
converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in recommendation
4) should be used to connect ground terminal of the
input capacitor and output capacitors to the system
ground plane. It is preferred to put these vias along
the edge of the GND copper closest to the +V copper.
These vias connect the input/output filter capacitors to
the GND plane, and help reduce parasitic inductances
in the input and output current loops. If vias cannot be
placed under the capacitors, then place them on both
sides of the slit in the top layer PGND copper.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. AVINO powers AVIN
in single supply mode. AVIN and AVINO should have
a decoupling capacitor close to each of their pins.
Refer to Figure 15.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure 15.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode DC/DC
converter, try not to run sensitive signal or control
lines underneath the converter package on other
layers.
Recommendation 8: The VOUT sense point should be
just after the last output filter capacitor. Keep the
sense trace short in order to avoid noise coupling into
the node. Contact Altera MySupport for any remote
sensing applications.
Recommendation 9: Keep RA, CA, RB, and RCA close
to the VFB pin (Refer to Figure 15). The VFB pin is a
high-impedance, sensitive node. Keep the trace to
this pin as short as possible. Whenever possible,
connect RB directly to the AGND instead of going
through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Altera provides schematic and layout
reviews for all customer designs. Contact Altera
for
detailed
support
MySupport
(www.altera.com/mysupport).
www.altera.com/enpirion Page 22
07512
June 2, 2015
Rev D
EN23F0QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 16.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EN23F0QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 16 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult the
EN23F0 Package Soldering Guidelines for more details and recommendations.
Figure 16: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
www.altera.com/enpirion Page 23
07512
June 2, 2015
Rev D
EN23F0QI
Recommended PCB Footprint
Figure 17: EN23F0QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad (shown in blue) is based on Altera’s manufacturing recommendations.
www.altera.com/enpirion Page 24
07512
June 2, 2015
Rev D
EN23F0QI
Package and Mechanical
Figure 18: EN23F0QI Package Dimensions (Bottom View)
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
www.altera.com/enpirion Page 25
07512
June 2, 2015
Rev D