Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 DNU DNU RREF_TL GXB_TX_L8n GXB_TX_L8p GXB_RX_L8p,GXB_REFCLK_L8p GXB_RX_L8n,GXB_REFCLK_L8n GXB_TX_L7n GXB_TX_L7p GXB_RX_L7p,GXB_REFCLK_L7p GXB_RX_L7n,GXB_REFCLK_L7n GXB_TX_L6n GXB_TX_L6p GXB_RX_L6p,GXB_REFCLK_L6p GXB_RX_L6n,GXB_REFCLK_L6n REFCLK2Ln REFCLK2Lp REFCLK1Ln REFCLK1Lp GXB_TX_L5n GXB_TX_L5p GXB_RX_L5p,GXB_REFCLK_L5p GXB_RX_L5n,GXB_REFCLK_L5n GXB_TX_L4n GXB_TX_L4p GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_TX_L3n GXB_TX_L3p GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_TX_L2n GXB_TX_L2p GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n GXB_TX_L1n GXB_TX_L1p GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_TX_L0n GXB_TX_L0p GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n REFCLK0Ln REFCLK0Lp DNU TDO TMS TCK TDI DCLK nCSO AS_DATA3 AS_DATA2 AS_DATA1 AS_DATA0,ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3D 3D 3D 3D PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel TDO TMS TCK TDI DCLK DATA4 DATA3 DATA2 DATA1 DATA0 RZQ_0 CLK0n CLK0p CLK1n CLK1p FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB0 FPLL_BL_CLKOUT3,FPLL_BL_FBn FPLL_BL_CLKOUT2,FPLL_BL_FBp,FPLL_BL_FB1 VREFB3AN0 CLK2n CLK2p CLK3n CLK3p DIFFIO_TX_B1n DIFFIO_TX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_TX_B3n DIFFIO_TX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_TX_B5n DIFFIO_TX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_TX_B8n DIFFIO_TX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_TX_B10n DIFFIO_TX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_TX_B12n DIFFIO_TX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p DIFFIO_TX_B14n DIFFIO_TX_B14p DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_TX_B70n DIFFIO_TX_B70p DIFFIO_RX_B71n DIFFIO_RX_B71p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B70n DIFFOUT_B70p DIFFOUT_B71n DIFFOUT_B71p Pin List GF31 F896 E29 F29 F30 G27 G28 H30 H29 J27 J28 K30 K29 L27 L28 M30 M29 R23 R22 U23 U22 N27 N28 P30 P29 R27 R28 T30 T29 U27 U28 V30 V29 W27 W28 Y30 Y29 AA27 AA28 AB30 AB29 AC27 AC28 AD30 AD29 W23 W22 AB26 AF30 AG30 AG29 AF29 AJ29 AA25 AH30 AJ30 AK29 AK28 AF28 AG28 AF27 AG27 AE27 AE26 AH28 AJ28 AJ27 AK27 AB25 AC25 AD25 AE25 AG26 AH26 AK26 AK25 AF25 AG25 AB23 AB24 AH25 AJ25 AC24 AD24 AF24 AG24 AD23 AE23 AJ24 AK24 AC22 AD22 AA22 AB22 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ1B DQ1B DQ1B DQ1B DQSn1B/QK1B DQS1B/CQ1B/CQn1B/QKn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B DQSn2B/QK2B DQS2B/CQ2B/CQn2B/QKn2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B Page 1 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCD_FPLL VCCA_FPLL DNU IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DIFFIO_TX_B72n DIFFIO_TX_B72p DIFFIO_RX_B73n DIFFIO_RX_B73p DIFFIO_TX_B74n DIFFIO_TX_B74p DIFFIO_RX_B75n DIFFIO_RX_B75p DIFFOUT_B72n DIFFOUT_B72p DIFFOUT_B73n DIFFOUT_B73p DIFFOUT_B74n DIFFOUT_B74p DIFFOUT_B75n DIFFOUT_B75p DIFFIO_RX_B76n DIFFIO_RX_B76p DIFFIO_TX_B77n DIFFIO_TX_B77p DIFFIO_RX_B78n DIFFIO_RX_B78p DIFFIO_TX_B79n DIFFIO_TX_B79p DIFFIO_RX_B80n DIFFIO_RX_B80p DIFFIO_TX_B81n DIFFIO_TX_B81p DIFFIO_RX_B82n DIFFIO_RX_B82p DIFFIO_TX_B83n DIFFIO_TX_B83p DIFFIO_RX_B84n DIFFIO_RX_B84p DIFFOUT_B76n DIFFOUT_B76p DIFFOUT_B77n DIFFOUT_B77p DIFFOUT_B78n DIFFOUT_B78p DIFFOUT_B79n DIFFOUT_B79p DIFFOUT_B80n DIFFOUT_B80p DIFFOUT_B81n DIFFOUT_B81p DIFFOUT_B82n DIFFOUT_B82p DIFFOUT_B83n DIFFOUT_B83p DIFFOUT_B84n DIFFOUT_B84p DIFFIO_TX_B93n DIFFIO_TX_B93p DIFFIO_RX_B94n DIFFIO_RX_B94p DIFFIO_TX_B95n DIFFIO_TX_B95p DIFFIO_RX_B96n DIFFIO_RX_B96p DIFFIO_TX_B97n DIFFIO_TX_B97p DIFFIO_RX_B98n DIFFIO_RX_B98p DIFFOUT_B93n DIFFOUT_B93p DIFFOUT_B94n DIFFOUT_B94p DIFFOUT_B95n DIFFOUT_B95p DIFFOUT_B96n DIFFOUT_B96p DIFFOUT_B97n DIFFOUT_B97p DIFFOUT_B98n DIFFOUT_B98p DIFFIO_RX_B99n DIFFIO_RX_B99p DIFFIO_TX_B100n DIFFIO_TX_B100p DIFFIO_RX_B101n DIFFIO_RX_B101p DIFFIO_TX_B102n DIFFIO_TX_B102p DIFFIO_RX_B103n DIFFIO_RX_B103p DIFFIO_TX_B104n DIFFIO_TX_B104p DIFFIO_RX_B105n DIFFIO_RX_B105p DIFFIO_TX_B106n DIFFIO_TX_B106p DIFFIO_RX_B107n DIFFIO_RX_B107p DIFFIO_TX_B108n DIFFIO_TX_B108p DIFFIO_RX_B109n DIFFIO_RX_B109p DIFFIO_TX_B110n DIFFIO_TX_B110p DIFFIO_RX_B111n DIFFIO_RX_B111p DIFFIO_TX_B112n DIFFIO_TX_B112p DIFFIO_RX_B113n DIFFIO_RX_B113p DIFFOUT_B99n DIFFOUT_B99p DIFFOUT_B100n DIFFOUT_B100p DIFFOUT_B101n DIFFOUT_B101p DIFFOUT_B102n DIFFOUT_B102p DIFFOUT_B103n DIFFOUT_B103p DIFFOUT_B104n DIFFOUT_B104p DIFFOUT_B105n DIFFOUT_B105p DIFFOUT_B106n DIFFOUT_B106p DIFFOUT_B107n DIFFOUT_B107p DIFFOUT_B108n DIFFOUT_B108p DIFFOUT_B109n DIFFOUT_B109p DIFFOUT_B110n DIFFOUT_B110p DIFFOUT_B111n DIFFOUT_B111p DIFFOUT_B112n DIFFOUT_B112p DIFFOUT_B113n DIFFOUT_B113p DIFFIO_RX_B114n DIFFIO_RX_B114p DIFFIO_TX_B115n DIFFIO_TX_B115p DIFFIO_RX_B116n DIFFIO_RX_B116p DIFFIO_TX_B117n DIFFIO_TX_B117p DIFFIO_RX_B118n DIFFIO_RX_B118p DIFFIO_TX_B119n DIFFIO_TX_B119p DIFFIO_RX_B120n DIFFIO_RX_B120p DIFFIO_TX_B121n DIFFOUT_B114n DIFFOUT_B114p DIFFOUT_B115n DIFFOUT_B115p DIFFOUT_B116n DIFFOUT_B116p DIFFOUT_B117n DIFFOUT_B117p DIFFOUT_B118n DIFFOUT_B118p DIFFOUT_B119n DIFFOUT_B119p DIFFOUT_B120n DIFFOUT_B120p DIFFOUT_B121n AB21 AC21 AG23 AH23 AD21 AE22 AF22 AG22 AA21 Y20 AH22 AJ22 AD20 AE20 AF21 AG21 AA19 AB19 AG20 AH20 AA20 AB20 AJ21 AK22 AC19 AD19 AK20 AK21 W15 W16 Y16 AJ19 AK19 AF19 AG19 AC18 AD18 AH19 AH18 AA18 AB18 AE18 AF18 AD17 AE17 AA17 AB17 AA16 AB16 AG17 AH17 AC16 AD16 AJ18 AK17 AF16 AG16 AA15 AB15 AC15 AD15 AJ16 AK16 AA14 AB14 AG15 AH15 AE15 AF15 AJ15 AK14 AG14 AH14 AD13 AE13 AD14 AE14 AH13 AJ13 AC13 AD12 AF12 AF13 AA13 AB13 AG12 AH12 AJ12 AK12 AB12 AC12 Y12 VREFB3DN0 CLK4n CLK4p CLK5n CLK5p FPLL_BC_CLKOUT1,FPLL_BC_CLKOUTn FPLL_BC_CLKOUT0,FPLL_BC_CLKOUTp,FPLL_BC_FB0 FPLL_BC_CLKOUT3,FPLL_BC_FBn FPLL_BC_CLKOUT2,FPLL_BC_FBp,FPLL_BC_FB1 CLK6n CLK6p CLK7n CLK7p VREFB4DN0 VREFB4CN0 Pin List GF31 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ3B DQSn3B/QK3B DQS3B/CQ3B/CQn3B/QKn3B DQ1B DQ1B DQ1B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ4B DQSn4B/QK4B DQS4B/CQ4B/CQn4B/QKn4B DQ1B DQSn1B/QK1B DQS1B/CQ1B/CQn1B/QKn1B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ5B DQSn5B/QK5B DQS5B/CQ5B/CQn5B/QKn5B DQ2B DQ2B DQ2B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DQ6B DQSn6B/QK6B DQS6B/CQ6B/CQn6B/QKn6B DQ2B DQSn2B/QK2B DQS2B/CQ2B/CQn2B/QKn2B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B A_4D_14 A_4D_13 A_4D_12 A_4D_11 A_4D_10 A_4D_9 A_4D_8 A_4D_7 A_4D_6 A_4D_5 A_4D_4 A_4D_3 A_4D_2 A_4D_1 A_4D_0 CKE_4D_1 CKE_4D_0 CK#_4D CK_4D RESET#_4D DQ1_4C_8 DQ1_4C_7 DQ1_4C_6 DQ7B DQSn7B/QK7B DQS7B/CQ7B/CQn7B/QKn7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DM1_4C DQS#1_4C DQS1_4C DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1_4C_5 DQ1_4C_4 DQ1_4C_3 DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1_4C_2 DQ1_4C_1 DQ1_4C_0 DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ2_4C_8 DQ2_4C_7 DQ2_4C_6 DQ8B DQSn8B/QK8B DQS8B/CQ8B/CQn8B/QKn8B DQ3B DQSn3B/QK3B DQS3B/CQ3B/CQn3B/QKn3B DQ1B DQ1B DQ1B DM2_4C DQS#2_4C DQS2_4C DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ2_4C_5 DQ2_4C_4 DQ2_4C_3 CS#_4D_1 CS#_4D_0 A_4D_15 ODT_4D_1 ODT_4D_0 WE#_4D CAS#_4D RAS#_4D BA_4D_2 BA_4D_1 BA_4D_0 Page 2 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) 4C 4C 4C 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO RREF_BR DNU DNU REFCLK0Rp REFCLK0Rn GXB_RX_R0n,GXB_REFCLK_R0n GXB_RX_R0p,GXB_REFCLK_R0p GXB_TX_R0p GXB_TX_R0n GXB_RX_R1n,GXB_REFCLK_R1n GXB_RX_R1p,GXB_REFCLK_R1p GXB_TX_R1p GXB_TX_R1n GXB_RX_R2n,GXB_REFCLK_R2n GXB_RX_R2p,GXB_REFCLK_R2p GXB_TX_R2p GXB_TX_R2n REFCLK2Rp REFCLK2Rn GXB_RX_R6n,GXB_REFCLK_R6n GXB_RX_R6p,GXB_REFCLK_R6p GXB_TX_R6p GXB_TX_R6n GXB_RX_R7n,GXB_REFCLK_R7n GXB_RX_R7p,GXB_REFCLK_R7p GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DIFFIO_TX_B121p DIFFIO_RX_B122n DIFFIO_RX_B122p DIFFIO_TX_B123n DIFFIO_TX_B123p DIFFIO_RX_B124n DIFFIO_RX_B124p DIFFIO_TX_B125n DIFFIO_TX_B125p DIFFIO_RX_B126n DIFFIO_RX_B126p DIFFIO_TX_B127n DIFFIO_TX_B127p DIFFIO_RX_B128n DIFFIO_RX_B128p DIFFIO_TX_B129n DIFFIO_TX_B129p DIFFIO_RX_B130n DIFFIO_RX_B130p DIFFIO_TX_B131n DIFFIO_TX_B131p DIFFIO_RX_B132n DIFFIO_RX_B132p DIFFIO_TX_B133n DIFFIO_TX_B133p DIFFIO_RX_B134n DIFFIO_RX_B134p DIFFIO_TX_B135n DIFFIO_TX_B135p DIFFIO_RX_B136n DIFFIO_RX_B136p DIFFOUT_B121p DIFFOUT_B122n DIFFOUT_B122p DIFFOUT_B123n DIFFOUT_B123p DIFFOUT_B124n DIFFOUT_B124p DIFFOUT_B125n DIFFOUT_B125p DIFFOUT_B126n DIFFOUT_B126p DIFFOUT_B127n DIFFOUT_B127p DIFFOUT_B128n DIFFOUT_B128p DIFFOUT_B129n DIFFOUT_B129p DIFFOUT_B130n DIFFOUT_B130p DIFFOUT_B131n DIFFOUT_B131p DIFFOUT_B132n DIFFOUT_B132p DIFFOUT_B133n DIFFOUT_B133p DIFFOUT_B134n DIFFOUT_B134p DIFFOUT_B135n DIFFOUT_B135p DIFFOUT_B136n DIFFOUT_B136p DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ3_4B_8 DQ3_4B_7 DQ3_4B_6 DQ9B DQSn9B/QK9B DQS9B/CQ9B/CQn9B/QKn9B DQ4B DQ4B DQ4B DQ1B DM3_4B DQSn1B/QK1B DQS#3_4B DQS1B/CQ1B/CQn1B/QKn1B DQS3_4B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ3_4B_5 DQ3_4B_4 DQ3_4B_3 DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ3_4B_2 DQ3_4B_1 DQ3_4B_0 DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ4_4B_8 DQ4_4B_7 DQ4_4B_6 DQ10B DQSn10B/QK10B DQS10B/CQ10B/CQn10B/QKn10B DQ4B DQSn4B/QK4B DQS4B/CQ4B/CQn4B/QKn4B DQ1B DQ1B DQ1B DM4_4B DQS#4_4B DQS4_4B DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ4_4B_5 DQ4_4B_4 DQ4_4B_3 DIFFIO_RX_B137n DIFFIO_RX_B137p DIFFIO_TX_B154n DIFFIO_TX_B154p DIFFIO_RX_B155n DIFFIO_RX_B155p DIFFIO_TX_B156n DIFFIO_TX_B156p DIFFIO_RX_B157n DIFFIO_RX_B157p DIFFIO_TX_B158n DIFFIO_TX_B158p DIFFIO_RX_B159n DIFFIO_RX_B159p DIFFOUT_B137n DIFFOUT_B137p DIFFOUT_B154n DIFFOUT_B154p DIFFOUT_B155n DIFFOUT_B155p DIFFOUT_B156n DIFFOUT_B156p DIFFOUT_B157n DIFFOUT_B157p DIFFOUT_B158n DIFFOUT_B158p DIFFOUT_B159n DIFFOUT_B159p DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ4_4B_2 DQ4_4B_1 DQ4_4B_0 DQ11B DQ11B DQ11B DQ5B DQ5B DQ5B DQ11B DQSn11B/QK11B DQS11B/CQ11B/CQn11B/QKn11B DQ5B DQ5B DQ5B DQ11B DQ11B DQ11B DQ5B DQ5B DQ5B DIFFIO_RX_B160n DIFFIO_RX_B160p DIFFIO_TX_B161n DIFFIO_TX_B161p DIFFIO_RX_B162n DIFFIO_RX_B162p DIFFIO_TX_B163n DIFFIO_TX_B163p DIFFIO_RX_B164n DIFFIO_RX_B164p DIFFIO_TX_B165n DIFFIO_TX_B165p DIFFIO_RX_B166n DIFFIO_RX_B166p DIFFIO_TX_B167n DIFFIO_TX_B167p DIFFIO_RX_B168n DIFFIO_RX_B168p DIFFOUT_B160n DIFFOUT_B160p DIFFOUT_B161n DIFFOUT_B161p DIFFOUT_B162n DIFFOUT_B162p DIFFOUT_B163n DIFFOUT_B163p DIFFOUT_B164n DIFFOUT_B164p DIFFOUT_B165n DIFFOUT_B165p DIFFOUT_B166n DIFFOUT_B166p DIFFOUT_B167n DIFFOUT_B167p DIFFOUT_B168n DIFFOUT_B168p Y13 AG11 AH11 AD11 AE11 AA12 AB11 AA11 AA10 AK11 AK10 AF10 AG10 AB10 AB9 AC10 AD10 AH9 AJ10 AE9 AF9 AJ9 AK8 AC9 AD9 AA9 AB8 AG8 AH8 AJ7 AK7 AD8 AE8 AG7 AH7 AF7 AG6 AJ6 AK6 AA8 AB7 AK5 AK4 AD7 AE7 AA6 AB6 AC6 AC7 AE6 AF6 AG5 AH5 AH4 AJ4 AD6 AE5 AJ3 AK3 AG4 AG3 AJ1 AK2 AE4 AF4 AH2 AH1 AF1 AF2 AG2 W9 W8 AD2 AD1 AC3 AC4 AB2 AB1 AA3 AA4 Y2 Y1 W3 W4 U9 U8 V2 V1 U3 U4 T2 T1 DDR3/DDR2 hard memory PHY (3) DQ2_4C_2 DQ2_4C_1 DQ2_4C_0 DQ11B DQ11B DQ11B DQ5B DQ5B DQ5B DQ12B DQ12B DQ12B DQ5B DQ5B DQ5B DQ12B DQSn12B/QK12B DQS12B/CQ12B/CQn12B/QKn12B DQ5B DQSn5B/QK5B DQS5B/CQ5B/CQn5B/QKn5B DQ12B DQ12B DQ12B DQ5B DQ5B DQ5B DQ12B DQ12B DQ12B DQ5B DQ5B DQ5B VREFB4BN0 DATA10 DATA11 DATA5 DATA6 DATA12 DATA13 DATA7 DATA8 DATA14 DATA15 DATA9 CLKUSR VREFB4AN0 CLK11n CLK11p FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB0 FPLL_BR_CLKOUT3,FPLL_BR_FBn FPLL_BR_CLKOUT2,FPLL_BR_FBp,FPLL_BR_FB1 CLK10n CLK10p CLK9n CLK9p RZQ_1 CLK8n CLK8p Pin List GF31 Page 3 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 GXB_TX_R7p GXB_TX_R7n GXB_RX_R8n,GXB_REFCLK_R8n GXB_RX_R8p,GXB_REFCLK_R8p GXB_TX_R8p GXB_TX_R8n GXB_RX_R9n,GXB_REFCLK_R9n GXB_RX_R9p,GXB_REFCLK_R9p GXB_TX_R9p GXB_TX_R9n GXB_RX_R10n,GXB_REFCLK_R10n GXB_RX_R10p,GXB_REFCLK_R10p GXB_TX_R10p GXB_TX_R10n GXB_RX_R11n,GXB_REFCLK_R11n GXB_RX_R11p,GXB_REFCLK_R11p GXB_TX_R11p GXB_TX_R11n REFCLK3Rp REFCLK3Rn DNU GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7C 7C 7C 7C 7C 7C PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function CLK12p CLK12n RZQ_5 CLK13p CLK13n CLK14p CLK14n FPLL_TR_CLKOUT2,FPLL_TR_FBp,FPLL_TR_FB1 FPLL_TR_CLKOUT3,FPLL_TR_FBn FPLL_TR_CLKOUT0,FPLL_TR_CLKOUTp,FPLL_TR_FB0 FPLL_TR_CLKOUT1,FPLL_TR_CLKOUTn CLK15p CLK15n Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_RX_T1p DIFFIO_RX_T1n DIFFIO_TX_T2p DIFFIO_TX_T2n DIFFIO_RX_T3p DIFFIO_RX_T3n DIFFIO_TX_T4p DIFFIO_TX_T4n DIFFIO_RX_T5p DIFFIO_RX_T5n DIFFIO_TX_T6p DIFFIO_TX_T6n DIFFIO_RX_T7p DIFFIO_RX_T7n DIFFIO_TX_T8p DIFFIO_TX_T8n DIFFIO_RX_T9p DIFFIO_RX_T9n DIFFOUT_T1p DIFFOUT_T1n DIFFOUT_T2p DIFFOUT_T2n DIFFOUT_T3p DIFFOUT_T3n DIFFOUT_T4p DIFFOUT_T4n DIFFOUT_T5p DIFFOUT_T5n DIFFOUT_T6p DIFFOUT_T6n DIFFOUT_T7p DIFFOUT_T7n DIFFOUT_T8p DIFFOUT_T8n DIFFOUT_T9p DIFFOUT_T9n DIFFIO_RX_T10p DIFFIO_RX_T10n DIFFIO_TX_T11p DIFFIO_TX_T11n DIFFIO_RX_T12p DIFFIO_RX_T12n DIFFIO_TX_T13p DIFFIO_TX_T13n DIFFIO_RX_T14p DIFFIO_RX_T14n DIFFIO_TX_T15p DIFFIO_TX_T15n DIFFIO_RX_T32p DIFFIO_RX_T32n DIFFOUT_T10p DIFFOUT_T10n DIFFOUT_T11p DIFFOUT_T11n DIFFOUT_T12p DIFFOUT_T12n DIFFOUT_T13p DIFFOUT_T13n DIFFOUT_T14p DIFFOUT_T14n DIFFOUT_T15p DIFFOUT_T15n DIFFOUT_T32p DIFFOUT_T32n DIFFIO_RX_T33p DIFFIO_RX_T33n DIFFIO_TX_T34p DIFFIO_TX_T34n DIFFIO_RX_T35p DIFFIO_RX_T35n DIFFIO_TX_T36p DIFFIO_TX_T36n DIFFIO_RX_T37p DIFFIO_RX_T37n DIFFIO_TX_T38p DIFFIO_TX_T38n DIFFIO_RX_T39p DIFFIO_RX_T39n DIFFIO_TX_T40p DIFFIO_TX_T40n DIFFIO_RX_T41p DIFFIO_RX_T41n DIFFIO_TX_T42p DIFFIO_TX_T42n DIFFIO_RX_T43p DIFFIO_RX_T43n DIFFIO_TX_T44p DIFFIO_TX_T44n DIFFIO_RX_T45p DIFFIO_RX_T45n DIFFIO_TX_T46p DIFFIO_TX_T46n DIFFIO_RX_T47p DIFFIO_RX_T47n DIFFIO_TX_T48p DIFFIO_TX_T48n DIFFIO_RX_T49p DIFFIO_RX_T49n DIFFOUT_T33p DIFFOUT_T33n DIFFOUT_T34p DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T35n DIFFOUT_T36p DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T37n DIFFOUT_T38p DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T39n DIFFOUT_T40p DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T41n DIFFOUT_T42p DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T43n DIFFOUT_T44p DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T45n DIFFOUT_T46p DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T47n DIFFOUT_T48p DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T49n VREFB7AN0 DEV_OE DEV_CLRn nPERSTL0 CvP_CONFDONE CRC_ERROR PR_DONE PR_REQUEST INIT_DONE nCEO PR_ERROR PR_READY VREFB7BN0 Pin List GF31 F896 R3 R4 P2 P1 N3 N4 M2 M1 L3 L4 K2 K1 J3 J4 H2 H1 G3 G4 R9 R8 H5 F5 E1 F1 E4 E3 D2 D1 D4 D3 A2 B1 C2 C1 A3 B3 B4 C4 C5 D5 J6 K6 A5 A4 J7 K7 D6 E6 G6 H6 A6 B6 G7 H7 F8 G8 J8 K8 E7 F7 G9 H9 A7 A8 B7 C7 C8 D8 J9 K9 D9 E9 B10 B9 A11 A10 J10 K10 C10 D10 E10 F10 C11 D11 G10 H10 J11 K11 F11 G11 B13 B12 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T/CQ1T/CQn1T/QKn1T DQSn1T/QK1T DQ1T DQS1T/CQ1T/CQn1T/QKn1T DQSn1T/QK1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQS2T/CQ2T/CQn2T/QKn2T DQSn2T/QK2T DQ2T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ4_7B_0 DQ4_7B_1 DQ4_7B_2 DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ4_7B_3 DQ4_7B_4 DQ4_7B_5 DQS3T/CQ3T/CQn3T/QKn3T DQSn3T/QK3T DQ3T DQS2T/CQ2T/CQn2T/QKn2T DQSn2T/QK2T DQ2T DQ1T DQ1T DQ1T DQS4_7B DQS#4_7B DM4_7B DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ4_7B_6 DQ4_7B_7 DQ4_7B_8 DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ3_7B_0 DQ3_7B_1 DQ3_7B_2 DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ3_7B_3 DQ3_7B_4 DQ3_7B_5 DQS4T/CQ4T/CQn4T/QKn4T DQSn4T/QK4T DQ4T DQ2T DQ2T DQ2T DQS1T/CQ1T/CQn1T/QKn1T DQS3_7B DQSn1T/QK1T DQS#3_7B DQ1T DM3_7B DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ3_7B_6 DQ3_7B_7 DQ3_7B_8 DQ5T DQ5T DQ5T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ2_7C_0 DQ2_7C_1 DQ2_7C_2 DQ5T DQ5T DQ3T DQ3T DQ1T DQ1T DQ2_7C_3 DQ2_7C_4 Page 4 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCA_FPLL VCCD_FPLL DNU IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DIFFIO_TX_T50p DIFFIO_TX_T50n DIFFIO_RX_T51p DIFFIO_RX_T51n DIFFIO_TX_T52p DIFFIO_TX_T52n DIFFIO_RX_T53p DIFFIO_RX_T53n DIFFIO_TX_T54p DIFFIO_TX_T54n DIFFIO_RX_T55p DIFFIO_RX_T55n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T55n DQ5T DQ3T DQ1T DQS5T/CQ5T/CQn5T/QKn5T DQSn5T/QK5T DQ5T DQS3T/CQ3T/CQn3T/QKn3T DQSn3T/QK3T DQ3T DQ1T DQ1T DQ1T DQS2_7C DQS#2_7C DM2_7C DQ5T DQ5T DQ5T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ2_7C_6 DQ2_7C_7 DQ2_7C_8 DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1_7C_0 DQ1_7C_1 DQ1_7C_2 DIFFIO_RX_T56p DIFFIO_RX_T56n DIFFIO_TX_T57p DIFFIO_TX_T57n DIFFIO_RX_T58p DIFFIO_RX_T58n DIFFIO_TX_T59p DIFFIO_TX_T59n DIFFIO_RX_T60p DIFFIO_RX_T60n DIFFIO_TX_T61p DIFFIO_TX_T61n DIFFIO_RX_T62p DIFFIO_RX_T62n DIFFIO_TX_T63p DIFFIO_TX_T63n DIFFIO_RX_T64p DIFFIO_RX_T64n DIFFIO_TX_T65p DIFFIO_TX_T65n DIFFIO_RX_T66p DIFFIO_RX_T66n DIFFIO_TX_T67p DIFFIO_TX_T67n DIFFIO_RX_T68p DIFFIO_RX_T68n DIFFIO_TX_T69p DIFFIO_TX_T69n DIFFIO_RX_T70p DIFFIO_RX_T70n DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n DIFFOUT_T65p DIFFOUT_T65n DIFFOUT_T66p DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T67n DIFFOUT_T68p DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T69n DIFFOUT_T70p DIFFOUT_T70n DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1_7C_3 DQ1_7C_4 DQ1_7C_5 DQS6T/CQ6T/CQn6T/QKn6T DQSn6T/QK6T DQ6T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQS1_7C DQS#1_7C DM1_7C DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ7T DQ7T DQ7T DQ4T DQ4T DQ4T DQ7T DQ7T DQ7T DQ4T DQ4T DQ4T DQS7T/CQ7T/CQn7T/QKn7T DQSn7T/QK7T DQ7T DQS4T/CQ4T/CQn4T/QKn4T DQSn4T/QK4T DQ4T DQ7T DQ7T DQ7T DQ4T DQ4T DQ4T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQ1_7C_6 DQ1_7C_7 DQ1_7C_8 RESET#_7D CK_7D CK#_7D CKE_7D_0 CKE_7D_1 A_7D_0 A_7D_1 A_7D_2 A_7D_3 A_7D_4 A_7D_5 A_7D_6 A_7D_7 A_7D_8 A_7D_9 A_7D_10 A_7D_11 A_7D_12 A_7D_13 A_7D_14 DIFFIO_RX_T71p DIFFIO_RX_T71n DIFFIO_TX_T72p DIFFIO_TX_T72n DIFFIO_RX_T73p DIFFIO_RX_T73n DIFFIO_TX_T74p DIFFIO_TX_T74n DIFFIO_RX_T75p DIFFIO_RX_T75n DIFFIO_TX_T76p DIFFIO_TX_T76n DIFFOUT_T71p DIFFOUT_T71n DIFFOUT_T72p DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T73n DIFFOUT_T74p DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T75n DIFFOUT_T76p DIFFOUT_T76n DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQS8T/CQ8T/CQn8T/QKn8T DQSn8T/QK8T DQ8T DQ4T DQ4T DQ4T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DIFFIO_RX_T85p DIFFIO_RX_T85n DIFFIO_TX_T86p DIFFIO_TX_T86n DIFFIO_RX_T87p DIFFIO_RX_T87n DIFFIO_TX_T88p DIFFIO_TX_T88n DIFFIO_RX_T89p DIFFIO_RX_T89n DIFFIO_TX_T90p DIFFIO_TX_T90n DIFFIO_RX_T91p DIFFIO_RX_T91n DIFFIO_TX_T92p DIFFIO_TX_T92n DIFFIO_RX_T93p DIFFIO_RX_T93n DIFFOUT_T85p DIFFOUT_T85n DIFFOUT_T86p DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T87n DIFFOUT_T88p DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T89n DIFFOUT_T90p DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T91n DIFFOUT_T92p DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T93n DQ9T DQ9T DQ9T DQ5T DQ5T DQ5T DQ9T DQ9T DQ9T DQ5T DQ5T DQ5T DQS9T/CQ9T/CQn9T/QKn9T DQSn9T/QK9T DQ9T DQS5T/CQ5T/CQn5T/QKn5T DQSn5T/QK5T DQ5T DQ9T DQ9T DQ9T DQ5T DQ5T DQ5T DQ10T DQ10T DQ10T DQ5T DQ5T DQ5T DIFFIO_RX_T94p DIFFIO_RX_T94n DIFFIO_TX_T95p DIFFIO_TX_T95n DIFFIO_RX_T96p DIFFIO_RX_T96n DIFFIO_TX_T97p DIFFIO_TX_T97n DIFFIO_RX_T98p DIFFIO_RX_T98n DIFFIO_TX_T99p DIFFOUT_T94p DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T95n DIFFOUT_T96p DIFFOUT_T96n DIFFOUT_T97p DIFFOUT_T97n DIFFOUT_T98p DIFFOUT_T98n DIFFOUT_T99p D12 E12 J12 K12 G12 H12 C13 D13 E13 F13 J14 K14 J13 K13 A14 A13 F14 G14 C14 D14 G13 H13 A15 B15 D15 E15 F15 G15 J16 K16 H15 J15 D16 E16 B16 C16 G16 H16 A17 A16 C17 D17 J17 K17 J18 K18 D18 E18 F17 G17 B18 C19 G18 H18 A19 B19 D19 E19 M16 M15 K15 F19 G20 J19 K19 J20 K20 F20 F21 C20 D20 G19 H19 A21 B21 D21 E21 D22 E22 J21 K21 J22 K22 G22 H22 B22 C22 G21 H21 F23 G23 C23 DDR3/DDR2 hard memory PHY (3) DQ2_7C_5 DQ10T DQ10T DQ10T DQ5T DQ5T DQ5T DQS10T/CQ10T/CQn10T/QKn10T DQSn10T/QK10T DQ10T DQ5T DQ5T DQ5T DQ10T DQ10T DQ10T DQ5T DQ5T DQ5T VREFB7CN0 VREFB7DN0 CLK19p CLK19n CLK18p CLK18n FPLL_TC_CLKOUT2,FPLL_TC_FBp,FPLL_TC_FB1 FPLL_TC_CLKOUT3,FPLL_TC_FBn FPLL_TC_CLKOUT0,FPLL_TC_CLKOUTp,FPLL_TC_FB0 FPLL_TC_CLKOUT1,FPLL_TC_CLKOUTn CLK17p CLK17n CLK16p CLK16n VREFB8DN0 Pin List GF31 BA_7D_0 BA_7D_1 BA_7D_2 RAS#_7D CAS#_7D WE#_7D ODT_7D_0 ODT_7D_1 A_7D_15 CS#_7D_0 CS#_7D_1 Page 5 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 8D 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREFB8DN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 CONF_DONE nSTATUS nCE nCONFIG GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function CLK23p CLK23n CLK22p CLK22n VREFB8AN0 FPLL_TL_CLKOUT2,FPLL_TL_FBp,FPLL_TL_FB1 FPLL_TL_CLKOUT3,FPLL_TL_FBn FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB0 FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn CLK21p CLK21n CLK20p CLK20n RZQ_6 Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DIFFIO_TX_T99n DIFFIO_RX_T154p DIFFIO_RX_T154n DIFFIO_TX_T155p DIFFIO_TX_T155n DIFFIO_RX_T156p DIFFIO_RX_T156n DIFFIO_TX_T157p DIFFIO_TX_T157n DIFFIO_RX_T158p DIFFIO_RX_T158n DIFFIO_TX_T159p DIFFIO_TX_T159n DIFFIO_RX_T160p DIFFIO_RX_T160n DIFFIO_TX_T161p DIFFIO_TX_T161n DIFFIO_RX_T162p DIFFIO_RX_T162n DIFFOUT_T99n DIFFOUT_T154p DIFFOUT_T154n DIFFOUT_T155p DIFFOUT_T155n DIFFOUT_T156p DIFFOUT_T156n DIFFOUT_T157p DIFFOUT_T157n DIFFOUT_T158p DIFFOUT_T158n DIFFOUT_T159p DIFFOUT_T159n DIFFOUT_T160p DIFFOUT_T160n DIFFOUT_T161p DIFFOUT_T161n DIFFOUT_T162p DIFFOUT_T162n DIFFIO_RX_T163p DIFFIO_RX_T163n DIFFIO_TX_T164p DIFFIO_TX_T164n DIFFIO_RX_T165p DIFFIO_RX_T165n DIFFIO_TX_T166p DIFFIO_TX_T166n DIFFIO_RX_T167p DIFFIO_RX_T167n DIFFIO_TX_T168p DIFFIO_TX_T168n DIFFOUT_T163p DIFFOUT_T163n DIFFOUT_T164p DIFFOUT_T164n DIFFOUT_T165p DIFFOUT_T165n DIFFOUT_T166p DIFFOUT_T166n DIFFOUT_T167p DIFFOUT_T167n DIFFOUT_T168p DIFFOUT_T168n D23 A23 A24 L22 K23 D24 E24 B24 B25 A26 A27 K24 J23 C25 D25 J25 K25 D26 E25 G24 H25 C27 C26 A28 B27 A29 B28 H24 J24 C28 D27 F25 G25 C30 D30 C29 D29 F26 B30 D28 E28 E27 H26 AA26 AA29 AA30 AB27 AB28 AC26 AC29 AC30 AD27 AD28 AE28 AE29 AE30 E30 F27 F28 G26 G29 G30 H27 H28 J26 J29 J30 K27 K28 L25 L26 L29 L30 M24 M27 M28 N23 N24 N26 N29 N30 P23 P25 P27 P28 R24 R29 R30 T23 T27 T28 U24 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 CONF_DONE nSTATUS nCE nCONFIG Pin List GF31 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ11T DQ11T DQ11T DQ11T DQ11T DQ11T DQS11T/CQ11T/CQn11T/QKn11T DQSn11T/QK11T DQ11T DQ11T DQ11T DQ11T DQ12T DQ12T DQ12T DQ12T DQ12T DQ12T DQS12T/CQ12T/CQn12T/QKn12T DQSn12T/QK12T DQ12T DQ12T DQ12T DQ12T Page 6 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F896 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) U26 U29 U30 V23 V25 V27 V28 W24 W29 W30 Y22 Y23 Y24 Y25 Y26 Y27 Y28 AA1 AA2 AA5 AB3 AB4 AC1 AC2 AC5 AD3 AD4 AE1 AE2 AE3 AG1 F3 F4 G1 G2 G5 H3 H4 J1 J2 J5 K3 K4 L1 L2 L5 L6 M3 M4 M7 N1 N2 N5 N8 N9 P3 P4 P6 P8 R1 R2 R5 R7 T3 T4 T8 U1 U2 U5 U7 V3 V4 V6 V8 W1 W2 W7 Y3 Y4 Y5 Y6 Y7 Y8 Y9 L11 L15 L19 L20 L9 W11 W13 W17 Pin List GF31 Page 7 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCP VCCP VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCBAT VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCA_GXBL0 VCCA_GXBR0 VCCA_GXBL1 VCCA_GXBR1 VCCH_GXBL0 VCCH_GXBR0 VCCH_GXBL1 VCCH_GXBR1 VCCL_GXBL0 VCCL_GXBL0 VCCL_GXBR0 VCCL_GXBL1 VCCL_GXBR1 VCCL_GXBR1 VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCT_GXBL0 VCCT_GXBL0 VCCT_GXBR0 VCCT_GXBL1 VCCT_GXBR1 VCCT_GXBR1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3D VCCIO3D VCCIO3D VCCIO3D PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F896 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) W19 W21 T22 T9 P22 P9 K26 M12 M18 W12 W18 V22 V9 N22 M8 V24 V7 P24 P7 T24 T7 N25 N7 T25 T26 U6 M25 M6 N6 M26 R25 R26 W25 W26 M5 T5 T6 W5 W6 U25 V26 V5 P26 P5 R6 M10 M14 M20 N11 N13 N15 N17 N19 N21 P10 P12 P14 P16 P18 P20 R11 R13 R15 R17 R19 R21 T10 T12 T14 T18 T20 U11 U13 U15 U17 U19 U21 V10 V12 V14 V16 V18 V20 T16 AD26 AE24 AH24 AH27 AE19 AE21 AH21 AK23 Pin List GF31 Page 8 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4C VCCIO4C VCCIO4C VCCIO4C VCCIO4D VCCIO4D VCCIO4D VCCIO4D VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7B VCCIO7B VCCIO7B VCCIO7B VCCIO7C VCCIO7C VCCIO7C VCCIO7C VCCIO7D VCCIO7D VCCIO7D VCCIO7D VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8D VCCIO8D VCCIO8D VCCIO8D VCCPD3 VCCPD3 VCCPD4A VCCPD4BCD VCCPD4BCD VCCPD4BCD VCCPD7A VCCPD7BCD VCCPD7BCD VCCPD7BCD VCCPD8 VCCPD8 VCCPGM VCCPGM GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F896 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) AB5 AD5 AH3 AH6 AE10 AG9 AH10 AK9 AE12 AG13 AK13 AK15 AE16 AG18 AH16 AK18 C3 C6 F2 F6 A9 C9 D7 F9 A12 C12 C15 F12 A18 C18 F16 F18 A25 C24 F24 L23 A20 A22 C21 F22 AA23 Y21 AA7 Y10 Y15 Y18 L8 L13 L17 M9 M22 M23 K5 AA24 AC11 AC14 AC17 AC20 AC23 AC8 AF11 AF14 AF17 AF20 AF23 AF26 AF3 AF5 AF8 AH29 AJ11 AJ14 AJ17 AJ2 AJ20 AJ23 AJ26 AJ5 AJ8 B11 B14 B17 B2 B20 B23 B26 B29 B5 B8 E11 E14 E17 Pin List GF31 Page 9 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Emulated LVDS Output Channel F896 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) E2 E20 E23 E26 E5 E8 H11 H14 H17 H20 H23 H8 L10 L12 L14 L16 L18 L21 L24 L7 M11 M13 M17 M19 M21 N10 N12 N14 N16 N18 N20 P11 P13 P15 P17 P19 P21 R10 R12 R14 R18 R20 T11 T13 T15 T17 T19 T21 U10 U12 U14 U16 U18 U20 V11 V13 V15 V17 V19 V21 W10 W14 W20 Y11 Y14 Y17 Y19 R16 Notes: (1) For more information about pin definitions and pin connection guidelines, refer to the Arria V Device Family Pin Connection Guidelines. (2) GXB_REFCLK pin is not supported in current Quartus II version, but will be supported in future Quartus II release version. (3) RESET pin is only applicable for DDR3 device. PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Pin List GF31 Page 10 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 DNU DNU RREF_TL GND GND DNU DNU GND GND DNU DNU GND GND DNU DNU GND GND GXB_TX_L8n GXB_TX_L8p GXB_RX_L8p,GXB_REFCLK_L8p GXB_RX_L8n,GXB_REFCLK_L8n GXB_TX_L7n GXB_TX_L7p GXB_RX_L7p,GXB_REFCLK_L7p GXB_RX_L7n,GXB_REFCLK_L7n GXB_TX_L6n GXB_TX_L6p GXB_RX_L6p,GXB_REFCLK_L6p GXB_RX_L6n,GXB_REFCLK_L6n REFCLK2Ln REFCLK2Lp REFCLK1Ln REFCLK1Lp GXB_TX_L5n GXB_TX_L5p GXB_RX_L5p,GXB_REFCLK_L5p GXB_RX_L5n,GXB_REFCLK_L5n GXB_TX_L4n GXB_TX_L4p GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_TX_L3n GXB_TX_L3p GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_TX_L2n GXB_TX_L2p GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n GXB_TX_L1n GXB_TX_L1p GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_TX_L0n GXB_TX_L0p GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n REFCLK0Ln REFCLK0Lp DNU TDO TMS TCK TDI DCLK nCSO AS_DATA3 AS_DATA2 AS_DATA1 AS_DATA0,ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel TDO TMS TCK TDI DCLK DATA4 DATA3 DATA2 DATA1 DATA0 RZQ_0 CLK0n CLK0p CLK1n CLK1p FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB0 FPLL_BL_CLKOUT3,FPLL_BL_FBn FPLL_BL_CLKOUT2,FPLL_BL_FBp,FPLL_BL_FB1 VREFB3AN0 CLK2n CLK2p CLK3n CLK3p DIFFIO_TX_B1n DIFFIO_TX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_TX_B3n DIFFIO_TX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_TX_B5n DIFFIO_TX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_TX_B8n DIFFIO_TX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_TX_B10n DIFFIO_TX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_TX_B12n DIFFIO_TX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p DIFFIO_TX_B14n DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n Pin List GF35 F1152 E33 F33 F34 R27 R26 G31 G32 H34 H33 J31 J32 K34 K33 L31 L32 M34 M33 N31 N32 P34 P33 R31 R32 T34 T33 U31 U32 V34 V33 U27 U26 W27 W26 W31 W32 Y34 Y33 AA31 AA32 AB34 AB33 AC31 AC32 AD34 AD33 AE31 AE32 AF34 AF33 AG31 AG32 AH34 AH33 AJ31 AJ32 AK34 AK33 AA28 AA27 AL32 AC28 AF30 AN32 AC29 AM32 AM34 AM33 AP33 AN33 AN34 AL31 AM31 AP31 AP32 AD27 AD26 AJ29 AK29 AL30 AM30 AN30 AP30 AE27 AF28 AH28 AJ28 AL29 AM29 AN29 AP29 AE29 AF29 AG27 AH27 AL28 AM28 AP27 AP28 AG29 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ1B DQ1B DQ1B DQ1B DQSn1B/QK1B DQS1B/CQ1B/CQn1B/QKn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ2B DQSn2B/QK2B DQS2B/CQ2B/CQn2B/QKn2B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B Page 11 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DQS for X8/X9 DQS for X16/ X18 DIFFIO_TX_B14p DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_TX_B16n DIFFIO_TX_B16p DIFFIO_RX_B17n DIFFIO_RX_B17p DIFFIO_TX_B18n DIFFIO_TX_B18p DIFFIO_RX_B19n DIFFIO_RX_B19p DIFFIO_TX_B20n DIFFIO_TX_B20p DIFFIO_RX_B21n DIFFIO_RX_B21p DIFFIO_TX_B22n DIFFIO_TX_B22p DIFFIO_RX_B23n DIFFIO_RX_B23p DIFFIO_TX_B24n DIFFIO_TX_B24p DIFFIO_RX_B25n DIFFIO_RX_B25p DIFFIO_TX_B26n DIFFIO_TX_B26p DIFFIO_RX_B27n DIFFIO_RX_B27p DIFFIO_TX_B28n DIFFIO_TX_B28p DIFFIO_RX_B29n DIFFIO_RX_B29p DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ3B DQSn3B/QK3B DQS3B/CQ3B/CQn3B/QKn3B DQ1B DQSn1B/QK1B DQS1B/CQ1B/CQn1B/QKn1B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ4B DQSn4B/QK4B DQS4B/CQ4B/CQn4B/QKn4B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DIFFIO_RX_B30n DIFFIO_RX_B30p DIFFIO_TX_B31n DIFFIO_TX_B31p DIFFIO_RX_B32n DIFFIO_RX_B32p DIFFIO_TX_B33n DIFFIO_TX_B33p DIFFIO_RX_B34n DIFFIO_RX_B34p DIFFIO_TX_B35n DIFFIO_TX_B35p DIFFIO_RX_B36n DIFFIO_RX_B36p DIFFIO_TX_B37n DIFFIO_TX_B37p DIFFIO_RX_B38n DIFFIO_RX_B38p DIFFIO_TX_B39n DIFFIO_TX_B39p DIFFIO_RX_B40n DIFFIO_RX_B40p DIFFIO_TX_B41n DIFFIO_TX_B41p DIFFIO_RX_B42n DIFFIO_RX_B42p DIFFIO_TX_B43n DIFFIO_TX_B43p DIFFIO_RX_B44n DIFFIO_RX_B44p DIFFIO_TX_B45n DIFFIO_TX_B45p DIFFIO_RX_B46n DIFFIO_RX_B46p DIFFIO_TX_B47n DIFFIO_TX_B47p DIFFIO_RX_B48n DIFFIO_RX_B48p DIFFIO_TX_B49n DIFFIO_TX_B49p DIFFIO_RX_B50n DIFFIO_RX_B50p DIFFIO_TX_B51n DIFFIO_TX_B51p DIFFIO_RX_B52n DIFFIO_RX_B52p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33n DIFFOUT_B33p DIFFOUT_B34n DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B35p DIFFOUT_B36n DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B37p DIFFOUT_B38n DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B39p DIFFOUT_B40n DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B41p DIFFOUT_B42n DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B43p DIFFOUT_B44n DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B45p DIFFOUT_B46n DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B47p DIFFOUT_B48n DIFFOUT_B48p DIFFOUT_B49n DIFFOUT_B49p DIFFOUT_B50n DIFFOUT_B50p DIFFOUT_B51n DIFFOUT_B51p DIFFOUT_B52n DIFFOUT_B52p DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ5B DQSn5B/QK5B DQS5B/CQ5B/CQn5B/QKn5B DQ2B DQSn2B/QK2B DQS2B/CQ2B/CQn2B/QKn2B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ6B DQ6B DQ6B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ6B DQSn6B/QK6B DQS6B/CQ6B/CQn6B/QKn6B DQ3B DQ3B DQ3B DQ1B DQSn1B/QK1B DQS1B/CQ1B/CQn1B/QKn1B DQ6B DQ6B DQ6B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ6B DQ6B DQ6B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ7B DQSn7B/QK7B DQS7B/CQ7B/CQn7B/QKn7B DQ3B DQSn3B/QK3B DQS3B/CQ3B/CQn3B/QKn3B DQ1B DQ1B DQ1B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DIFFIO_RX_B53n DIFFIO_RX_B53p DIFFIO_TX_B70n DIFFIO_TX_B70p DIFFIO_RX_B71n DIFFIO_RX_B71p DIFFIO_TX_B72n DIFFIO_TX_B72p DIFFIO_RX_B73n DIFFIO_RX_B73p DIFFIO_TX_B74n DIFFIO_TX_B74p DIFFIO_RX_B75n DIFFIO_RX_B75p DIFFOUT_B53n DIFFOUT_B53p DIFFOUT_B70n DIFFOUT_B70p DIFFOUT_B71n DIFFOUT_B71p DIFFOUT_B72n DIFFOUT_B72p DIFFOUT_B73n DIFFOUT_B73p DIFFOUT_B74n DIFFOUT_B74p DIFFOUT_B75n DIFFOUT_B75p DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ8B DQ8B DQ8B DQ4B DQ4B DQ4B DQ8B DQSn8B/QK8B DQS8B/CQ8B/CQn8B/QKn8B DQ4B DQ4B DQ4B DQ8B DQ8B DQ8B DQ4B DQ4B DQ4B DIFFIO_RX_B76n DIFFIO_RX_B76p DIFFOUT_B76n DIFFOUT_B76p AH29 AK27 AL27 AG26 AH26 AJ26 AK26 AD29 AE28 AL26 AM26 AN27 AN26 AP25 AP26 AE26 AF26 AL25 AM25 AE23 AE24 AC24 AC25 AA25 AB25 AD24 AE25 AF25 AG24 AH24 AH25 Y23 AB24 AJ25 AK24 AK23 AL24 AF23 AG23 AC23 AD23 AH23 AJ23 AL23 AM23 AN23 AN24 AA23 AB23 AP22 AP23 AE21 AE22 AL21 AL22 AB22 AC22 AH21 AH22 AF22 AG21 AJ22 AK21 AA21 AB21 AM22 AN21 AC21 AD21 AN20 AP20 AA20 AB20 AL20 AM20 AJ20 AK20 AG20 AH20 AC20 AD20 AE20 AF20 AH19 AJ19 AL19 AM19 AB19 AC19 AN18 AP19 AE19 AF19 AK18 AL18 AB18 AA18 AG18 AH18 DQ8B DQ8B DQ8B DQ4B DQ4B DQ4B VREFB3BN0 VREFB3CN0 VREFB3DN0 CLK4n CLK4p Pin List GF35 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) Page 12 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCD_FPLL VCCA_FPLL DNU IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) CLK5n CLK5p FPLL_BC_CLKOUT1,FPLL_BC_CLKOUTn FPLL_BC_CLKOUT0,FPLL_BC_CLKOUTp,FPLL_BC_FB0 FPLL_BC_CLKOUT3,FPLL_BC_FBn FPLL_BC_CLKOUT2,FPLL_BC_FBp,FPLL_BC_FB1 CLK6n CLK6p CLK7n CLK7p Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DIFFIO_TX_B77n DIFFIO_TX_B77p DIFFIO_RX_B78n DIFFIO_RX_B78p DIFFIO_TX_B79n DIFFIO_TX_B79p DIFFIO_RX_B80n DIFFIO_RX_B80p DIFFIO_TX_B81n DIFFIO_TX_B81p DIFFIO_RX_B82n DIFFIO_RX_B82p DIFFIO_TX_B83n DIFFIO_TX_B83p DIFFIO_RX_B84n DIFFIO_RX_B84p DIFFOUT_B77n DIFFOUT_B77p DIFFOUT_B78n DIFFOUT_B78p DIFFOUT_B79n DIFFOUT_B79p DIFFOUT_B80n DIFFOUT_B80p DIFFOUT_B81n DIFFOUT_B81p DIFFOUT_B82n DIFFOUT_B82p DIFFOUT_B83n DIFFOUT_B83p DIFFOUT_B84n DIFFOUT_B84p DIFFIO_TX_B93n DIFFIO_TX_B93p DIFFIO_RX_B94n DIFFIO_RX_B94p DIFFIO_TX_B95n DIFFIO_TX_B95p DIFFIO_RX_B96n DIFFIO_RX_B96p DIFFIO_TX_B97n DIFFIO_TX_B97p DIFFIO_RX_B98n DIFFIO_RX_B98p DIFFOUT_B93n DIFFOUT_B93p DIFFOUT_B94n DIFFOUT_B94p DIFFOUT_B95n DIFFOUT_B95p DIFFOUT_B96n DIFFOUT_B96p DIFFOUT_B97n DIFFOUT_B97p DIFFOUT_B98n DIFFOUT_B98p DIFFIO_RX_B99n DIFFIO_RX_B99p DIFFIO_TX_B100n DIFFIO_TX_B100p DIFFIO_RX_B101n DIFFIO_RX_B101p DIFFIO_TX_B102n DIFFIO_TX_B102p DIFFIO_RX_B103n DIFFIO_RX_B103p DIFFIO_TX_B104n DIFFIO_TX_B104p DIFFIO_RX_B105n DIFFIO_RX_B105p DIFFIO_TX_B106n DIFFIO_TX_B106p DIFFIO_RX_B107n DIFFIO_RX_B107p DIFFIO_TX_B108n DIFFIO_TX_B108p DIFFIO_RX_B109n DIFFIO_RX_B109p DIFFIO_TX_B110n DIFFIO_TX_B110p DIFFIO_RX_B111n DIFFIO_RX_B111p DIFFIO_TX_B112n DIFFIO_TX_B112p DIFFIO_RX_B113n DIFFIO_RX_B113p DIFFOUT_B99n DIFFOUT_B99p DIFFOUT_B100n DIFFOUT_B100p DIFFOUT_B101n DIFFOUT_B101p DIFFOUT_B102n DIFFOUT_B102p DIFFOUT_B103n DIFFOUT_B103p DIFFOUT_B104n DIFFOUT_B104p DIFFOUT_B105n DIFFOUT_B105p DIFFOUT_B106n DIFFOUT_B106p DIFFOUT_B107n DIFFOUT_B107p DIFFOUT_B108n DIFFOUT_B108p DIFFOUT_B109n DIFFOUT_B109p DIFFOUT_B110n DIFFOUT_B110p DIFFOUT_B111n DIFFOUT_B111p DIFFOUT_B112n DIFFOUT_B112p DIFFOUT_B113n DIFFOUT_B113p DIFFIO_RX_B114n DIFFIO_RX_B114p DIFFIO_TX_B115n DIFFIO_TX_B115p DIFFIO_RX_B116n DIFFIO_RX_B116p DIFFIO_TX_B117n DIFFIO_TX_B117p DIFFIO_RX_B118n DIFFIO_RX_B118p DIFFIO_TX_B119n DIFFIO_TX_B119p DIFFIO_RX_B120n DIFFIO_RX_B120p DIFFIO_TX_B121n DIFFIO_TX_B121p DIFFIO_RX_B122n DIFFIO_RX_B122p DIFFIO_TX_B123n DIFFIO_TX_B123p DIFFIO_RX_B124n DIFFIO_RX_B124p DIFFIO_TX_B125n DIFFIO_TX_B125p DIFFIO_RX_B126n DIFFIO_RX_B126p DIFFIO_TX_B127n DIFFIO_TX_B127p DIFFIO_RX_B128n DIFFIO_RX_B128p DIFFIO_TX_B129n DIFFIO_TX_B129p DIFFIO_RX_B130n DIFFIO_RX_B130p DIFFOUT_B114n DIFFOUT_B114p DIFFOUT_B115n DIFFOUT_B115p DIFFOUT_B116n DIFFOUT_B116p DIFFOUT_B117n DIFFOUT_B117p DIFFOUT_B118n DIFFOUT_B118p DIFFOUT_B119n DIFFOUT_B119p DIFFOUT_B120n DIFFOUT_B120p DIFFOUT_B121n DIFFOUT_B121p DIFFOUT_B122n DIFFOUT_B122p DIFFOUT_B123n DIFFOUT_B123p DIFFOUT_B124n DIFFOUT_B124p DIFFOUT_B125n DIFFOUT_B125p DIFFOUT_B126n DIFFOUT_B126p DIFFOUT_B127n DIFFOUT_B127p DIFFOUT_B128n DIFFOUT_B128p DIFFOUT_B129n DIFFOUT_B129p DIFFOUT_B130n DIFFOUT_B130p AN17 AP17 AG17 AH17 AA17 AB17 AJ17 AK17 AL17 AM17 AE17 AF17 AC17 AC18 AD17 AE18 Y17 Y18 AD18 AP16 AN15 AH16 AJ16 AE16 AF16 Y15 AA15 AB16 AC16 AL16 AM16 AJ14 AK14 AL14 AM14 AA14 AB15 AK15 AL15 AG14 AH14 AG15 AH15 AD15 AE15 AE14 AF14 AB14 AC15 AC14 AD14 AB13 AC13 AN14 AP14 AN12 AP13 AL13 AM13 Y11 AA12 AK12 AL12 AK11 AL11 AH13 AJ13 AB11 AB12 AG12 AH12 AH11 AJ11 AE13 AF13 AC11 AC12 AD12 AE12 AD11 AE11 AF11 AG11 AD9 AE9 AM11 AN11 AL10 AM10 AP10 AP11 AA10 AB10 AH10 AJ10 AK9 AL9 AN9 AN8 VREFB4DN0 VREFB4CN0 Pin List GF35 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ9B DQSn9B/QK9B DQS9B/CQ9B/CQn9B/QKn9B DQ4B DQSn4B/QK4B DQS4B/CQ4B/CQn4B/QKn4B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ10B DQ10B DQ10B DQ5B DQ5B DQ5B DQ10B DQSn10B/QK10B DQS10B/CQ10B/CQn10B/QKn10B DQ5B DQ5B DQ5B DQ10B DQ10B DQ10B DQ5B DQ5B DQ5B DQ10B DQ10B DQ10B DQ5B DQ5B DQ5B DQ11B DQ11B DQ11B DQ5B DQ5B DQ5B DQ11B DQSn11B/QK11B DQS11B/CQ11B/CQn11B/QKn11B DQ5B DQSn5B/QK5B DQS5B/CQ5B/CQn5B/QKn5B DQ11B DQ11B DQ11B DQ5B DQ5B DQ5B DQ11B DQ11B DQ11B DQ5B DQ5B DQ5B DQ12B DQ12B DQ12B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B A_4D_14 A_4D_13 A_4D_12 A_4D_11 A_4D_10 A_4D_9 A_4D_8 A_4D_7 A_4D_6 A_4D_5 A_4D_4 A_4D_3 A_4D_2 A_4D_1 A_4D_0 CKE_4D_1 CKE_4D_0 CK#_4D CK_4D RESET#_4D DQ1_4C_8 DQ1_4C_7 DQ1_4C_6 DQ12B DQSn12B/QK12B DQS12B/CQ12B/CQn12B/QKn12B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DM1_4C DQS#1_4C DQS1_4C DQ12B DQ12B DQ12B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DQ1_4C_5 DQ1_4C_4 DQ1_4C_3 DQ12B DQ12B DQ12B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DQ1_4C_2 DQ1_4C_1 DQ1_4C_0 DQ13B DQ13B DQ13B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DQ2_4C_8 DQ2_4C_7 DQ2_4C_6 DQ13B DQSn13B/QK13B DQS13B/CQ13B/CQn13B/QKn13B DQ6B DQSn6B/QK6B DQS6B/CQ6B/CQn6B/QKn6B DQ2B DQ2B DQ2B DM2_4C DQS#2_4C DQS2_4C DQ13B DQ13B DQ13B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DQ2_4C_5 DQ2_4C_4 DQ2_4C_3 DQ13B DQ13B DQ13B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DQ2_4C_2 DQ2_4C_1 DQ2_4C_0 DQ14B DQ14B DQ14B DQ7B DQ7B DQ7B DQ2B DQ2B DQ2B DQ3_4B_8 DQ3_4B_7 DQ3_4B_6 DQ14B DQSn14B/QK14B DQS14B/CQ14B/CQn14B/QKn14B DQ7B DQ7B DQ7B DQ2B DQSn2B/QK2B DQS2B/CQ2B/CQn2B/QKn2B DM3_4B DQS#3_4B DQS3_4B DQ14B DQ14B DQ14B DQ7B DQ7B DQ7B DQ2B DQ2B DQ2B DQ3_4B_5 DQ3_4B_4 DQ3_4B_3 DQ14B DQ14B DQ14B DQ7B DQ7B DQ7B DQ2B DQ2B DQ2B DQ3_4B_2 DQ3_4B_1 DQ3_4B_0 CS#_4D_1 CS#_4D_0 A_4D_15 ODT_4D_1 ODT_4D_0 WE#_4D CAS#_4D RAS#_4D BA_4D_2 BA_4D_1 BA_4D_0 Page 13 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO RREF_BR DNU DNU REFCLK0Rp REFCLK0Rn GXB_RX_R0n,GXB_REFCLK_R0n GXB_RX_R0p,GXB_REFCLK_R0p GXB_TX_R0p GXB_TX_R0n GXB_RX_R1n,GXB_REFCLK_R1n GXB_RX_R1p,GXB_REFCLK_R1p GXB_TX_R1p GXB_TX_R1n GXB_RX_R2n,GXB_REFCLK_R2n GXB_RX_R2p,GXB_REFCLK_R2p GXB_TX_R2p GXB_TX_R2n GND GND DNU DNU GND GND DNU DNU GND GND DNU DNU GND GND REFCLK2Rp REFCLK2Rn GXB_RX_R6n,GXB_REFCLK_R6n GXB_RX_R6p,GXB_REFCLK_R6p GXB_TX_R6p GXB_TX_R6n GXB_RX_R7n,GXB_REFCLK_R7n GXB_RX_R7p,GXB_REFCLK_R7p GXB_TX_R7p GXB_TX_R7n GXB_RX_R8n,GXB_REFCLK_R8n GXB_RX_R8p,GXB_REFCLK_R8p GXB_TX_R8p GXB_TX_R8n GXB_RX_R9n,GXB_REFCLK_R9n GXB_RX_R9p,GXB_REFCLK_R9p GXB_TX_R9p GXB_TX_R9n GXB_RX_R10n,GXB_REFCLK_R10n GXB_RX_R10p,GXB_REFCLK_R10p GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DIFFIO_TX_B131n DIFFIO_TX_B131p DIFFIO_RX_B132n DIFFIO_RX_B132p DIFFIO_TX_B133n DIFFIO_TX_B133p DIFFIO_RX_B134n DIFFIO_RX_B134p DIFFIO_TX_B135n DIFFIO_TX_B135p DIFFIO_RX_B136n DIFFIO_RX_B136p DIFFOUT_B131n DIFFOUT_B131p DIFFOUT_B132n DIFFOUT_B132p DIFFOUT_B133n DIFFOUT_B133p DIFFOUT_B134n DIFFOUT_B134p DIFFOUT_B135n DIFFOUT_B135p DIFFOUT_B136n DIFFOUT_B136p DIFFIO_RX_B137n DIFFIO_RX_B137p DIFFIO_TX_B154n DIFFIO_TX_B154p DIFFIO_RX_B155n DIFFIO_RX_B155p DIFFIO_TX_B156n DIFFIO_TX_B156p DIFFIO_RX_B157n DIFFIO_RX_B157p DIFFIO_TX_B158n DIFFIO_TX_B158p DIFFIO_RX_B159n DIFFIO_RX_B159p DIFFOUT_B137n DIFFOUT_B137p DIFFOUT_B154n DIFFOUT_B154p DIFFOUT_B155n DIFFOUT_B155p DIFFOUT_B156n DIFFOUT_B156p DIFFOUT_B157n DIFFOUT_B157p DIFFOUT_B158n DIFFOUT_B158p DIFFOUT_B159n DIFFOUT_B159p DIFFIO_RX_B160n DIFFIO_RX_B160p DIFFIO_TX_B161n DIFFIO_TX_B161p DIFFIO_RX_B162n DIFFIO_RX_B162p DIFFIO_TX_B163n DIFFIO_TX_B163p DIFFIO_RX_B164n DIFFIO_RX_B164p DIFFIO_TX_B165n DIFFIO_TX_B165p DIFFIO_RX_B166n DIFFIO_RX_B166p DIFFIO_TX_B167n DIFFIO_TX_B167p DIFFIO_RX_B168n DIFFIO_RX_B168p DIFFOUT_B160n DIFFOUT_B160p DIFFOUT_B161n DIFFOUT_B161p DIFFOUT_B162n DIFFOUT_B162p DIFFOUT_B163n DIFFOUT_B163p DIFFOUT_B164n DIFFOUT_B164p DIFFOUT_B165n DIFFOUT_B165p DIFFOUT_B166n DIFFOUT_B166p DIFFOUT_B167n DIFFOUT_B167p DIFFOUT_B168n DIFFOUT_B168p AC9 AC10 AG9 AH9 AE10 AF10 AL8 AM8 AC8 AD8 AJ8 AK8 AE8 AF8 AG8 AH8 AP8 AP7 AL7 AM7 AM6 AN6 AP6 AP5 AE7 AF7 AM5 AN5 AK6 AL6 AH7 AJ7 AD6 AE6 AP3 AP4 AH6 AJ6 AP2 AN3 AC7 AC6 AL4 AL5 AM3 AM4 AF6 AG6 AM1 AM2 AN2 AA8 AA7 AK2 AK1 AJ3 AJ4 AH2 AH1 AG3 AG4 AF2 AF1 AE3 AE4 AD2 AD1 AC3 AC4 AB2 AB1 AA3 AA4 Y2 Y1 W3 W4 W9 W8 U9 U8 V2 V1 U3 U4 T2 T1 R3 R4 P2 P1 N3 N4 M2 M1 L3 L4 K2 K1 VREFB4BN0 DATA10 DATA11 DATA5 DATA6 DATA12 DATA13 DATA7 DATA8 DATA14 DATA15 DATA9 CLKUSR VREFB4AN0 CLK11n CLK11p FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB0 FPLL_BR_CLKOUT3,FPLL_BR_FBn FPLL_BR_CLKOUT2,FPLL_BR_FBp,FPLL_BR_FB1 CLK10n CLK10p CLK9n CLK9p RZQ_1 CLK8n CLK8p Pin List GF35 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ15B DQ15B DQ15B DQ7B DQ7B DQ7B DQ2B DQ2B DQ2B DQ4_4B_8 DQ4_4B_7 DQ4_4B_6 DQ15B DQSn15B/QK15B DQS15B/CQ15B/CQn15B/QKn15B DQ7B DQSn7B/QK7B DQS7B/CQ7B/CQn7B/QKn7B DQ2B DQ2B DQ2B DM4_4B DQS#4_4B DQS4_4B DQ15B DQ15B DQ15B DQ7B DQ7B DQ7B DQ2B DQ2B DQ2B DQ4_4B_5 DQ4_4B_4 DQ4_4B_3 DQ15B DQ15B DQ15B DQ7B DQ7B DQ7B DQ2B DQ2B DQ2B DQ4_4B_2 DQ4_4B_1 DQ4_4B_0 DQ16B DQ16B DQ16B DQ8B DQ8B DQ8B DQ16B DQSn16B/QK16B DQS16B/CQ16B/CQn16B/QKn16B DQ8B DQ8B DQ8B DQ16B DQ16B DQ16B DQ8B DQ8B DQ8B DQ16B DQ16B DQ16B DQ8B DQ8B DQ8B DQ17B DQ17B DQ17B DQ8B DQ8B DQ8B DQ17B DQSn17B/QK17B DQS17B/CQ17B/CQn17B/QKn17B DQ8B DQSn8B/QK8B DQS8B/CQ8B/CQn8B/QKn8B DQ17B DQ17B DQ17B DQ8B DQ8B DQ8B DQ17B DQ17B DQ17B DQ8B DQ8B DQ8B Page 14 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 GXB_TX_R10p GXB_TX_R10n GXB_RX_R11n,GXB_REFCLK_R11n GXB_RX_R11p,GXB_REFCLK_R11p GXB_TX_R11p GXB_TX_R11n REFCLK3Rp REFCLK3Rn DNU GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function CLK12p CLK12n RZQ_5 CLK13p CLK13n CLK14p CLK14n FPLL_TR_CLKOUT2,FPLL_TR_FBp,FPLL_TR_FB1 FPLL_TR_CLKOUT3,FPLL_TR_FBn FPLL_TR_CLKOUT0,FPLL_TR_CLKOUTp,FPLL_TR_FB0 FPLL_TR_CLKOUT1,FPLL_TR_CLKOUTn CLK15p CLK15n Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_RX_T1p DIFFIO_RX_T1n DIFFIO_TX_T2p DIFFIO_TX_T2n DIFFIO_RX_T3p DIFFIO_RX_T3n DIFFIO_TX_T4p DIFFIO_TX_T4n DIFFIO_RX_T5p DIFFIO_RX_T5n DIFFIO_TX_T6p DIFFIO_TX_T6n DIFFIO_RX_T7p DIFFIO_RX_T7n DIFFIO_TX_T8p DIFFIO_TX_T8n DIFFIO_RX_T9p DIFFIO_RX_T9n DIFFOUT_T1p DIFFOUT_T1n DIFFOUT_T2p DIFFOUT_T2n DIFFOUT_T3p DIFFOUT_T3n DIFFOUT_T4p DIFFOUT_T4n DIFFOUT_T5p DIFFOUT_T5n DIFFOUT_T6p DIFFOUT_T6n DIFFOUT_T7p DIFFOUT_T7n DIFFOUT_T8p DIFFOUT_T8n DIFFOUT_T9p DIFFOUT_T9n DIFFIO_RX_T10p DIFFIO_RX_T10n DIFFIO_TX_T11p DIFFIO_TX_T11n DIFFIO_RX_T12p DIFFIO_RX_T12n DIFFIO_TX_T13p DIFFIO_TX_T13n DIFFIO_RX_T14p DIFFIO_RX_T14n DIFFIO_TX_T15p DIFFIO_TX_T15n DIFFIO_RX_T32p DIFFIO_RX_T32n DIFFOUT_T10p DIFFOUT_T10n DIFFOUT_T11p DIFFOUT_T11n DIFFOUT_T12p DIFFOUT_T12n DIFFOUT_T13p DIFFOUT_T13n DIFFOUT_T14p DIFFOUT_T14n DIFFOUT_T15p DIFFOUT_T15n DIFFOUT_T32p DIFFOUT_T32n DIFFIO_RX_T33p DIFFIO_RX_T33n DIFFIO_TX_T34p DIFFIO_TX_T34n DIFFIO_RX_T35p DIFFIO_RX_T35n DIFFIO_TX_T36p DIFFIO_TX_T36n DIFFIO_RX_T37p DIFFIO_RX_T37n DIFFIO_TX_T38p DIFFIO_TX_T38n DIFFIO_RX_T39p DIFFIO_RX_T39n DIFFIO_TX_T40p DIFFIO_TX_T40n DIFFIO_RX_T41p DIFFIO_RX_T41n DIFFIO_TX_T42p DIFFIO_TX_T42n DIFFIO_RX_T43p DIFFIO_RX_T43n DIFFIO_TX_T44p DIFFIO_TX_T44n DIFFIO_RX_T45p DIFFIO_RX_T45n DIFFIO_TX_T46p DIFFIO_TX_T46n DIFFIO_RX_T47p DIFFIO_RX_T47n DIFFIO_TX_T48p DIFFIO_TX_T48n DIFFIO_RX_T49p DIFFIO_RX_T49n DIFFIO_TX_T50p DIFFIO_TX_T50n DIFFIO_RX_T51p DIFFIO_RX_T51n DIFFIO_TX_T52p DIFFIO_TX_T52n DIFFIO_RX_T53p DIFFIO_RX_T53n DIFFIO_TX_T54p DIFFIO_TX_T54n DIFFIO_RX_T55p DIFFIO_RX_T55n DIFFOUT_T33p DIFFOUT_T33n DIFFOUT_T34p DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T35n DIFFOUT_T36p DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T37n DIFFOUT_T38p DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T39n DIFFOUT_T40p DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T41n DIFFOUT_T42p DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T43n DIFFOUT_T44p DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T45n DIFFOUT_T46p DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T47n DIFFOUT_T48p DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T55n DIFFIO_RX_T56p DIFFIO_RX_T56n DIFFIO_TX_T57p DIFFIO_TX_T57n DIFFIO_RX_T58p DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p VREFB7AN0 DEV_OE DEV_CLRn nPERSTL0 CvP_CONFDONE CRC_ERROR PR_DONE PR_REQUEST INIT_DONE nCEO PR_ERROR PR_READY VREFB7BN0 VREFB7CN0 Pin List GF35 F1152 J3 J4 H2 H1 G3 G4 R9 R8 K5 H5 E3 E4 E1 F1 D1 E2 G6 H6 C1 C2 E5 F6 C3 D3 J6 K6 A3 B3 L6 M7 C6 D5 A2 B2 B5 C4 A5 A4 D6 E6 J7 K7 K9 K8 M10 P11 C8 D7 E8 F7 N10 N11 G8 G7 H8 J8 L9 M8 B6 C7 E9 F8 A7 A6 G9 H9 D8 D9 A8 B8 A10 B9 J10 K10 F10 G10 J11 K11 G11 H11 K12 L11 E11 F11 C10 D10 G12 H12 L12 M12 A11 B11 N13 M13 C11 D11 J13 K13 A13 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T/CQ1T/CQn1T/QKn1T DQSn1T/QK1T DQ1T DQS1T/CQ1T/CQn1T/QKn1T DQSn1T/QK1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQS2T/CQ2T/CQn2T/QKn2T DQSn2T/QK2T DQ2T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ4_7B_0 DQ4_7B_1 DQ4_7B_2 DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ4_7B_3 DQ4_7B_4 DQ4_7B_5 DQS3T/CQ3T/CQn3T/QKn3T DQSn3T/QK3T DQ3T DQS2T/CQ2T/CQn2T/QKn2T DQSn2T/QK2T DQ2T DQ1T DQ1T DQ1T DQS4_7B DQS#4_7B DM4_7B DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ4_7B_6 DQ4_7B_7 DQ4_7B_8 DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ3_7B_0 DQ3_7B_1 DQ3_7B_2 DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ3_7B_3 DQ3_7B_4 DQ3_7B_5 DQS4T/CQ4T/CQn4T/QKn4T DQSn4T/QK4T DQ4T DQ2T DQ2T DQ2T DQS1T/CQ1T/CQn1T/QKn1T DQSn1T/QK1T DQ1T DQS3_7B DQS#3_7B DM3_7B DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ3_7B_6 DQ3_7B_7 DQ3_7B_8 DQ5T DQ5T DQ5T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ2_7C_0 DQ2_7C_1 DQ2_7C_2 DQ5T DQ5T DQ5T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ2_7C_3 DQ2_7C_4 DQ2_7C_5 DQS5T/CQ5T/CQn5T/QKn5T DQSn5T/QK5T DQ5T DQS3T/CQ3T/CQn3T/QKn3T DQSn3T/QK3T DQ3T DQ1T DQ1T DQ1T DQS2_7C DQS#2_7C DM2_7C DQ5T DQ5T DQ5T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ2_7C_6 DQ2_7C_7 DQ2_7C_8 DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1_7C_0 DQ1_7C_1 DQ1_7C_2 DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1_7C_3 DQ1_7C_4 DQ1_7C_5 DQS6T/CQ6T/CQn6T/QKn6T DQ3T DQ1T DQS1_7C Page 15 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 7C 7C 7C 7C 7C 7C 7C 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCA_FPLL VCCD_FPLL DNU IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DIFFIO_RX_T58n DIFFIO_TX_T59p DIFFIO_TX_T59n DIFFIO_RX_T60p DIFFIO_RX_T60n DIFFIO_TX_T61p DIFFIO_TX_T61n DIFFIO_RX_T62p DIFFIO_RX_T62n DIFFIO_TX_T63p DIFFIO_TX_T63n DIFFIO_RX_T64p DIFFIO_RX_T64n DIFFIO_TX_T65p DIFFIO_TX_T65n DIFFIO_RX_T66p DIFFIO_RX_T66n DIFFIO_TX_T67p DIFFIO_TX_T67n DIFFIO_RX_T68p DIFFIO_RX_T68n DIFFIO_TX_T69p DIFFIO_TX_T69n DIFFIO_RX_T70p DIFFIO_RX_T70n DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n DIFFOUT_T65p DIFFOUT_T65n DIFFOUT_T66p DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T67n DIFFOUT_T68p DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T69n DIFFOUT_T70p DIFFOUT_T70n DQSn6T/QK6T DQ6T DQ3T DQ3T DQ1T DQ1T DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ7T DQ7T DQ7T DQ4T DQ4T DQ4T DQ7T DQ7T DQ7T DQ4T DQ4T DQ4T DQS7T/CQ7T/CQn7T/QKn7T DQSn7T/QK7T DQ7T DQS4T/CQ4T/CQn4T/QKn4T DQSn4T/QK4T DQ4T DQ7T DQ7T DQ7T DQ4T DQ4T DQ4T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DIFFIO_RX_T71p DIFFIO_RX_T71n DIFFIO_TX_T72p DIFFIO_TX_T72n DIFFIO_RX_T73p DIFFIO_RX_T73n DIFFIO_TX_T74p DIFFIO_TX_T74n DIFFIO_RX_T75p DIFFIO_RX_T75n DIFFIO_TX_T76p DIFFIO_TX_T76n DIFFOUT_T71p DIFFOUT_T71n DIFFOUT_T72p DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T73n DIFFOUT_T74p DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T75n DIFFOUT_T76p DIFFOUT_T76n DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQS8T/CQ8T/CQn8T/QKn8T DQSn8T/QK8T DQ8T DQ4T DQ4T DQ4T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DIFFIO_RX_T85p DIFFIO_RX_T85n DIFFIO_TX_T86p DIFFIO_TX_T86n DIFFIO_RX_T87p DIFFIO_RX_T87n DIFFIO_TX_T88p DIFFIO_TX_T88n DIFFIO_RX_T89p DIFFIO_RX_T89n DIFFIO_TX_T90p DIFFIO_TX_T90n DIFFIO_RX_T91p DIFFIO_RX_T91n DIFFIO_TX_T92p DIFFIO_TX_T92n DIFFIO_RX_T93p DIFFIO_RX_T93n DIFFOUT_T85p DIFFOUT_T85n DIFFOUT_T86p DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T87n DIFFOUT_T88p DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T89n DIFFOUT_T90p DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T91n DIFFOUT_T92p DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T93n DQ9T DQ9T DQ9T DQ5T DQ5T DQ5T DQ9T DQ9T DQ9T DQ5T DQ5T DQ5T DQS9T/CQ9T/CQn9T/QKn9T DQSn9T/QK9T DQ9T DQS5T/CQ5T/CQn5T/QKn5T DQSn5T/QK5T DQ5T DQ9T DQ9T DQ9T DQ5T DQ5T DQ5T DQ10T DQ10T DQ10T DQ5T DQ5T DQ5T DIFFIO_RX_T94p DIFFIO_RX_T94n DIFFIO_TX_T95p DIFFIO_TX_T95n DIFFIO_RX_T96p DIFFIO_RX_T96n DIFFIO_TX_T97p DIFFIO_TX_T97n DIFFIO_RX_T98p DIFFIO_RX_T98n DIFFIO_TX_T99p DIFFIO_TX_T99n DIFFIO_RX_T116p DIFFIO_RX_T116n DIFFOUT_T94p DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T95n DIFFOUT_T96p DIFFOUT_T96n DIFFOUT_T97p DIFFOUT_T97n DIFFOUT_T98p DIFFOUT_T98n DIFFOUT_T99p DIFFOUT_T99n DIFFOUT_T116p DIFFOUT_T116n DQ10T DQ10T DQ10T DQ5T DQ5T DQ5T DQS10T/CQ10T/CQn10T/QKn10T DQSn10T/QK10T DQ10T DQ5T DQ5T DQ5T DQ10T DQ10T DQ10T DQ5T DQ5T DQ5T DQ11T DQ11T DQ11T DQ6T DQ6T DQ6T DQ2T DQ2T DQ2T DIFFIO_RX_T117p DIFFIO_RX_T117n DIFFIO_TX_T118p DIFFIO_TX_T118n DIFFIO_RX_T119p DIFFIO_RX_T119n DIFFIO_TX_T120p DIFFIO_TX_T120n DIFFIO_RX_T121p DIFFIO_RX_T121n DIFFIO_TX_T122p DIFFIO_TX_T122n DIFFIO_RX_T123p DIFFIO_RX_T123n DIFFIO_TX_T124p DIFFIO_TX_T124n DIFFIO_RX_T125p DIFFIO_RX_T125n DIFFIO_TX_T126p DIFFIO_TX_T126n DIFFIO_RX_T127p DIFFOUT_T117p DIFFOUT_T117n DIFFOUT_T118p DIFFOUT_T118n DIFFOUT_T119p DIFFOUT_T119n DIFFOUT_T120p DIFFOUT_T120n DIFFOUT_T121p DIFFOUT_T121n DIFFOUT_T122p DIFFOUT_T122n DIFFOUT_T123p DIFFOUT_T123n DIFFOUT_T124p DIFFOUT_T124n DIFFOUT_T125p DIFFOUT_T125n DIFFOUT_T126p DIFFOUT_T126n DIFFOUT_T127p B12 D12 E12 F13 G13 M11 N12 H14 J14 K14 L14 F14 G14 M14 M15 G15 H15 C13 D13 D14 E14 K15 L15 B14 C14 N15 N14 A14 B15 D15 E15 F16 G16 J16 K16 C16 D16 M16 N16 R17 R16 L18 A16 A17 K17 L17 K18 K19 D17 E17 F17 G17 M17 N17 H17 J17 B17 C17 A19 A20 M18 N18 C19 B18 G18 G19 H18 J19 M19 N19 D19 D18 E18 F19 K20 L20 M20 N20 A22 B21 B20 C20 D20 E20 K21 L21 F20 G20 H20 J20 D21 E21 M21 N21 C22 D22 G21 H21 F22 DQ11T DQ11T DQ11T DQ6T DQ6T DQ6T DQ2T DQ2T DQ2T DQS11T/CQ11T/CQn11T/QKn11T DQSn11T/QK11T DQ11T DQS6T/CQ6T/CQn6T/QKn6T DQSn6T/QK6T DQ6T DQ2T DQ2T DQ2T DQ11T DQ11T DQ11T DQ6T DQ6T DQ6T DQ2T DQ2T DQ2T DQ12T DQ12T DQ12T DQ6T DQ6T DQ6T DQ2T DQ2T DQ2T DQ12T DQ12T DQ12T DQ6T DQ6T DQ6T DQ2T DQ2T DQ2T DQS12T/CQ12T/CQn12T/QKn12T DQ6T DQS2T/CQ2T/CQn2T/QKn2T VREFB7DN0 CLK19p CLK19n CLK18p CLK18n FPLL_TC_CLKOUT2,FPLL_TC_FBp,FPLL_TC_FB1 FPLL_TC_CLKOUT3,FPLL_TC_FBn FPLL_TC_CLKOUT0,FPLL_TC_CLKOUTp,FPLL_TC_FB0 FPLL_TC_CLKOUT1,FPLL_TC_CLKOUTn CLK17p CLK17n CLK16p CLK16n VREFB8DN0 VREFB8CN0 Pin List GF35 DDR3/DDR2 hard memory PHY (3) DQS#1_7C DM1_7C DQ1_7C_6 DQ1_7C_7 DQ1_7C_8 RESET#_7D CK_7D CK#_7D CKE_7D_0 CKE_7D_1 A_7D_0 A_7D_1 A_7D_2 A_7D_3 A_7D_4 A_7D_5 A_7D_6 A_7D_7 A_7D_8 A_7D_9 A_7D_10 A_7D_11 A_7D_12 A_7D_13 A_7D_14 BA_7D_0 BA_7D_1 BA_7D_2 RAS#_7D CAS#_7D WE#_7D ODT_7D_0 ODT_7D_1 A_7D_15 CS#_7D_0 CS#_7D_1 Page 16 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 8C 8C 8C 8C 8C 8C 8C 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 CONF_DONE nSTATUS nCE nCONFIG GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DIFFIO_RX_T127n DIFFIO_TX_T128p DIFFIO_TX_T128n DIFFIO_RX_T129p DIFFIO_RX_T129n DIFFIO_TX_T130p DIFFIO_TX_T130n DIFFIO_RX_T131p DIFFIO_RX_T131n DIFFIO_TX_T132p DIFFIO_TX_T132n DIFFIO_RX_T133p DIFFIO_RX_T133n DIFFIO_TX_T134p DIFFIO_TX_T134n DIFFIO_RX_T135p DIFFIO_RX_T135n DIFFIO_TX_T136p DIFFIO_TX_T136n DIFFIO_RX_T137p DIFFIO_RX_T137n DIFFIO_TX_T138p DIFFIO_TX_T138n DIFFIO_RX_T139p DIFFIO_RX_T139n DIFFOUT_T127n DIFFOUT_T128p DIFFOUT_T128n DIFFOUT_T129p DIFFOUT_T129n DIFFOUT_T130p DIFFOUT_T130n DIFFOUT_T131p DIFFOUT_T131n DIFFOUT_T132p DIFFOUT_T132n DIFFOUT_T133p DIFFOUT_T133n DIFFOUT_T134p DIFFOUT_T134n DIFFOUT_T135p DIFFOUT_T135n DIFFOUT_T136p DIFFOUT_T136n DIFFOUT_T137p DIFFOUT_T137n DIFFOUT_T138p DIFFOUT_T138n DIFFOUT_T139p DIFFOUT_T139n DQSn12T/QK12T DQ12T DQ6T DQ6T DQSn2T/QK2T DQ2T DQ12T DQ12T DQ12T DQ6T DQ6T DQ6T DQ2T DQ2T DQ2T DQ13T DQ13T DQ13T DQ7T DQ7T DQ7T DQ2T DQ2T DQ2T DQ13T DQ13T DQ13T DQ7T DQ7T DQ7T DQ2T DQ2T DQ2T DQS13T/CQ13T/CQn13T/QKn13T DQSn13T/QK13T DQ13T DQS7T/CQ7T/CQn7T/QKn7T DQSn7T/QK7T DQ7T DQ2T DQ2T DQ2T DQ13T DQ13T DQ13T DQ7T DQ7T DQ7T DQ2T DQ2T DQ2T DQ14T DQ14T DQ14T DQ7T DQ7T DQ7T DQ2T DQ2T DQ2T DIFFIO_RX_T140p DIFFIO_RX_T140n DIFFIO_TX_T141p DIFFIO_TX_T141n DIFFIO_RX_T142p DIFFIO_RX_T142n DIFFIO_TX_T143p DIFFIO_TX_T143n DIFFIO_RX_T144p DIFFIO_RX_T144n DIFFIO_TX_T145p DIFFIO_TX_T145n DIFFIO_RX_T146p DIFFIO_RX_T146n DIFFIO_TX_T147p DIFFIO_TX_T147n DIFFIO_RX_T148p DIFFIO_RX_T148n DIFFIO_TX_T149p DIFFIO_TX_T149n DIFFIO_RX_T150p DIFFIO_RX_T150n DIFFIO_TX_T151p DIFFIO_TX_T151n DIFFIO_RX_T152p DIFFIO_RX_T152n DIFFIO_TX_T153p DIFFIO_TX_T153n DIFFIO_RX_T154p DIFFIO_RX_T154n DIFFIO_TX_T155p DIFFIO_TX_T155n DIFFIO_RX_T156p DIFFIO_RX_T156n DIFFIO_TX_T157p DIFFIO_TX_T157n DIFFIO_RX_T158p DIFFIO_RX_T158n DIFFIO_TX_T159p DIFFIO_TX_T159n DIFFIO_RX_T160p DIFFIO_RX_T160n DIFFIO_TX_T161p DIFFIO_TX_T161n DIFFIO_RX_T162p DIFFIO_RX_T162n DIFFOUT_T140p DIFFOUT_T140n DIFFOUT_T141p DIFFOUT_T141n DIFFOUT_T142p DIFFOUT_T142n DIFFOUT_T143p DIFFOUT_T143n DIFFOUT_T144p DIFFOUT_T144n DIFFOUT_T145p DIFFOUT_T145n DIFFOUT_T146p DIFFOUT_T146n DIFFOUT_T147p DIFFOUT_T147n DIFFOUT_T148p DIFFOUT_T148n DIFFOUT_T149p DIFFOUT_T149n DIFFOUT_T150p DIFFOUT_T150n DIFFOUT_T151p DIFFOUT_T151n DIFFOUT_T152p DIFFOUT_T152n DIFFOUT_T153p DIFFOUT_T153n DIFFOUT_T154p DIFFOUT_T154n DIFFOUT_T155p DIFFOUT_T155n DIFFOUT_T156p DIFFOUT_T156n DIFFOUT_T157p DIFFOUT_T157n DIFFOUT_T158p DIFFOUT_T158n DIFFOUT_T159p DIFFOUT_T159n DIFFOUT_T160p DIFFOUT_T160n DIFFOUT_T161p DIFFOUT_T161n DIFFOUT_T162p DIFFOUT_T162n DQ14T DQ14T DQ14T DQ7T DQ7T DQ7T DQ2T DQ2T DQ2T DQS14T/CQ14T/CQn14T/QKn14T DQSn14T/QK14T DQ14T DQ7T DQ7T DQ7T DQ2T DQ2T DQ2T DQ14T DQ14T DQ14T DQ7T DQ7T DQ7T DQ2T DQ2T DQ2T DQ15T DQ15T DQ15T DQ8T DQ8T DQ8T DQ15T DQ15T DQ15T DQ8T DQ8T DQ8T DQS15T/CQ15T/CQn15T/QKn15T DQSn15T/QK15T DQ15T DQS8T/CQ8T/CQn8T/QKn8T DQSn8T/QK8T DQ8T DQ15T DQ15T DQ15T DQ8T DQ8T DQ8T DQ16T DQ16T DQ16T DQ8T DQ8T DQ8T DQ16T DQ16T DQ16T DQ8T DQ8T DQ8T DQS16T/CQ16T/CQn16T/QKn16T DQSn16T/QK16T DQ16T DQ8T DQ8T DQ8T DQ16T DQ16T DQ16T DQ8T DQ8T DQ8T DIFFIO_RX_T163p DIFFIO_RX_T163n DIFFIO_TX_T164p DIFFIO_TX_T164n DIFFIO_RX_T165p DIFFIO_RX_T165n DIFFIO_TX_T166p DIFFIO_TX_T166n DIFFIO_RX_T167p DIFFIO_RX_T167n DIFFIO_TX_T168p DIFFIO_TX_T168n DIFFOUT_T163p DIFFOUT_T163n DIFFOUT_T164p DIFFOUT_T164n DIFFOUT_T165p DIFFOUT_T165n DIFFOUT_T166p DIFFOUT_T166n DIFFOUT_T167p DIFFOUT_T167n DIFFOUT_T168p DIFFOUT_T168n G22 M22 N22 A23 B23 J22 K22 H23 J23 K24 L24 B24 C23 D23 E23 F23 G23 M23 N23 D24 E24 K23 L23 G24 H24 M24 N24 A26 A25 C25 D25 F25 G25 M25 N25 B26 C26 J25 K25 E26 F26 K29 L29 D26 E27 A27 B27 G26 H26 K27 L27 D27 C28 C29 D28 G27 G28 J26 K26 A29 A28 B29 B30 F28 F29 H27 J27 D29 E29 D30 E30 G29 H29 L26 M27 A31 A30 C31 D31 A32 B32 J28 K28 D33 C32 D32 E32 D34 H30 K30 M29 M30 C34 B34 A33 C33 B33 AA26 AA33 VREFB8BN0 CLK23p CLK23n CLK22p CLK22n VREFB8AN0 FPLL_TL_CLKOUT2,FPLL_TL_FBp,FPLL_TL_FB1 FPLL_TL_CLKOUT3,FPLL_TL_FBn FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB0 FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn CLK21p CLK21n CLK20p CLK20n RZQ_6 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 CONF_DONE nSTATUS nCE nCONFIG Pin List GF35 DDR3/DDR2 hard memory PHY (3) DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQS17T/CQ17T/CQn17T/QKn17T DQSn17T/QK17T DQ17T DQ17T DQ17T DQ17T Page 17 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1152 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) AA34 AB27 AB28 AB29 AB30 AB31 AB32 AC30 AC33 AC34 AD31 AD32 AE30 AE33 AE34 AF31 AF32 AG30 AG33 AG34 AH31 AH32 AJ30 AJ33 AJ34 AK31 AK32 AL33 AL34 E34 F31 F32 G30 G33 G34 H31 H32 J30 J33 J34 K31 K32 L30 L33 L34 M31 M32 N28 N29 N33 N34 P27 P31 P32 R28 R30 R33 R34 T27 T29 T31 T32 U28 U33 U34 V27 V31 V32 W28 W30 W33 W34 Y27 Y29 Y31 Y32 AA1 AA2 AA9 AB3 AB4 AB5 AB7 AB8 AC1 AC2 AC5 AD3 AD4 AE1 AE2 AE5 AF3 AF4 AG1 AG2 AG5 AH3 AH4 Pin List GF35 Page 18 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCBAT VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCA_GXBL0 VCCA_GXBR0 VCCA_GXBL1 VCCA_GXBR1 VCCH_GXBL0 VCCH_GXBR0 VCCH_GXBL1 VCCH_GXBR1 VCCL_GXBL0 VCCL_GXBL0 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBL1 VCCL_GXBL1 VCCL_GXBR1 VCCL_GXBR1 VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1152 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) AJ1 AJ2 AJ5 AK3 AK4 AL1 AL2 AL3 AN1 F3 F4 G1 G2 G5 H3 H4 J1 J2 J5 K3 K4 L1 L2 L5 M3 M4 M5 N1 N2 N6 P3 P4 P8 R1 R2 R5 R7 T3 T4 T6 T8 U1 U2 U7 V3 V4 V8 W1 W2 W5 W7 Y3 Y4 Y6 Y8 P18 R13 R21 T10 U25 V10 W25 Y12 Y19 Y22 V26 V9 T26 T9 M28 P12 P24 W11 Y24 Y26 Y9 P26 P9 Y28 Y7 T28 T7 V28 V7 P28 P7 V29 V30 V5 V6 P29 P30 P5 P6 AA29 AA30 N30 U29 U30 Pin List GF35 Page 19 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCT_GXBL0 VCCT_GXBL0 VCCT_GXBR0 VCCT_GXBR0 VCCT_GXBL1 VCCT_GXBL1 VCCT_GXBR1 VCCT_GXBR1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3C VCCIO3C VCCIO3C VCCIO3C VCCIO3D VCCIO3D VCCIO3D VCCIO3D VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4C VCCIO4C VCCIO4C VCCIO4C VCCIO4D VCCIO4D VCCIO4D VCCIO4D VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7B VCCIO7B VCCIO7B VCCIO7B VCCIO7C VCCIO7C VCCIO7C VCCIO7C VCCIO7D VCCIO7D VCCIO7D PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1152 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) AA5 AA6 N5 U5 U6 W29 Y30 W6 Y5 R29 T30 R6 T5 R14 R15 R19 R23 R25 T12 T14 T16 T18 T20 T22 T24 U11 U12 U13 U15 U17 U19 U20 U21 U22 U23 V12 V14 V16 V20 V22 V24 W13 W15 W17 W19 W21 W23 Y13 Y20 V18 AD30 AF27 AH30 AJ27 AK30 AM27 AF24 AJ24 AM24 AP24 AF21 AJ21 AM21 AP21 AF18 AJ18 AM18 AP18 AD5 AF5 AH5 AK5 AF9 AJ9 AM9 AP9 AF12 AJ12 AM12 AP12 AF15 AJ15 AM15 AP15 C5 F2 F5 L7 A9 C9 F9 J9 A12 C12 F12 J12 A15 C15 F15 Pin List GF35 Page 20 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCIO7D VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8B VCCIO8B VCCIO8B VCCIO8B VCCIO8C VCCIO8C VCCIO8C VCCIO8C VCCIO8D VCCIO8D VCCIO8D VCCIO8D VCCPD3 VCCPD3 VCCPD3 VCCPD3 VCCPD4A VCCPD4A VCCPD4BCD VCCPD4BCD VCCPD4BCD VCCPD7A VCCPD7A VCCPD7BCD VCCPD7BCD VCCPD7BCD VCCPD8 VCCPD8 VCCPD8 VCCPD8 VCCPGM VCCPGM GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1152 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) J15 C27 C30 F27 F30 J29 M26 A24 C24 F24 J24 A21 C21 F21 J21 A18 C18 F18 J18 AB26 AC27 Y21 Y25 AB6 AB9 Y10 Y14 Y16 N8 N9 P14 P16 R11 N26 N27 P20 P22 M9 AC26 AA11 AA13 AA16 AA19 AA22 AA24 AD10 AD13 AD16 AD19 AD22 AD25 AD28 AD7 AG10 AG13 AG16 AG19 AG22 AG25 AG28 AG7 AK10 AK13 AK16 AK19 AK22 AK25 AK28 AK7 AN10 AN13 AN16 AN19 AN22 AN25 AN28 AN31 AN4 AN7 B1 B10 B13 B16 B19 B22 B25 B28 B31 B4 B7 D2 D4 E10 E13 E16 E19 E22 E25 E28 Pin List GF35 Page 21 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Emulated LVDS Output Channel F1152 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) E31 E7 H10 H13 H16 H19 H22 H25 H28 H7 L10 L13 L16 L19 L22 L25 L28 L8 M6 N7 P10 P13 P15 P17 P19 P21 P23 P25 R10 R12 R18 R20 R22 R24 T11 T13 T15 T17 T19 T21 T23 T25 U10 U14 U16 U24 V11 V13 V15 V17 V19 V21 V23 V25 W10 W12 W14 W16 W18 W20 W22 W24 U18 Notes: (1) For more information about pin definitions and pin connection guidelines, refer to the Arria V Device Family Pin Connection Guidelines. (2) GXB_REFCLK pin is not supported in current Quartus II version, but will be supported in future Quartus II release version. (3) RESET pin is only applicable for DDR3 device. PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Pin List GF35 Page 22 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 DNU DNU RREF_TL GND GND DNU DNU GND GND DNU DNU GND GND DNU DNU GND GND GXB_TX_L8n GXB_TX_L8p GXB_RX_L8p,GXB_REFCLK_L8p GXB_RX_L8n,GXB_REFCLK_L8n GXB_TX_L7n GXB_TX_L7p GXB_RX_L7p,GXB_REFCLK_L7p GXB_RX_L7n,GXB_REFCLK_L7n GXB_TX_L6n GXB_TX_L6p GXB_RX_L6p,GXB_REFCLK_L6p GXB_RX_L6n,GXB_REFCLK_L6n REFCLK2Ln REFCLK2Lp REFCLK1Ln REFCLK1Lp GXB_TX_L5n GXB_TX_L5p GXB_RX_L5p,GXB_REFCLK_L5p GXB_RX_L5n,GXB_REFCLK_L5n GXB_TX_L4n GXB_TX_L4p GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_TX_L3n GXB_TX_L3p GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_TX_L2n GXB_TX_L2p GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n GXB_TX_L1n GXB_TX_L1p GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_TX_L0n GXB_TX_L0p GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n REFCLK0Ln REFCLK0Lp DNU TDO TMS TCK TDI DCLK nCSO AS_DATA3 AS_DATA2 AS_DATA1 AS_DATA0,ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel TDO TMS TCK TDI DCLK DATA4 DATA3 DATA2 DATA1 DATA0 RZQ_0 CLK0n CLK0p CLK1n CLK1p FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB0 FPLL_BL_CLKOUT3,FPLL_BL_FBn FPLL_BL_CLKOUT2,FPLL_BL_FBp,FPLL_BL_FB1 VREFB3AN0 CLK2n CLK2p CLK3n CLK3p DIFFIO_TX_B1n DIFFIO_TX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_TX_B3n DIFFIO_TX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_TX_B5n DIFFIO_TX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_TX_B8n DIFFIO_TX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_TX_B10n DIFFIO_TX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_TX_B12n DIFFIO_TX_B12p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p Pin List GF40 F1517 A38 B38 B39 AA32 AA31 R36 R37 T39 T38 U36 U37 V39 V38 W36 W37 Y39 Y38 AA36 AA37 AB39 AB38 AC36 AC37 AD39 AD38 AE36 AE37 AF39 AF38 AC32 AC31 AE32 AE31 AG36 AG37 AH39 AH38 AJ36 AJ37 AK39 AK38 AL36 AL37 AM39 AM38 AN36 AN37 AP39 AP38 AR36 AR37 AT39 AT38 AU36 AU37 AW37 AW36 AG33 AG32 AH31 AT34 AM35 AV34 AT33 AW34 AR34 AU34 AR33 AU33 AV33 AN33 AP33 AN34 AP34 AK32 AL32 AJ34 AK34 AL34 AM34 AJ33 AK33 AJ31 AK31 AL33 AM33 AN32 AP32 AT32 AU32 AL31 AM31 AW33 AW32 AN31 AP31 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ1B DQ1B DQ1B DQ1B DQSn1B/QK1B DQS1B/CQ1B/CQn1B/QKn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ2B DQSn2B/QK2B DQS2B/CQ2B/CQn2B/QKn2B DQ1B DQ1B DQ1B DQ2B DQ1B Page 23 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DIFFIO_RX_B13n DIFFIO_RX_B13p DIFFIO_TX_B14n DIFFIO_TX_B14p DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_TX_B16n DIFFIO_TX_B16p DIFFIO_RX_B17n DIFFIO_RX_B17p DIFFIO_TX_B18n DIFFIO_TX_B18p DIFFIO_RX_B19n DIFFIO_RX_B19p DIFFIO_TX_B20n DIFFIO_TX_B20p DIFFIO_RX_B21n DIFFIO_RX_B21p DIFFIO_TX_B22n DIFFIO_TX_B22p DIFFIO_RX_B23n DIFFIO_RX_B23p DIFFIO_TX_B24n DIFFIO_TX_B24p DIFFIO_RX_B25n DIFFIO_RX_B25p DIFFIO_TX_B26n DIFFIO_TX_B26p DIFFIO_RX_B27n DIFFIO_RX_B27p DIFFIO_TX_B28n DIFFIO_TX_B28p DIFFIO_RX_B29n DIFFIO_RX_B29p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DQ2B DQ2B DQ1B DQ1B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ3B DQSn3B/QK3B DQS3B/CQ3B/CQn3B/QKn3B DQ1B DQSn1B/QK1B DQS1B/CQ1B/CQn1B/QKn1B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ4B DQSn4B/QK4B DQS4B/CQ4B/CQn4B/QKn4B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DIFFIO_RX_B30n DIFFIO_RX_B30p DIFFIO_TX_B31n DIFFIO_TX_B31p DIFFIO_RX_B32n DIFFIO_RX_B32p DIFFIO_TX_B33n DIFFIO_TX_B33p DIFFIO_RX_B34n DIFFIO_RX_B34p DIFFIO_TX_B35n DIFFIO_TX_B35p DIFFIO_RX_B36n DIFFIO_RX_B36p DIFFIO_TX_B37n DIFFIO_TX_B37p DIFFIO_RX_B38n DIFFIO_RX_B38p DIFFIO_TX_B39n DIFFIO_TX_B39p DIFFIO_RX_B40n DIFFIO_RX_B40p DIFFIO_TX_B41n DIFFIO_TX_B41p DIFFIO_RX_B42n DIFFIO_RX_B42p DIFFIO_TX_B43n DIFFIO_TX_B43p DIFFIO_RX_B44n DIFFIO_RX_B44p DIFFIO_TX_B45n DIFFIO_TX_B45p DIFFIO_RX_B46n DIFFIO_RX_B46p DIFFIO_TX_B47n DIFFIO_TX_B47p DIFFIO_RX_B48n DIFFIO_RX_B48p DIFFIO_TX_B49n DIFFIO_TX_B49p DIFFIO_RX_B50n DIFFIO_RX_B50p DIFFIO_TX_B51n DIFFIO_TX_B51p DIFFIO_RX_B52n DIFFIO_RX_B52p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33n DIFFOUT_B33p DIFFOUT_B34n DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B35p DIFFOUT_B36n DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B37p DIFFOUT_B38n DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B39p DIFFOUT_B40n DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B41p DIFFOUT_B42n DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B43p DIFFOUT_B44n DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B45p DIFFOUT_B46n DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B47p DIFFOUT_B48n DIFFOUT_B48p DIFFOUT_B49n DIFFOUT_B49p DIFFOUT_B50n DIFFOUT_B50p DIFFOUT_B51n DIFFOUT_B51p DIFFOUT_B52n DIFFOUT_B52p DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ5B DQSn5B/QK5B DQS5B/CQ5B/CQn5B/QKn5B DQ2B DQSn2B/QK2B DQS2B/CQ2B/CQn2B/QKn2B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ6B DQ6B DQ6B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ6B DQSn6B/QK6B DQS6B/CQ6B/CQn6B/QKn6B DQ3B DQ3B DQ3B DQ1B DQSn1B/QK1B DQS1B/CQ1B/CQn1B/QKn1B DQ6B DQ6B DQ6B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ6B DQ6B DQ6B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ7B DQSn7B/QK7B DQS7B/CQ7B/CQn7B/QKn7B DQ3B DQSn3B/QK3B DQS3B/CQ3B/CQn3B/QKn3B DQ1B DQ1B DQ1B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DIFFIO_RX_B53n DIFFIO_RX_B53p DIFFIO_TX_B54n DIFFIO_TX_B54p DIFFIO_RX_B55n DIFFIO_RX_B55p DIFFIO_TX_B56n DIFFIO_TX_B56p DIFFIO_RX_B57n DIFFIO_RX_B57p DIFFIO_TX_B58n DIFFIO_TX_B58p DIFFOUT_B53n DIFFOUT_B53p DIFFOUT_B54n DIFFOUT_B54p DIFFOUT_B55n DIFFOUT_B55p DIFFOUT_B56n DIFFOUT_B56p DIFFOUT_B57n DIFFOUT_B57p DIFFOUT_B58n DIFFOUT_B58p AR31 AT31 AD29 AE29 AG30 AH30 AU31 AV31 AW30 AW31 AK30 AL30 AR30 AT30 AU30 AV30 AT29 AU29 AN30 AP30 AN29 AP29 AB29 AC29 AF28 AG28 AK29 AL29 AH28 AJ28 AD28 AE28 AB27 AB28 AL28 AM28 AC27 AD27 AP28 AR28 AU28 AV28 AJ27 AK27 AW29 AW28 AP27 AR27 AT27 AU27 AM27 AN27 AV27 AW27 AG27 AH27 AB25 AC25 AE27 AF27 AE25 AF25 AC24 AD25 AG26 AH26 AD26 AE26 AG25 AH25 AN26 AP26 AM25 AN25 AJ25 AK25 AT26 AU26 AR25 AT25 AW25 AW26 AK26 AL26 AV25 AV24 AD23 AD24 AT24 AU24 AK24 AL24 AE24 AF24 AG24 AH24 DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ8B DQ8B DQ8B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ8B DQSn8B/QK8B DQS8B/CQ8B/CQn8B/QKn8B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ8B DQ4B DQ2B VREFB3BN0 VREFB3CN0 Pin List GF40 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) Page 24 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 3C 3C 3C 3C 3C 3C 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D 3D VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 VREFB3DN0 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D 4D VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCD_FPLL VCCA_FPLL DNU IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DIFFIO_RX_B59n DIFFIO_RX_B59p DIFFIO_TX_B60n DIFFIO_TX_B60p DIFFIO_RX_B61n DIFFIO_RX_B61p DIFFIO_TX_B62n DIFFIO_TX_B62p DIFFIO_RX_B63n DIFFIO_RX_B63p DIFFIO_TX_B64n DIFFIO_TX_B64p DIFFIO_RX_B65n DIFFIO_RX_B65p DIFFIO_TX_B66n DIFFIO_TX_B66p DIFFIO_RX_B67n DIFFIO_RX_B67p DIFFIO_TX_B68n DIFFIO_TX_B68p DIFFIO_RX_B69n DIFFIO_RX_B69p DIFFIO_TX_B70n DIFFIO_TX_B70p DIFFIO_RX_B71n DIFFIO_RX_B71p DIFFIO_TX_B72n DIFFIO_TX_B72p DIFFIO_RX_B73n DIFFIO_RX_B73p DIFFIO_TX_B74n DIFFIO_TX_B74p DIFFIO_RX_B75n DIFFIO_RX_B75p DIFFOUT_B59n DIFFOUT_B59p DIFFOUT_B60n DIFFOUT_B60p DIFFOUT_B61n DIFFOUT_B61p DIFFOUT_B62n DIFFOUT_B62p DIFFOUT_B63n DIFFOUT_B63p DIFFOUT_B64n DIFFOUT_B64p DIFFOUT_B65n DIFFOUT_B65p DIFFOUT_B66n DIFFOUT_B66p DIFFOUT_B67n DIFFOUT_B67p DIFFOUT_B68n DIFFOUT_B68p DIFFOUT_B69n DIFFOUT_B69p DIFFOUT_B70n DIFFOUT_B70p DIFFOUT_B71n DIFFOUT_B71p DIFFOUT_B72n DIFFOUT_B72p DIFFOUT_B73n DIFFOUT_B73p DIFFOUT_B74n DIFFOUT_B74p DIFFOUT_B75n DIFFOUT_B75p DQ8B DQ8B DQ4B DQ4B DQ2B DQ2B DQ8B DQ8B DQ8B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ9B DQSn9B/QK9B DQS9B/CQ9B/CQn9B/QKn9B DQ4B DQSn4B/QK4B DQS4B/CQ4B/CQn4B/QKn4B DQ2B DQ2B DQ2B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ10B DQ10B DQ10B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ10B DQSn10B/QK10B DQS10B/CQ10B/CQn10B/QKn10B DQ5B DQ5B DQ5B DQ2B DQSn2B/QK2B DQS2B/CQ2B/CQn2B/QKn2B DQ10B DQ10B DQ10B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DIFFIO_RX_B76n DIFFIO_RX_B76p DIFFIO_TX_B77n DIFFIO_TX_B77p DIFFIO_RX_B78n DIFFIO_RX_B78p DIFFIO_TX_B79n DIFFIO_TX_B79p DIFFIO_RX_B80n DIFFIO_RX_B80p DIFFIO_TX_B81n DIFFIO_TX_B81p DIFFIO_RX_B82n DIFFIO_RX_B82p DIFFIO_TX_B83n DIFFIO_TX_B83p DIFFIO_RX_B84n DIFFIO_RX_B84p DIFFOUT_B76n DIFFOUT_B76p DIFFOUT_B77n DIFFOUT_B77p DIFFOUT_B78n DIFFOUT_B78p DIFFOUT_B79n DIFFOUT_B79p DIFFOUT_B80n DIFFOUT_B80p DIFFOUT_B81n DIFFOUT_B81p DIFFOUT_B82n DIFFOUT_B82p DIFFOUT_B83n DIFFOUT_B83p DIFFOUT_B84n DIFFOUT_B84p DQ10B DQ10B DQ10B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ11B DQ11B DQ11B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ11B DQSn11B/QK11B DQS11B/CQ11B/CQn11B/QKn11B DQ5B DQSn5B/QK5B DQS5B/CQ5B/CQn5B/QKn5B DQ2B DQ2B DQ2B DQ11B DQ11B DQ11B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ11B DQ11B DQ11B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DIFFIO_TX_B85n DIFFIO_TX_B85p DIFFIO_RX_B86n DIFFIO_RX_B86p DIFFIO_TX_B87n DIFFIO_TX_B87p DIFFIO_RX_B88n DIFFIO_RX_B88p DIFFIO_TX_B89n DIFFIO_TX_B89p DIFFIO_RX_B90n DIFFIO_RX_B90p DIFFIO_TX_B91n DIFFIO_TX_B91p DIFFIO_RX_B92n DIFFIO_RX_B92p DIFFIO_TX_B93n DIFFIO_TX_B93p DIFFIO_RX_B94n DIFFIO_RX_B94p DIFFIO_TX_B95n DIFFIO_TX_B95p DIFFIO_RX_B96n DIFFIO_RX_B96p DIFFIO_TX_B97n DIFFIO_TX_B97p DIFFIO_RX_B98n DIFFIO_RX_B98p DIFFOUT_B85n DIFFOUT_B85p DIFFOUT_B86n DIFFOUT_B86p DIFFOUT_B87n DIFFOUT_B87p DIFFOUT_B88n DIFFOUT_B88p DIFFOUT_B89n DIFFOUT_B89p DIFFOUT_B90n DIFFOUT_B90p DIFFOUT_B91n DIFFOUT_B91p DIFFOUT_B92n DIFFOUT_B92p DIFFOUT_B93n DIFFOUT_B93p DIFFOUT_B94n DIFFOUT_B94p DIFFOUT_B95n DIFFOUT_B95p DIFFOUT_B96n DIFFOUT_B96p DIFFOUT_B97n DIFFOUT_B97p DIFFOUT_B98n DIFFOUT_B98p DIFFIO_RX_B99n DIFFIO_RX_B99p DIFFIO_TX_B100n DIFFIO_TX_B100p DIFFIO_RX_B101n DIFFIO_RX_B101p DIFFIO_TX_B102n DIFFIO_TX_B102p DIFFIO_RX_B103n DIFFOUT_B99n DIFFOUT_B99p DIFFOUT_B100n DIFFOUT_B100p DIFFOUT_B101n DIFFOUT_B101p DIFFOUT_B102n DIFFOUT_B102p DIFFOUT_B103n AW23 AW24 AN24 AP24 AT23 AU23 AN23 AP23 AD22 AE23 AK23 AL23 AT22 AU22 AV22 AW22 AV21 AW21 AG23 AH23 AE22 AF22 AN22 AP22 AW19 AW20 AK22 AL22 AR21 AT21 AG22 AH22 AT20 AU20 AJ21 AK21 AU19 AV19 AM21 AN21 AE21 AF21 AD21 AC22 AG21 AH21 AN20 AP20 AC21 AD20 AG20 AH20 AK20 AL20 AB20 AB21 AE20 AV18 AW18 AG19 AH19 AN19 AP19 AK19 AL19 AH18 AJ18 AU18 AT19 AE19 AF19 AW17 AW16 AK17 AL17 AT17 AU17 AC19 AD19 AP18 AR18 AD17 AC18 AD18 AE18 AF18 AG18 AL18 AM18 AG17 AH17 AN17 AP17 AR16 AT16 AU16 VREFB3DN0 CLK4n CLK4p CLK5n CLK5p FPLL_BC_CLKOUT1,FPLL_BC_CLKOUTn FPLL_BC_CLKOUT0,FPLL_BC_CLKOUTp,FPLL_BC_FB0 FPLL_BC_CLKOUT3,FPLL_BC_FBn FPLL_BC_CLKOUT2,FPLL_BC_FBp,FPLL_BC_FB1 CLK6n CLK6p CLK7n CLK7p VREFB4DN0 Pin List GF40 DDR3/DDR2 hard memory PHY (3) DQ12B DQ12B DQ12B DQ12B DQSn12B/QK12B DQS12B/CQ12B/CQn12B/QKn12B DQ12B DQ12B DQ12B DQ12B DQ12B DQ12B DQ13B DQ13B DQ13B DQ6B DQ6B DQ6B DQ13B DQSn13B/QK13B DQS13B/CQ13B/CQn13B/QKn13B DQ6B DQ6B DQ6B DQ13B DQ13B DQ13B DQ6B DQ6B DQ6B DQ13B DQ13B DQ13B DQ6B DQ6B DQ6B DQ14B DQ14B DQ14B DQ6B DQ6B DQ6B DQ14B DQSn14B/QK14B DQ6B DQSn6B/QK6B CS#_4D_1 CS#_4D_0 A_4D_15 ODT_4D_1 ODT_4D_0 WE#_4D CAS#_4D RAS#_4D BA_4D_2 BA_4D_1 BA_4D_0 A_4D_14 A_4D_13 A_4D_12 A_4D_11 A_4D_10 A_4D_9 A_4D_8 A_4D_7 A_4D_6 A_4D_5 Page 25 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 4D 4D 4D 4D 4D 4D 4D 4D 4D 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4A 4A 4A 4A 4A 4A 4A VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4DN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DIFFIO_RX_B103p DIFFIO_TX_B104n DIFFIO_TX_B104p DIFFIO_RX_B105n DIFFIO_RX_B105p DIFFIO_TX_B106n DIFFIO_TX_B106p DIFFIO_RX_B107n DIFFIO_RX_B107p DIFFIO_TX_B108n DIFFIO_TX_B108p DIFFIO_RX_B109n DIFFIO_RX_B109p DIFFIO_TX_B110n DIFFIO_TX_B110p DIFFIO_RX_B111n DIFFIO_RX_B111p DIFFIO_TX_B112n DIFFIO_TX_B112p DIFFIO_RX_B113n DIFFIO_RX_B113p DIFFOUT_B103p DIFFOUT_B104n DIFFOUT_B104p DIFFOUT_B105n DIFFOUT_B105p DIFFOUT_B106n DIFFOUT_B106p DIFFOUT_B107n DIFFOUT_B107p DIFFOUT_B108n DIFFOUT_B108p DIFFOUT_B109n DIFFOUT_B109p DIFFOUT_B110n DIFFOUT_B110p DIFFOUT_B111n DIFFOUT_B111p DIFFOUT_B112n DIFFOUT_B112p DIFFOUT_B113n DIFFOUT_B113p DQS14B/CQ14B/CQn14B/QKn14B DQS6B/CQ6B/CQn6B/QKn6B DQ14B DQ14B DQ14B DQ6B DQ6B DQ6B DQ14B DQ14B DQ14B DQ6B DQ6B DQ6B DQ15B DQ15B DQ15B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DDR3/DDR2 hard memory PHY (3) A_4D_4 A_4D_3 A_4D_2 A_4D_1 A_4D_0 CKE_4D_1 CKE_4D_0 CK#_4D CK_4D RESET#_4D DQ1_4C_8 DQ1_4C_7 DQ1_4C_6 DQ15B DQSn15B/QK15B DQS15B/CQ15B/CQn15B/QKn15B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DM1_4C DQS#1_4C DQS1_4C DQ15B DQ15B DQ15B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1_4C_5 DQ1_4C_4 DQ1_4C_3 DIFFIO_RX_B114n DIFFIO_RX_B114p DIFFIO_TX_B115n DIFFIO_TX_B115p DIFFIO_RX_B116n DIFFIO_RX_B116p DIFFIO_TX_B117n DIFFIO_TX_B117p DIFFIO_RX_B118n DIFFIO_RX_B118p DIFFIO_TX_B119n DIFFIO_TX_B119p DIFFIO_RX_B120n DIFFIO_RX_B120p DIFFIO_TX_B121n DIFFIO_TX_B121p DIFFIO_RX_B122n DIFFIO_RX_B122p DIFFIO_TX_B123n DIFFIO_TX_B123p DIFFIO_RX_B124n DIFFIO_RX_B124p DIFFIO_TX_B125n DIFFIO_TX_B125p DIFFIO_RX_B126n DIFFIO_RX_B126p DIFFIO_TX_B127n DIFFIO_TX_B127p DIFFIO_RX_B128n DIFFIO_RX_B128p DIFFIO_TX_B129n DIFFIO_TX_B129p DIFFIO_RX_B130n DIFFIO_RX_B130p DIFFIO_TX_B131n DIFFIO_TX_B131p DIFFIO_RX_B132n DIFFIO_RX_B132p DIFFIO_TX_B133n DIFFIO_TX_B133p DIFFIO_RX_B134n DIFFIO_RX_B134p DIFFIO_TX_B135n DIFFIO_TX_B135p DIFFIO_RX_B136n DIFFIO_RX_B136p DIFFOUT_B114n DIFFOUT_B114p DIFFOUT_B115n DIFFOUT_B115p DIFFOUT_B116n DIFFOUT_B116p DIFFOUT_B117n DIFFOUT_B117p DIFFOUT_B118n DIFFOUT_B118p DIFFOUT_B119n DIFFOUT_B119p DIFFOUT_B120n DIFFOUT_B120p DIFFOUT_B121n DIFFOUT_B121p DIFFOUT_B122n DIFFOUT_B122p DIFFOUT_B123n DIFFOUT_B123p DIFFOUT_B124n DIFFOUT_B124p DIFFOUT_B125n DIFFOUT_B125p DIFFOUT_B126n DIFFOUT_B126p DIFFOUT_B127n DIFFOUT_B127p DIFFOUT_B128n DIFFOUT_B128p DIFFOUT_B129n DIFFOUT_B129p DIFFOUT_B130n DIFFOUT_B130p DIFFOUT_B131n DIFFOUT_B131p DIFFOUT_B132n DIFFOUT_B132p DIFFOUT_B133n DIFFOUT_B133p DIFFOUT_B134n DIFFOUT_B134p DIFFOUT_B135n DIFFOUT_B135p DIFFOUT_B136n DIFFOUT_B136p DQ15B DQ15B DQ15B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ1_4C_2 DQ1_4C_1 DQ1_4C_0 DQ16B DQ16B DQ16B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ2_4C_8 DQ2_4C_7 DQ2_4C_6 DQ16B DQSn16B/QK16B DQS16B/CQ16B/CQn16B/QKn16B DQ7B DQSn7B/QK7B DQS7B/CQ7B/CQn7B/QKn7B DQ3B DQ3B DQ3B DM2_4C DQS#2_4C DQS2_4C DQ16B DQ16B DQ16B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ2_4C_5 DQ2_4C_4 DQ2_4C_3 DQ16B DQ16B DQ16B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ2_4C_2 DQ2_4C_1 DQ2_4C_0 DQ17B DQ17B DQ17B DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ3_4B_8 DQ3_4B_7 DQ3_4B_6 DQ17B DQSn17B/QK17B DQS17B/CQ17B/CQn17B/QKn17B DQ8B DQ8B DQ8B DQ3B DQSn3B/QK3B DQS3B/CQ3B/CQn3B/QKn3B DM3_4B DQS#3_4B DQS3_4B DQ17B DQ17B DQ17B DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ3_4B_5 DQ3_4B_4 DQ3_4B_3 DQ17B DQ17B DQ17B DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ3_4B_2 DQ3_4B_1 DQ3_4B_0 DQ18B DQ18B DQ18B DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ4_4B_8 DQ4_4B_7 DQ4_4B_6 DQ18B DQSn18B/QK18B DQS18B/CQ18B/CQn18B/QKn18B DQ8B DQSn8B/QK8B DQS8B/CQ8B/CQn8B/QKn8B DQ3B DQ3B DQ3B DM4_4B DQS#4_4B DQS4_4B DQ18B DQ18B DQ18B DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ4_4B_5 DQ4_4B_4 DQ4_4B_3 DIFFIO_RX_B137n DIFFIO_RX_B137p DIFFIO_TX_B138n DIFFIO_TX_B138p DIFFIO_RX_B139n DIFFIO_RX_B139p DIFFIO_TX_B140n DIFFIO_TX_B140p DIFFIO_RX_B141n DIFFIO_RX_B141p DIFFIO_TX_B142n DIFFIO_TX_B142p DIFFIO_RX_B143n DIFFIO_RX_B143p DIFFIO_TX_B144n DIFFIO_TX_B144p DIFFIO_RX_B145n DIFFIO_RX_B145p DIFFIO_TX_B146n DIFFIO_TX_B146p DIFFIO_RX_B147n DIFFIO_RX_B147p DIFFIO_TX_B148n DIFFIO_TX_B148p DIFFIO_RX_B149n DIFFOUT_B137n DIFFOUT_B137p DIFFOUT_B138n DIFFOUT_B138p DIFFOUT_B139n DIFFOUT_B139p DIFFOUT_B140n DIFFOUT_B140p DIFFOUT_B141n DIFFOUT_B141p DIFFOUT_B142n DIFFOUT_B142p DIFFOUT_B143n DIFFOUT_B143p DIFFOUT_B144n DIFFOUT_B144p DIFFOUT_B145n DIFFOUT_B145p DIFFOUT_B146n DIFFOUT_B146p DIFFOUT_B147n DIFFOUT_B147p DIFFOUT_B148n DIFFOUT_B148p DIFFOUT_B149n AV16 AJ16 AK16 AN16 AP16 AL16 AM16 AE17 AF16 AN15 AP15 AW14 AW15 AC16 AD16 AG16 AH16 AK15 AL15 AV13 AW13 AG15 AH15 AT15 AU15 AC15 AD14 AT14 AU14 AT13 AU13 AE16 AF15 AK14 AL14 AN14 AP14 AG14 AH14 AD15 AE15 AP13 AR13 AE14 AE13 AT12 AU12 AV12 AW12 AL13 AM13 AW10 AW11 AN12 AP12 AH13 AJ13 AH12 AJ12 AF13 AG13 AU10 AV10 AT11 AU11 AK12 AL12 AC13 AD13 AN11 AP11 AV9 AW9 AC12 AD11 AF12 AG12 AT9 AU9 AG11 AH11 AD12 AE12 AP10 AR10 AK11 AL11 AL10 AM10 AL9 AM9 AW7 AW8 AV7 AV6 AW6 DQ18B DQ18B DQ18B DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ4_4B_2 DQ4_4B_1 DQ4_4B_0 DQ19B DQ19B DQ19B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ5_4B_8 DQ5_4B_7 DQ5_4B_6 DQ19B DQSn19B/QK19B DQS19B/CQ19B/CQn19B/QKn19B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DM5_4B DQS#5_4B DQS5_4B DQ19B DQ19B DQ19B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ5_4B_5 DQ5_4B_4 DQ5_4B_3 DQ19B DQ19B DQ19B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ5_4B_2 DQ5_4B_1 DQ5_4B_0 DQ20B DQ20B DQ20B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ20B DQSn20B/QK20B DQ9B DQSn9B/QK9B DQ4B DQ4B VREFB4CN0 VREFB4BN0 Pin List GF40 DQS for X32/ X36 Page 26 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO RREF_BR DNU DNU REFCLK0Rp REFCLK0Rn GXB_RX_R0n,GXB_REFCLK_R0n GXB_RX_R0p,GXB_REFCLK_R0p GXB_TX_R0p GXB_TX_R0n GXB_RX_R1n,GXB_REFCLK_R1n GXB_RX_R1p,GXB_REFCLK_R1p GXB_TX_R1p GXB_TX_R1n GXB_RX_R2n,GXB_REFCLK_R2n GXB_RX_R2p,GXB_REFCLK_R2p GXB_TX_R2p GXB_TX_R2n GND GND DNU DNU GND GND DNU DNU GND GND DNU DNU GND GND REFCLK2Rp REFCLK2Rn GXB_RX_R6n,GXB_REFCLK_R6n GXB_RX_R6p,GXB_REFCLK_R6p GXB_TX_R6p GXB_TX_R6n GXB_RX_R7n,GXB_REFCLK_R7n GXB_RX_R7p,GXB_REFCLK_R7p GXB_TX_R7p GXB_TX_R7n GXB_RX_R8n,GXB_REFCLK_R8n GXB_RX_R8p,GXB_REFCLK_R8p GXB_TX_R8p GXB_TX_R8n GXB_RX_R9n,GXB_REFCLK_R9n GXB_RX_R9p,GXB_REFCLK_R9p GXB_TX_R9p GXB_TX_R9n GXB_RX_R10n,GXB_REFCLK_R10n GXB_RX_R10p,GXB_REFCLK_R10p GXB_TX_R10p GXB_TX_R10n GXB_RX_R11n,GXB_REFCLK_R11n GXB_RX_R11p,GXB_REFCLK_R11p GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R0 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 GXB_R1 PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DIFFOUT_B149p DIFFOUT_B150n DIFFOUT_B150p DIFFOUT_B151n DIFFOUT_B151p DIFFOUT_B152n DIFFOUT_B152p DIFFOUT_B153n DIFFOUT_B153p DIFFOUT_B154n DIFFOUT_B154p DIFFOUT_B155n DIFFOUT_B155p DIFFOUT_B156n DIFFOUT_B156p DIFFOUT_B157n DIFFOUT_B157p DIFFOUT_B158n DIFFOUT_B158p DIFFOUT_B159n DIFFOUT_B159p DQS9B/CQ9B/CQn9B/QKn9B DQ4B DQ20B DQ20B DQ20B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ20B DQ20B DQ20B DQ9B DQ9B DQ9B DQ4B DQ4B DQ4B DQ21B DQ21B DQ21B DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B DQ21B DQSn21B/QK21B DQS21B/CQ21B/CQn21B/QKn21B DQ10B DQ10B DQ10B DQ4B DQSn4B/QK4B DQS4B/CQ4B/CQn4B/QKn4B DQ21B DQ21B DQ21B DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B DIFFIO_RX_B160n DIFFIO_RX_B160p DIFFIO_TX_B161n DIFFIO_TX_B161p DIFFIO_RX_B162n DIFFIO_RX_B162p DIFFIO_TX_B163n DIFFIO_TX_B163p DIFFIO_RX_B164n DIFFIO_RX_B164p DIFFIO_TX_B165n DIFFIO_TX_B165p DIFFIO_RX_B166n DIFFIO_RX_B166p DIFFIO_TX_B167n DIFFIO_TX_B167p DIFFIO_RX_B168n DIFFIO_RX_B168p DIFFOUT_B160n DIFFOUT_B160p DIFFOUT_B161n DIFFOUT_B161p DIFFOUT_B162n DIFFOUT_B162p DIFFOUT_B163n DIFFOUT_B163p DIFFOUT_B164n DIFFOUT_B164p DIFFOUT_B165n DIFFOUT_B165p DIFFOUT_B166n DIFFOUT_B166p DIFFOUT_B167n DIFFOUT_B167p DIFFOUT_B168n DIFFOUT_B168p AW5 AK9 AK10 AU7 AU8 AN9 AP9 AT8 AR9 AH10 AJ10 AF10 AE11 AK6 AL6 AH6 AJ6 AH9 AJ9 AM6 AN6 AH7 AH8 AJ7 AK7 AL7 AM7 AN8 AP8 AT6 AU6 AR7 AT7 AK8 AL8 AV4 AW4 AN7 AP7 AP6 AR6 AW2 AV3 AW3 AF8 AF7 AU2 AU1 AT3 AT4 AR2 AR1 AP3 AP4 AN2 AN1 AM3 AM4 AL2 AL1 AK3 AK4 AJ2 AJ1 AH3 AH4 AG2 AG1 AF3 AF4 AD9 AD8 AB9 AB8 AE2 AE1 AD3 AD4 AC2 AC1 AB3 AB4 AA2 AA1 Y3 Y4 W2 W1 V3 V4 U2 U1 T3 T4 R2 R1 DQS20B/CQ20B/CQn20B/QKn20B DATA10 DATA11 DATA5 DATA6 DATA12 DATA13 DATA7 DATA8 DATA14 DATA15 DATA9 CLKUSR DIFFIO_RX_B149p DIFFIO_TX_B150n DIFFIO_TX_B150p DIFFIO_RX_B151n DIFFIO_RX_B151p DIFFIO_TX_B152n DIFFIO_TX_B152p DIFFIO_RX_B153n DIFFIO_RX_B153p DIFFIO_TX_B154n DIFFIO_TX_B154p DIFFIO_RX_B155n DIFFIO_RX_B155p DIFFIO_TX_B156n DIFFIO_TX_B156p DIFFIO_RX_B157n DIFFIO_RX_B157p DIFFIO_TX_B158n DIFFIO_TX_B158p DIFFIO_RX_B159n DIFFIO_RX_B159p DQ21B DQ21B DQ21B DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B DQ22B DQ22B DQ22B DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B DQ22B DQSn22B/QK22B DQS22B/CQ22B/CQn22B/QKn22B DQ10B DQSn10B/QK10B DQS10B/CQ10B/CQn10B/QKn10B DQ4B DQ4B DQ4B DQ22B DQ22B DQ22B DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B DQ22B DQ22B DQ22B DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B VREFB4AN0 CLK11n CLK11p FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB0 FPLL_BR_CLKOUT3,FPLL_BR_FBn FPLL_BR_CLKOUT2,FPLL_BR_FBp,FPLL_BR_FB1 CLK10n CLK10p CLK9n CLK9p RZQ_1 CLK8n CLK8p Pin List GF40 DDR3/DDR2 hard memory PHY (3) Page 27 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 GXB_TX_R11p GXB_TX_R11n REFCLK3Rp REFCLK3Rn DNU GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_R1 GXB_R1 GXB_R1 GXB_R1 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function CLK12p CLK12n RZQ_5 CLK13p CLK13n CLK14p CLK14n FPLL_TR_CLKOUT2,FPLL_TR_FBp,FPLL_TR_FB1 FPLL_TR_CLKOUT3,FPLL_TR_FBn FPLL_TR_CLKOUT0,FPLL_TR_CLKOUTp,FPLL_TR_FB0 FPLL_TR_CLKOUT1,FPLL_TR_CLKOUTn CLK15p CLK15n Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_RX_T1p DIFFIO_RX_T1n DIFFIO_TX_T2p DIFFIO_TX_T2n DIFFIO_RX_T3p DIFFIO_RX_T3n DIFFIO_TX_T4p DIFFIO_TX_T4n DIFFIO_RX_T5p DIFFIO_RX_T5n DIFFIO_TX_T6p DIFFIO_TX_T6n DIFFIO_RX_T7p DIFFIO_RX_T7n DIFFIO_TX_T8p DIFFIO_TX_T8n DIFFIO_RX_T9p DIFFIO_RX_T9n DIFFOUT_T1p DIFFOUT_T1n DIFFOUT_T2p DIFFOUT_T2n DIFFOUT_T3p DIFFOUT_T3n DIFFOUT_T4p DIFFOUT_T4n DIFFOUT_T5p DIFFOUT_T5n DIFFOUT_T6p DIFFOUT_T6n DIFFOUT_T7p DIFFOUT_T7n DIFFOUT_T8p DIFFOUT_T8n DIFFOUT_T9p DIFFOUT_T9n DIFFIO_RX_T10p DIFFIO_RX_T10n DIFFIO_TX_T11p DIFFIO_TX_T11n DIFFIO_RX_T12p DIFFIO_RX_T12n DIFFIO_TX_T13p DIFFIO_TX_T13n DIFFIO_RX_T14p DIFFIO_RX_T14n DIFFIO_TX_T15p DIFFIO_TX_T15n DIFFIO_RX_T16p DIFFIO_RX_T16n DIFFIO_TX_T17p DIFFIO_TX_T17n DIFFIO_RX_T18p DIFFIO_RX_T18n DIFFIO_TX_T19p DIFFIO_TX_T19n DIFFIO_RX_T20p DIFFIO_RX_T20n DIFFIO_TX_T21p DIFFIO_TX_T21n DIFFIO_RX_T22p DIFFIO_RX_T22n DIFFIO_TX_T23p DIFFIO_TX_T23n DIFFIO_RX_T24p DIFFIO_RX_T24n DIFFIO_TX_T25p DIFFIO_TX_T25n DIFFIO_RX_T26p DIFFIO_RX_T26n DIFFIO_TX_T27p DIFFIO_TX_T27n DIFFIO_RX_T28p DIFFIO_RX_T28n DIFFIO_TX_T29p DIFFIO_TX_T29n DIFFIO_RX_T30p DIFFIO_RX_T30n DIFFIO_TX_T31p DIFFIO_TX_T31n DIFFIO_RX_T32p DIFFIO_RX_T32n DIFFOUT_T10p DIFFOUT_T10n DIFFOUT_T11p DIFFOUT_T11n DIFFOUT_T12p DIFFOUT_T12n DIFFOUT_T13p DIFFOUT_T13n DIFFOUT_T14p DIFFOUT_T14n DIFFOUT_T15p DIFFOUT_T15n DIFFOUT_T16p DIFFOUT_T16n DIFFOUT_T17p DIFFOUT_T17n DIFFOUT_T18p DIFFOUT_T18n DIFFOUT_T19p DIFFOUT_T19n DIFFOUT_T20p DIFFOUT_T20n DIFFOUT_T21p DIFFOUT_T21n DIFFOUT_T22p DIFFOUT_T22n DIFFOUT_T23p DIFFOUT_T23n DIFFOUT_T24p DIFFOUT_T24n DIFFOUT_T25p DIFFOUT_T25n DIFFOUT_T26p DIFFOUT_T26n DIFFOUT_T27p DIFFOUT_T27n DIFFOUT_T28p DIFFOUT_T28n DIFFOUT_T29p DIFFOUT_T29n DIFFOUT_T30p DIFFOUT_T30n DIFFOUT_T31p DIFFOUT_T31n DIFFOUT_T32p DIFFOUT_T32n DIFFIO_RX_T33p DIFFIO_RX_T33n DIFFIO_TX_T34p DIFFIO_TX_T34n DIFFIO_RX_T35p DIFFIO_RX_T35n DIFFIO_TX_T36p DIFFIO_TX_T36n DIFFIO_RX_T37p DIFFIO_RX_T37n DIFFIO_TX_T38p DIFFIO_TX_T38n DIFFIO_RX_T39p DIFFIO_RX_T39n DIFFIO_TX_T40p DIFFIO_TX_T40n DIFFIO_RX_T41p DIFFIO_RX_T41n DIFFIO_TX_T42p DIFFIO_TX_T42n DIFFIO_RX_T43p DIFFIO_RX_T43n DIFFOUT_T33p DIFFOUT_T33n DIFFOUT_T34p DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T35n DIFFOUT_T36p DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T37n DIFFOUT_T38p DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T39n DIFFOUT_T40p DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T41n DIFFOUT_T42p DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T43n VREFB7AN0 DEV_OE DEV_CLRn nPERSTL0 CvP_CONFDONE CRC_ERROR PR_DONE PR_REQUEST INIT_DONE nCEO PR_ERROR PR_READY VREFB7BN0 Pin List GF40 F1517 P3 P4 Y9 Y8 C5 N6 C6 D6 F6 G6 A6 B6 F7 G7 E6 E7 C7 D7 F8 G8 J8 K8 H6 J6 K7 J7 K6 L6 M8 N9 P10 P9 L7 M6 M7 N7 L10 M10 D9 E9 F9 G9 C8 D8 K9 L9 A7 B7 B9 C9 A9 A8 H9 J9 E10 F10 N10 M11 B10 C10 H10 J10 P12 R12 R11 T11 A11 A10 J11 K11 M12 N12 F11 G11 C11 D11 K12 L12 D12 E12 F12 G12 P13 R13 H12 J12 B12 C12 M13 N13 A13 A12 J13 K13 D13 E13 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T/CQ1T/CQn1T/QKn1T DQSn1T/QK1T DQ1T DQS1T/CQ1T/CQn1T/QKn1T DQSn1T/QK1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS2T/CQ2T/CQn2T/QKn2T DQSn2T/QK2T DQ2T DQ1T DQ1T DQ1T DQS1T/CQ1T/CQn1T/QKn1T DQSn1T/QK1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQS3T/CQ3T/CQn3T/QKn3T DQSn3T/QK3T DQ3T DQS2T/CQ2T/CQn2T/QKn2T DQSn2T/QK2T DQ2T DQ1T DQ1T DQ1T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ5_7B_0 DQ5_7B_1 DQ5_7B_2 DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ5_7B_3 DQ5_7B_4 DQ5_7B_5 DQS4T/CQ4T/CQn4T/QKn4T DQSn4T/QK4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQS5_7B DQS#5_7B DM5_7B DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ5_7B_6 DQ5_7B_7 DQ5_7B_8 DQ5T DQ5T DQ5T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ4_7B_0 DQ4_7B_1 DQ4_7B_2 DQ5T DQ5T DQ5T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ4_7B_3 DQ4_7B_4 DQ4_7B_5 DQS5T/CQ5T/CQn5T/QKn5T DQSn5T/QK5T DQ5T DQS3T/CQ3T/CQn3T/QKn3T DQSn3T/QK3T DQ3T DQ2T DQ2T DQ2T DQS4_7B DQS#4_7B DM4_7B DQ5T DQ5T DQ5T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ4_7B_6 DQ4_7B_7 DQ4_7B_8 DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ3_7B_0 DQ3_7B_1 DQ3_7B_2 DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ3_7B_3 DQ3_7B_4 DQ3_7B_5 DQS6T/CQ6T/CQn6T/QKn6T DQSn6T/QK6T DQ3T DQ3T DQS2T/CQ2T/CQn2T/QKn2T DQSn2T/QK2T DQS3_7B DQS#3_7B Page 28 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 7B 7B 7B 7B 7B 7B 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 VREFB7DN0 8D 8D 8D 8D 8D 8D 8D VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCA_FPLL VCCD_FPLL DNU IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DIFFIO_TX_T44p DIFFIO_TX_T44n DIFFIO_RX_T45p DIFFIO_RX_T45n DIFFIO_TX_T46p DIFFIO_TX_T46n DIFFIO_RX_T47p DIFFIO_RX_T47n DIFFIO_TX_T48p DIFFIO_TX_T48n DIFFIO_RX_T49p DIFFIO_RX_T49n DIFFIO_TX_T50p DIFFIO_TX_T50n DIFFIO_RX_T51p DIFFIO_RX_T51n DIFFIO_TX_T52p DIFFIO_TX_T52n DIFFIO_RX_T53p DIFFIO_RX_T53n DIFFIO_TX_T54p DIFFIO_TX_T54n DIFFIO_RX_T55p DIFFIO_RX_T55n DIFFOUT_T44p DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T45n DIFFOUT_T46p DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T47n DIFFOUT_T48p DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T55n DQ6T DQ3T DQ2T DDR3/DDR2 hard memory PHY (3) DM3_7B DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ2T DQ2T DQ2T DQ3_7B_6 DQ3_7B_7 DQ3_7B_8 DQ7T DQ7T DQ7T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ2_7C_0 DQ2_7C_1 DQ2_7C_2 DQ7T DQ7T DQ7T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ2_7C_3 DQ2_7C_4 DQ2_7C_5 DQS7T/CQ7T/CQn7T/QKn7T DQSn7T/QK7T DQ7T DQS4T/CQ4T/CQn4T/QKn4T DQSn4T/QK4T DQ4T DQ2T DQ2T DQ2T DQS2_7C DQS#2_7C DM2_7C DQ7T DQ7T DQ7T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ2_7C_6 DQ2_7C_7 DQ2_7C_8 DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1_7C_0 DQ1_7C_1 DQ1_7C_2 DIFFIO_RX_T56p DIFFIO_RX_T56n DIFFIO_TX_T57p DIFFIO_TX_T57n DIFFIO_RX_T58p DIFFIO_RX_T58n DIFFIO_TX_T59p DIFFIO_TX_T59n DIFFIO_RX_T60p DIFFIO_RX_T60n DIFFIO_TX_T61p DIFFIO_TX_T61n DIFFIO_RX_T62p DIFFIO_RX_T62n DIFFIO_TX_T63p DIFFIO_TX_T63n DIFFIO_RX_T64p DIFFIO_RX_T64n DIFFIO_TX_T65p DIFFIO_TX_T65n DIFFIO_RX_T66p DIFFIO_RX_T66n DIFFIO_TX_T67p DIFFIO_TX_T67n DIFFIO_RX_T68p DIFFIO_RX_T68n DIFFIO_TX_T69p DIFFIO_TX_T69n DIFFIO_RX_T70p DIFFIO_RX_T70n DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n DIFFOUT_T65p DIFFOUT_T65n DIFFOUT_T66p DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T67n DIFFOUT_T68p DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T69n DIFFOUT_T70p DIFFOUT_T70n DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ1_7C_3 DQ1_7C_4 DQ1_7C_5 DQS8T/CQ8T/CQn8T/QKn8T DQSn8T/QK8T DQ8T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQS1_7C DQS#1_7C DM1_7C DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ9T DQ9T DQ9T DQ5T DQ5T DQ5T DQ9T DQ9T DQ9T DQ5T DQ5T DQ5T DQS9T/CQ9T/CQn9T/QKn9T DQSn9T/QK9T DQ9T DQS5T/CQ5T/CQn5T/QKn5T DQSn5T/QK5T DQ5T DQ9T DQ9T DQ9T DQ5T DQ5T DQ5T DQ10T DQ10T DQ10T DQ5T DQ5T DQ5T DQ1_7C_6 DQ1_7C_7 DQ1_7C_8 RESET#_7D CK_7D CK#_7D CKE_7D_0 CKE_7D_1 A_7D_0 A_7D_1 A_7D_2 A_7D_3 A_7D_4 A_7D_5 A_7D_6 A_7D_7 A_7D_8 A_7D_9 A_7D_10 A_7D_11 A_7D_12 A_7D_13 A_7D_14 DIFFIO_RX_T71p DIFFIO_RX_T71n DIFFIO_TX_T72p DIFFIO_TX_T72n DIFFIO_RX_T73p DIFFIO_RX_T73n DIFFIO_TX_T74p DIFFIO_TX_T74n DIFFIO_RX_T75p DIFFIO_RX_T75n DIFFIO_TX_T76p DIFFIO_TX_T76n DIFFIO_RX_T77p DIFFIO_RX_T77n DIFFIO_TX_T78p DIFFIO_TX_T78n DIFFIO_RX_T79p DIFFIO_RX_T79n DIFFIO_TX_T80p DIFFIO_TX_T80n DIFFIO_RX_T81p DIFFIO_RX_T81n DIFFIO_TX_T82p DIFFIO_TX_T82n DIFFIO_RX_T83p DIFFIO_RX_T83n DIFFIO_TX_T84p DIFFIO_TX_T84n DIFFOUT_T71p DIFFOUT_T71n DIFFOUT_T72p DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T73n DIFFOUT_T74p DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T75n DIFFOUT_T76p DIFFOUT_T76n DIFFOUT_T77p DIFFOUT_T77n DIFFOUT_T78p DIFFOUT_T78n DIFFOUT_T79p DIFFOUT_T79n DIFFOUT_T80p DIFFOUT_T80n DIFFOUT_T81p DIFFOUT_T81n DIFFOUT_T82p DIFFOUT_T82n DIFFOUT_T83p DIFFOUT_T83n DIFFOUT_T84p DIFFOUT_T84n DQ10T DQ10T DQ10T DQ5T DQ5T DQ5T DQS10T/CQ10T/CQn10T/QKn10T DQSn10T/QK10T DQ10T DQ5T DQ5T DQ5T DQ10T DQ10T DQ10T DQ5T DQ5T DQ5T DIFFIO_RX_T85p DIFFIO_RX_T85n DIFFIO_TX_T86p DIFFIO_TX_T86n DIFFIO_RX_T87p DIFFIO_RX_T87n DIFFIO_TX_T88p DIFFOUT_T85p DIFFOUT_T85n DIFFOUT_T86p DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T87n DIFFOUT_T88p A14 B13 C14 D14 G13 H13 R14 T14 M14 N14 F14 G14 L15 M15 R15 T15 N15 P15 E15 F15 J14 K14 P16 R16 C15 D15 M16 N16 H15 J15 G16 H16 A15 B15 D16 E16 J16 K16 N18 P18 M17 N17 B16 C16 J17 K17 F17 G17 R17 T17 C17 D17 K18 L18 R19 T19 R18 T18 E18 F18 H18 J18 N19 P19 B18 C18 A17 A16 L19 M19 F19 G19 J19 K19 C19 D19 J20 K20 A18 A19 R20 T20 F20 G20 M20 N20 V20 V19 P21 C20 D20 M21 N21 G21 H21 D21 VREFB7CN0 VREFB7DN0 CLK19p CLK19n CLK18p CLK18n Pin List GF40 BA_7D_0 BA_7D_1 BA_7D_2 RAS#_7D CAS#_7D WE#_7D ODT_7D_0 ODT_7D_1 A_7D_15 CS#_7D_0 CS#_7D_1 DQ11T DQ11T DQ11T DQ11T DQ11T DQ11T DQS11T/CQ11T/CQn11T/QKn11T DQSn11T/QK11T DQ11T DQ11T DQ11T DQ11T DQ12T DQ12T DQ12T DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ12T DQ12T DQ12T DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T Page 29 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8B 8B 8B 8B 8B 8B 8B VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8DN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) FPLL_TC_CLKOUT2,FPLL_TC_FBp,FPLL_TC_FB1 FPLL_TC_CLKOUT3,FPLL_TC_FBn FPLL_TC_CLKOUT0,FPLL_TC_CLKOUTp,FPLL_TC_FB0 FPLL_TC_CLKOUT1,FPLL_TC_CLKOUTn CLK17p CLK17n CLK16p CLK16n Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1517 DIFFIO_TX_T88n DIFFIO_RX_T89p DIFFIO_RX_T89n DIFFIO_TX_T90p DIFFIO_TX_T90n DIFFIO_RX_T91p DIFFIO_RX_T91n DIFFIO_TX_T92p DIFFIO_TX_T92n DIFFIO_RX_T93p DIFFIO_RX_T93n DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T89n DIFFOUT_T90p DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T91n DIFFOUT_T92p DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T93n DIFFIO_RX_T94p DIFFIO_RX_T94n DIFFIO_TX_T95p DIFFIO_TX_T95n DIFFIO_RX_T96p DIFFIO_RX_T96n DIFFIO_TX_T97p DIFFIO_TX_T97n DIFFIO_RX_T98p DIFFIO_RX_T98n DIFFIO_TX_T99p DIFFIO_TX_T99n DIFFIO_RX_T100p DIFFIO_RX_T100n DIFFIO_TX_T101p DIFFIO_TX_T101n DIFFIO_RX_T102p DIFFIO_RX_T102n DIFFIO_TX_T103p DIFFIO_TX_T103n DIFFIO_RX_T104p DIFFIO_RX_T104n DIFFIO_TX_T105p DIFFIO_TX_T105n DIFFIO_RX_T106p DIFFIO_RX_T106n DIFFIO_TX_T107p DIFFIO_TX_T107n DIFFIO_RX_T108p DIFFIO_RX_T108n DIFFIO_TX_T109p DIFFIO_TX_T109n DIFFIO_RX_T110p DIFFIO_RX_T110n DIFFIO_TX_T111p DIFFIO_TX_T111n DIFFIO_RX_T112p DIFFIO_RX_T112n DIFFIO_TX_T113p DIFFIO_TX_T113n DIFFIO_RX_T114p DIFFIO_RX_T114n DIFFIO_TX_T115p DIFFIO_TX_T115n DIFFIO_RX_T116p DIFFIO_RX_T116n DIFFOUT_T94p DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T95n DIFFOUT_T96p DIFFOUT_T96n DIFFOUT_T97p DIFFOUT_T97n DIFFOUT_T98p DIFFOUT_T98n DIFFOUT_T99p DIFFOUT_T99n DIFFOUT_T100p DIFFOUT_T100n DIFFOUT_T101p DIFFOUT_T101n DIFFOUT_T102p DIFFOUT_T102n DIFFOUT_T103p DIFFOUT_T103n DIFFOUT_T104p DIFFOUT_T104n DIFFOUT_T105p DIFFOUT_T105n DIFFOUT_T106p DIFFOUT_T106n DIFFOUT_T107p DIFFOUT_T107n DIFFOUT_T108p DIFFOUT_T108n DIFFOUT_T109p DIFFOUT_T109n DIFFOUT_T110p DIFFOUT_T110n DIFFOUT_T111p DIFFOUT_T111n DIFFOUT_T112p DIFFOUT_T112n DIFFOUT_T113p DIFFOUT_T113n DIFFOUT_T114p DIFFOUT_T114n DIFFOUT_T115p DIFFOUT_T115n DIFFOUT_T116p DIFFOUT_T116n DIFFIO_RX_T117p DIFFIO_RX_T117n DIFFIO_TX_T118p DIFFIO_TX_T118n DIFFIO_RX_T119p DIFFIO_RX_T119n DIFFIO_TX_T120p DIFFIO_TX_T120n DIFFIO_RX_T121p DIFFIO_RX_T121n DIFFIO_TX_T122p DIFFIO_TX_T122n DIFFIO_RX_T123p DIFFIO_RX_T123n DIFFIO_TX_T124p DIFFIO_TX_T124n DIFFIO_RX_T125p DIFFIO_RX_T125n DIFFIO_TX_T126p DIFFIO_TX_T126n DIFFIO_RX_T127p DIFFIO_RX_T127n DIFFIO_TX_T128p DIFFIO_TX_T128n DIFFIO_RX_T129p DIFFIO_RX_T129n DIFFIO_TX_T130p DIFFIO_TX_T130n DIFFIO_RX_T131p DIFFIO_RX_T131n DIFFIO_TX_T132p DIFFIO_TX_T132n DIFFIO_RX_T133p DIFFIO_RX_T133n DIFFIO_TX_T134p DIFFOUT_T117p DIFFOUT_T117n DIFFOUT_T118p DIFFOUT_T118n DIFFOUT_T119p DIFFOUT_T119n DIFFOUT_T120p DIFFOUT_T120n DIFFOUT_T121p DIFFOUT_T121n DIFFOUT_T122p DIFFOUT_T122n DIFFOUT_T123p DIFFOUT_T123n DIFFOUT_T124p DIFFOUT_T124n DIFFOUT_T125p DIFFOUT_T125n DIFFOUT_T126p DIFFOUT_T126n DIFFOUT_T127p DIFFOUT_T127n DIFFOUT_T128p DIFFOUT_T128n DIFFOUT_T129p DIFFOUT_T129n DIFFOUT_T130p DIFFOUT_T130n DIFFOUT_T131p DIFFOUT_T131n DIFFOUT_T132p DIFFOUT_T132n DIFFOUT_T133p DIFFOUT_T133n DIFFOUT_T134p E21 A20 B21 J21 K21 A22 A21 R21 T21 B22 C22 J22 H22 E22 F22 A23 A24 C23 D23 L22 M22 N22 P22 R22 T22 F23 G23 R23 T23 B24 C24 M23 N23 D24 E24 J23 K23 F24 G24 H24 J24 T26 T25 G25 H25 N24 P24 R24 T24 A25 B25 K24 L24 D25 E25 P25 R25 C26 D26 K25 L25 R26 T27 A26 A27 M26 N26 J26 K26 F26 G26 M25 N25 P27 R27 H27 J27 B27 C27 E27 F27 R28 T28 K27 L27 M27 N27 N28 P28 L28 M28 H28 J28 C28 D28 F28 VREFB8DN0 VREFB8CN0 Pin List GF40 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DQS12T/CQ12T/CQn12T/QKn12T DQSn12T/QK12T DQ12T DQS6T/CQ6T/CQn6T/QKn6T DQSn6T/QK6T DQ6T DQ3T DQ3T DQ3T DQ12T DQ12T DQ12T DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ13T DQ13T DQ13T DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ13T DQ13T DQ13T DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQS13T/CQ13T/CQn13T/QKn13T DQSn13T/QK13T DQ13T DQ6T DQ6T DQ6T DQS3T/CQ3T/CQn3T/QKn3T DQSn3T/QK3T DQ3T DQ13T DQ13T DQ13T DQ6T DQ6T DQ6T DQ3T DQ3T DQ3T DQ14T DQ14T DQ14T DQ7T DQ7T DQ7T DQ3T DQ3T DQ3T DQ14T DQ14T DQ14T DQ7T DQ7T DQ7T DQ3T DQ3T DQ3T DQS14T/CQ14T/CQn14T/QKn14T DQSn14T/QK14T DQ14T DQS7T/CQ7T/CQn7T/QKn7T DQSn7T/QK7T DQ7T DQ3T DQ3T DQ3T DQ14T DQ14T DQ14T DQ7T DQ7T DQ7T DQ3T DQ3T DQ3T DQ15T DQ15T DQ15T DQ7T DQ7T DQ7T DQ3T DQ3T DQ3T DQ15T DQ15T DQ15T DQ7T DQ7T DQ7T DQ3T DQ3T DQ3T DQS15T/CQ15T/CQn15T/QKn15T DQSn15T/QK15T DQ15T DQ7T DQ7T DQ7T DQ3T DQ3T DQ3T DQ15T DQ15T DQ15T DQ7T DQ7T DQ7T DQ3T DQ3T DQ3T DQ16T DQ16T DQ16T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQ16T DQ16T DQ16T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQS16T/CQ16T/CQn16T/QKn16T DQSn16T/QK16T DQ16T DQS8T/CQ8T/CQn8T/QKn8T DQSn8T/QK8T DQ8T DQ4T DQ4T DQ4T DQ16T DQ16T DQ16T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQ17T DQ17T DQ17T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQ17T DQ17T DQ17T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQS17T/CQ17T/CQn17T/QKn17T DQSn17T/QK17T DQ17T DQ8T DQ8T DQ8T DQS4T/CQ4T/CQn4T/QKn4T DQSn4T/QK4T DQ4T DQ17T DQ17T DQ17T DQ8T DQ8T DQ8T DQ4T DQ4T DQ4T DQ18T DQ18T DQ18T DQ9T DQ9T DQ9T DQ4T DQ4T DQ4T DQ18T DQ18T DQ18T DQ9T DQ9T DQ9T DQ4T DQ4T DQ4T DDR3/DDR2 hard memory PHY (3) Page 30 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Bank Number VREF PinName/Function (2) 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 CONF_DONE nSTATUS nCE nCONFIG GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1517 DIFFIO_TX_T134n DIFFIO_RX_T135p DIFFIO_RX_T135n DIFFIO_TX_T136p DIFFIO_TX_T136n DIFFIO_RX_T137p DIFFIO_RX_T137n DIFFIO_TX_T138p DIFFIO_TX_T138n DIFFIO_RX_T139p DIFFIO_RX_T139n DIFFOUT_T134n DIFFOUT_T135p DIFFOUT_T135n DIFFOUT_T136p DIFFOUT_T136n DIFFOUT_T137p DIFFOUT_T137n DIFFOUT_T138p DIFFOUT_T138n DIFFOUT_T139p DIFFOUT_T139n DIFFIO_RX_T140p DIFFIO_RX_T140n DIFFIO_TX_T141p DIFFIO_TX_T141n DIFFIO_RX_T142p DIFFIO_RX_T142n DIFFIO_TX_T143p DIFFIO_TX_T143n DIFFIO_RX_T144p DIFFIO_RX_T144n DIFFIO_TX_T145p DIFFIO_TX_T145n DIFFIO_RX_T146p DIFFIO_RX_T146n DIFFIO_TX_T147p DIFFIO_TX_T147n DIFFIO_RX_T148p DIFFIO_RX_T148n DIFFIO_TX_T149p DIFFIO_TX_T149n DIFFIO_RX_T150p DIFFIO_RX_T150n DIFFIO_TX_T151p DIFFIO_TX_T151n DIFFIO_RX_T152p DIFFIO_RX_T152n DIFFIO_TX_T153p DIFFIO_TX_T153n DIFFIO_RX_T154p DIFFIO_RX_T154n DIFFIO_TX_T155p DIFFIO_TX_T155n DIFFIO_RX_T156p DIFFIO_RX_T156n DIFFIO_TX_T157p DIFFIO_TX_T157n DIFFIO_RX_T158p DIFFIO_RX_T158n DIFFIO_TX_T159p DIFFIO_TX_T159n DIFFIO_RX_T160p DIFFIO_RX_T160n DIFFIO_TX_T161p DIFFIO_TX_T161n DIFFIO_RX_T162p DIFFIO_RX_T162n DIFFOUT_T140p DIFFOUT_T140n DIFFOUT_T141p DIFFOUT_T141n DIFFOUT_T142p DIFFOUT_T142n DIFFOUT_T143p DIFFOUT_T143n DIFFOUT_T144p DIFFOUT_T144n DIFFOUT_T145p DIFFOUT_T145n DIFFOUT_T146p DIFFOUT_T146n DIFFOUT_T147p DIFFOUT_T147n DIFFOUT_T148p DIFFOUT_T148n DIFFOUT_T149p DIFFOUT_T149n DIFFOUT_T150p DIFFOUT_T150n DIFFOUT_T151p DIFFOUT_T151n DIFFOUT_T152p DIFFOUT_T152n DIFFOUT_T153p DIFFOUT_T153n DIFFOUT_T154p DIFFOUT_T154n DIFFOUT_T155p DIFFOUT_T155n DIFFOUT_T156p DIFFOUT_T156n DIFFOUT_T157p DIFFOUT_T157n DIFFOUT_T158p DIFFOUT_T158n DIFFOUT_T159p DIFFOUT_T159n DIFFOUT_T160p DIFFOUT_T160n DIFFOUT_T161p DIFFOUT_T161n DIFFOUT_T162p DIFFOUT_T162n DIFFIO_RX_T163p DIFFIO_RX_T163n DIFFIO_TX_T164p DIFFIO_TX_T164n DIFFIO_RX_T165p DIFFIO_RX_T165n DIFFIO_TX_T166p DIFFIO_TX_T166n DIFFIO_RX_T167p DIFFIO_RX_T167n DIFFIO_TX_T168p DIFFIO_TX_T168n DIFFOUT_T163p DIFFOUT_T163n DIFFOUT_T164p DIFFOUT_T164n DIFFOUT_T165p DIFFOUT_T165n DIFFOUT_T166p DIFFOUT_T166n DIFFOUT_T167p DIFFOUT_T167n DIFFOUT_T168p DIFFOUT_T168n G28 R29 T29 J29 K29 M29 N29 F29 G29 B28 C29 R30 R31 A29 A28 L30 M30 N30 P30 J30 K30 D30 D29 F30 G30 B30 C30 E31 F31 B31 A30 A31 A32 A33 B33 H31 J31 C31 D31 C32 D32 N31 P31 J32 K32 M32 N32 J34 K34 L33 M33 L31 M31 N34 N33 L34 M34 E34 F34 J33 H33 B34 A35 C33 D33 G34 H34 F32 G32 C34 D34 E33 F33 H35 A34 D35 A37 P34 K35 F35 M35 A36 P35 AA33 AA35 AA38 AA39 AB31 AB32 AB34 AB36 AB37 AC33 AC38 AC39 AD30 VREFB8BN0 CLK23p CLK23n CLK22p CLK22n VREFB8AN0 FPLL_TL_CLKOUT2,FPLL_TL_FBp,FPLL_TL_FB1 FPLL_TL_CLKOUT3,FPLL_TL_FBn FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB0 FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn CLK21p CLK21n CLK20p CLK20n RZQ_6 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 CONF_DONE nSTATUS nCE nCONFIG Pin List GF40 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DQS18T/CQ18T/CQn18T/QKn18T DQSn18T/QK18T DQ18T DQS9T/CQ9T/CQn9T/QKn9T DQSn9T/QK9T DQ9T DQ4T DQ4T DQ4T DQ18T DQ18T DQ18T DQ9T DQ9T DQ9T DQ4T DQ4T DQ4T DQ19T DQ19T DQ19T DQ9T DQ9T DQ9T DQ4T DQ4T DQ4T DQ19T DQ19T DQ19T DQ9T DQ9T DQ9T DQ4T DQ4T DQ4T DQS19T/CQ19T/CQn19T/QKn19T DQSn19T/QK19T DQ19T DQ9T DQ9T DQ9T DQ4T DQ4T DQ4T DQ19T DQ19T DQ19T DQ9T DQ9T DQ9T DQ4T DQ4T DQ4T DQ20T DQ20T DQ20T DQ10T DQ10T DQ10T DQ20T DQ20T DQ20T DQ10T DQ10T DQ10T DQS20T/CQ20T/CQn20T/QKn20T DQSn20T/QK20T DQ20T DQS10T/CQ10T/CQn10T/QKn10T DQSn10T/QK10T DQ10T DQ20T DQ20T DQ20T DQ10T DQ10T DQ10T DQ21T DQ21T DQ21T DQ10T DQ10T DQ10T DQ21T DQ21T DQ21T DQ10T DQ10T DQ10T DQS21T/CQ21T/CQn21T/QKn21T DQSn21T/QK21T DQ21T DQ10T DQ10T DQ10T DQ21T DQ21T DQ21T DQ10T DQ10T DQ10T DDR3/DDR2 hard memory PHY (3) DQ22T DQ22T DQ22T DQ22T DQ22T DQ22T DQS22T/CQ22T/CQn22T/QKn22T DQSn22T/QK22T DQ22T DQ22T DQ22T DQ22T Page 31 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) AD32 AD36 AD37 AE33 AE35 AE38 AE39 AF31 AF32 AF34 AF36 AF37 AG38 AG39 AH32 AH33 AH34 AH35 AH36 AH37 AJ35 AJ38 AJ39 AK36 AK37 AL35 AL38 AL39 AM36 AM37 AN35 AN38 AN39 AP36 AP37 AR35 AR38 AR39 AT36 AT37 AU35 AU38 AU39 AV35 AV36 AV37 AV38 AV39 AW35 AW38 B36 B37 C35 C38 C39 D36 D37 E35 E38 E39 F36 F37 G35 G38 G39 H36 H37 J35 J38 J39 K36 K37 L35 L38 L39 M36 M37 N35 N38 N39 P36 P37 R34 R38 R39 T32 T36 T37 U33 U35 U38 U39 V32 V34 V36 V37 Pin List GF40 Page 32 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) W33 W38 W39 Y31 Y32 Y36 Y37 A2 A3 A4 A5 AA3 AA4 AA6 AA8 AB1 AB2 AB7 AC3 AC4 AC8 AD1 AD10 AD2 AD5 AD7 AE3 AE4 AE6 AE8 AF1 AF2 AF9 AG3 AG4 AG5 AG6 AG7 AG8 AH1 AH2 AH5 AJ3 AJ4 AK1 AK2 AK5 AL3 AL4 AM1 AM2 AM5 AN3 AN4 AP1 AP2 AP5 AR3 AR4 AT1 AT2 AT5 AU3 AU4 AV1 AV2 B1 B2 B5 C3 C4 D1 D2 D5 E3 E4 F1 F2 F5 G3 G4 H1 H2 H5 J3 J4 K1 K2 K5 L3 L4 M1 M2 M5 N3 N4 Pin List GF40 Page 33 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCBAT VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCA_GXBL0 VCCA_GXBR0 VCCA_GXBL1 VCCA_GXBR1 VCCH_GXBL0 VCCH_GXBR0 VCCH_GXBL1 VCCH_GXBR1 VCCL_GXBL0 VCCL_GXBL0 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBL1 VCCL_GXBL1 VCCL_GXBR1 VCCL_GXBR1 VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCT_GXBL0 VCCT_GXBL0 VCCT_GXBR0 VCCT_GXBR0 VCCT_GXBL1 VCCT_GXBL1 VCCT_GXBR1 VCCT_GXBR1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) N5 P1 P2 P6 P7 R3 R4 R8 T1 T10 T2 T5 T7 U3 U4 U6 U8 V1 V2 V7 W3 W4 W8 Y1 Y2 Y5 Y7 AA21 AA25 AB15 U16 V13 V22 V25 V27 Y13 Y27 AC30 AC9 Y30 AA9 R33 AB14 AB26 U14 U28 AD31 AE9 W30 W9 AF33 AE7 AB33 AA7 AD33 AC7 Y33 W7 AD34 AD35 AC5 AC6 Y34 Y35 W5 W6 AC34 AC35 AG34 AG35 R35 AB5 AB6 AF5 AF6 P5 AE34 AF35 AD6 AE5 AA34 AB35 AA5 Y6 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA24 AA26 AB11 AB17 U10 Pin List GF40 Page 34 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3C VCCIO3C VCCIO3C VCCIO3C VCCIO3C VCCIO3C VCCIO3D VCCIO3D VCCIO3D VCCIO3D VCCIO3D VCCIO3D VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4C VCCIO4C VCCIO4C VCCIO4C VCCIO4D VCCIO4D VCCIO4D VCCIO4D VCCIO4D VCCIO4D VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7B VCCIO7B VCCIO7B VCCIO7B VCCIO7B VCCIO7B VCCIO7C VCCIO7C VCCIO7C VCCIO7C VCCIO7D VCCIO7D VCCIO7D VCCIO7D VCCIO7D VCCIO7D VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) U12 V11 V15 V17 V23 V29 W10 W12 W14 W16 W18 W20 W22 W24 W26 W28 Y11 Y15 Y17 Y19 Y23 Y25 Y29 Y21 AH29 AJ30 AK35 AM30 AP35 AT35 AK28 AL27 AN28 AT28 AJ24 AL25 AM24 AP25 AR24 AU25 AJ22 AL21 AM22 AP21 AR22 AU21 AG10 AJ5 AL5 AN5 AR5 AU5 AK13 AM12 AN10 AN13 AR12 AT10 AJ15 AM15 AR15 AV15 AJ19 AK18 AM19 AN18 AR19 AT18 E5 G5 H7 J5 L5 M9 C13 D10 F13 G10 K10 L13 F16 G15 K15 L16 B19 D18 E19 G18 H19 M18 B35 G31 G33 K31 K33 P33 Pin List GF40 Page 35 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCIO8B VCCIO8B VCCIO8B VCCIO8B VCCIO8C VCCIO8C VCCIO8C VCCIO8C VCCIO8C VCCIO8C VCCIO8D VCCIO8D VCCIO8D VCCIO8D VCCIO8D VCCIO8D VCCPD3 VCCPD3 VCCPD3 VCCPD3 VCCPD3 VCCPD3 VCCPD3 VCCPD4A VCCPD4A VCCPD4BCD VCCPD4BCD VCCPD4BCD VCCPD4BCD VCCPD4BCD VCCPD7A VCCPD7A VCCPD7BCD VCCPD7BCD VCCPD7BCD VCCPD7BCD VCCPD7BCD VCCPD8 VCCPD8 VCCPD8 VCCPD8 VCCPD8 VCCPD8 VCCPD8 VCCPGM VCCPGM GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) E28 E30 H30 K28 C25 D27 F25 G27 J25 M24 C21 D22 F21 G22 K22 L21 AA27 AA28 AA29 AB22 AB23 AB24 AB30 AC10 AE10 AB12 AB13 AB16 AB18 AB19 P8 R10 T12 T13 T16 U18 U19 R32 T30 U21 U22 U24 U26 U29 N11 AG29 AA11 AA13 AA15 AA17 AA19 AA23 AA30 AB10 AC11 AC14 AC17 AC20 AC23 AC26 AC28 AE30 AF11 AF14 AF17 AF20 AF23 AF26 AF29 AF30 AG31 AG9 AJ11 AJ14 AJ17 AJ20 AJ23 AJ26 AJ29 AJ32 AJ8 AM11 AM14 AM17 AM20 AM23 AM26 AM29 AM32 AM8 AR11 AR14 AR17 AR20 AR23 AR26 Pin List GF40 Page 36 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) AR29 AR32 AR8 AV11 AV14 AV17 AV20 AV23 AV26 AV29 AV32 AV5 AV8 B11 B14 B17 B20 B23 B26 B29 B32 B8 E11 E14 E17 E20 E23 E26 E29 E32 E8 H11 H14 H17 H20 H23 H26 H29 H32 H8 L11 L14 L17 L20 L23 L26 L29 L32 L8 N8 P11 P14 P17 P20 P23 P26 P29 P32 U11 U13 U15 U17 U20 U23 U25 U27 U30 V10 V12 V14 V16 V18 V21 V24 V26 V28 V30 W11 W13 W15 W17 W19 W23 W25 W27 W29 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y24 Y26 Y28 Pin List GF40 Page 37 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Note (1) Bank Number VREF PinName/Function (2) Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND VCCR_GXBR VCCR_GXBR VCCR_GXBL VCCR_GXBL VCCD_FPLL VCCD_FPLL VCCA_FPLL VCCA_FPLL VCCL_GXBR2 VCCL_GXBR2 VCCL_GXBL2 VCCL_GXBL2 VCCH_GXBR2 VCCH_GXBL2 VCCA_GXBR2 VCCA_GXBL2 GND GND GND GND DNU DNU DNU DNU GND GND GND GND DNU DNU DNU DNU GND GND GND GND DNU DNU DNU DNU GND GND GND GND GND DNU GND DNU GND GND GND GND DNU DNU DNU DNU GND GND GND GND DNU DNU DNU DNU GND GND GND GND DNU GND DNU GND VCCT_GXBR2 VCCT_GXBR2 VCCT_GXBL2 VCCT_GXBL2 Emulated LVDS Output Channel F1517 DQS for X8/X9 DQS for X16/ X18 DQS for X32/ X36 DDR3/DDR2 hard memory PHY (3) W21 V6 V5 W35 W34 R9 T31 U9 V31 R6 R5 T35 T34 R7 T33 U7 V33 H38 T8 H39 T9 G37 B4 G36 B3 F38 C1 F39 C2 E37 D4 E36 D3 D38 E1 D39 E2 C37 F4 C36 F3 U31 G1 U32 G2 W31 H4 W32 H3 P38 J1 P39 J2 N37 K4 N36 K3 M38 L1 M39 L2 L37 M4 L36 M3 K38 N1 K39 N2 J37 V8 J36 V9 U5 T6 V35 U34 Notes: (1) For more information about pin definitions and pin connection guidelines, refer to the Arria V Device Family Pin Connection Guidelines. (2) GXB_REFCLK pin is not supported in current Quartus II version, but will be supported in future Quartus II release version. (3) RESET pin is only applicable for DDR3 device. PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Pin List GF40 Page 38 of 39 Pin Information for the Arria® V 5AGXMB3 Device Version 1.7 Version Number 1.0 Date 9/2/2011 1.1 11/8/2011 1.2 1.3 1.4 11/30/2011 1/3/2012 5/11/2012 1.5 7/6/2012 1.6 1.7 9/3/2012 7/31/2015 PT-5AGXMB3-1.7 Copyright © 2015 Altera Corp. Changes Made Initial release. Updated F1517 package - R9 and T31 changed from NC to VCCD_FPLL - U9 and V31 changed from NC to VCCA_FPLL Updated pin name nPERSTL1 to nPERSTR0 Split VCC to VCC and VCCP Rename the CQ pins in DQS and hard memory PHY columns - Some of the NC pins changed to power, DNU, or GND pins. - Updated for production deivce support. Added two HMC address pins (A_4D_15 and A_7D_15) for 5AGXB3 production devices, these two pins are not applicable for 5AGXB3 ES devices. Removed unsupported nPERSTR0 pin Removed LPDDR2 hard memory PHY, RLDRAMII hard memory PHY, and QDRII hard memory PHY columns. Revision History Page 39 of 39