Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number VREF Group 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 Pin Name /Function TDI TMS TRST TCK TDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) TDI TMS TRST TCK TDO RDN1A RUP1A CLKUSR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFIO_RX_L1n DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFIO_RX_L3n DIFFIO_RX_L3p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFIO_RX_L5n DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFIO_RX_L8n DIFFIO_RX_L8p DIFFIO_TX_L9n DIFFIO_TX_L9p DIFFIO_RX_L9n DIFFIO_RX_L9p DIFFIO_TX_L10n DIFFIO_TX_L10p DIFFIO_RX_L10n DIFFIO_RX_L10p DIFFIO_TX_L11n DIFFIO_TX_L11p DIFFIO_RX_L11n DIFFIO_RX_L11p DIFFIO_TX_L12n DIFFIO_TX_L12p DIFFIO_RX_L12n DIFFOUT_L1n DIFFOUT_L1p DIFFOUT_L2n DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFOUT_L6n DIFFOUT_L6p DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFOUT_L10n DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFOUT_L16n DIFFOUT_L16p DIFFOUT_L17n DIFFOUT_L17p DIFFOUT_L18n DIFFOUT_L18p DIFFOUT_L19n DIFFOUT_L19p DIFFOUT_L20n DIFFOUT_L20p DIFFOUT_L21n DIFFOUT_L21p DIFFOUT_L22n DIFFOUT_L22p DIFFOUT_L23n DIFFOUT_L23p DIFFOUT_L24n Pin List F780 J20 G23 D26 D25 E25 H23 H22 D28 D27 G25 G24 B28 C28 F26 F25 E28 E27 H25 H24 G27 G26 K24 K23 F28 G28 K22 K21 J26 J25 L21 L20 H28 H27 L23 L22 K26 K25 L24 M23 L26 L25 N21 N20 J28 K28 N23 N22 L28 K27 P21 P20 M26 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQSn2L DQS2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQSn3L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn5L DQS5L DQ5L DQ5L DQ5L DQ5L DQ6L DQ6L DQSn6L DQS6L DQ6L DQ6L DQSn7L DQ5L DQ5L DQ5L DQ5L/CQn5L DQ5L DQ5L DQSn5L/DQ5L Page 1 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A VREF Group VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO CLK1n CLK1p CLK3p CLK3n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) PLL_L2_CLKOUT0n PLL_L2_FB_CLKOUT0p CLK0n CLK0p CLK1n CLK1p CLK3p CLK3n CLK2p CLK2n Configuration Function for Stratix IV Only (1) DATA7 INIT_DONE CRC_ERROR DEV_OE DEV_CLRn Dedicated Tx_Rx Channel (2) DIFFIO_RX_L12p DIFFIO_TX_L13n DIFFIO_TX_L13p DIFFIO_RX_L13n DIFFIO_RX_L13p DIFFIO_TX_L14n DIFFIO_TX_L14p DIFFIO_RX_L14n DIFFIO_RX_L14p Emulated LVDS Output Channel (2) DIFFOUT_L24p DIFFOUT_L25n DIFFOUT_L25p DIFFOUT_L26n DIFFOUT_L26p DIFFOUT_L27n DIFFOUT_L27p DIFFOUT_L28n DIFFOUT_L28p DIFFIO_RX_L15p DIFFIO_RX_L15n DIFFIO_TX_L15p DIFFIO_TX_L15n DIFFIO_RX_L16p DIFFIO_RX_L16n DIFFIO_TX_L16p DIFFIO_TX_L16n DIFFIO_RX_L17p DIFFIO_RX_L17n DIFFIO_TX_L17p DIFFIO_TX_L17n DIFFIO_RX_L18p DIFFIO_RX_L18n DIFFIO_TX_L18p DIFFIO_TX_L18n DIFFIO_RX_L19p DIFFIO_RX_L19n DIFFIO_TX_L19p DIFFIO_TX_L19n DIFFIO_RX_L20p DIFFIO_RX_L20n DIFFIO_TX_L20p DIFFIO_TX_L20n DIFFIO_RX_L21p DIFFIO_RX_L21n DIFFIO_TX_L21p DIFFIO_TX_L21n DIFFIO_RX_L22p DIFFIO_RX_L22n DIFFIO_TX_L22p DIFFIO_TX_L22n DIFFIO_RX_L23p DIFFIO_RX_L23n DIFFIO_TX_L23p DIFFIO_TX_L23n DIFFIO_RX_L24p DIFFIO_RX_L24n DIFFIO_TX_L24p DIFFOUT_L29p DIFFOUT_L29n DIFFOUT_L30p DIFFOUT_L30n DIFFOUT_L31p DIFFOUT_L31n DIFFOUT_L32p DIFFOUT_L32n DIFFOUT_L33p DIFFOUT_L33n DIFFOUT_L34p DIFFOUT_L34n DIFFOUT_L35p DIFFOUT_L35n DIFFOUT_L36p DIFFOUT_L36n DIFFOUT_L37p DIFFOUT_L37n DIFFOUT_L38p DIFFOUT_L38n DIFFOUT_L39p DIFFOUT_L39n DIFFOUT_L40p DIFFOUT_L40n DIFFOUT_L41p DIFFOUT_L41n DIFFOUT_L42p DIFFOUT_L42n DIFFOUT_L43p DIFFOUT_L43n DIFFOUT_L44p DIFFOUT_L44n DIFFOUT_L45p DIFFOUT_L45n DIFFOUT_L46p DIFFOUT_L46n DIFFOUT_L47p DIFFOUT_L47n DIFFOUT_L48p Pin List F780 M25 N25 N24 M28 L27 P26 P25 N28 N27 P28 P27 T28 R28 T27 U28 R25 R26 T25 U26 R20 T21 U27 V28 T22 T23 U25 V26 T20 U21 W27 W28 U23 U24 V25 W26 V22 V23 Y27 Y28 W24 W25 AB28 AA28 W22 W23 AB27 AC28 V20 W21 AC27 AD28 Y25 DQ Group for DQS X4 Mode (2) DQS7L DQ7L DQ7L DQ7L DQ7L DQ Group for DQS X8/X9 Mode (2) DQS5L/CQ5L DQ5L DQ5L DQ5L DQ5L DQ8L DQ8L DQ8L DQ8L DQS8L DQSn8L DQ9L DQ9L DQS9L DQSn9L DQ9L DQ9L DQ10L DQ10L DQ10L DQ10L DQS10L DQSn10L DQ10L DQ10L DQ10L DQ10L DQS10L/CQ10L DQSn10L/DQ10L DQ10L DQ10L DQ10L/CQn10L DQ10L DQ10L DQ10L DQ11L DQ11L DQ11L DQ11L DQS11L DQSn11L DQ12L DQ12L DQS12L DQSn12L DQ12L DQ13L DQ13L DQ13L DQ13L DQS13L/CQ13L DQSn13L/DQ13L DQ13L DQ13L DQ13L/CQn13L DQ13L DQ13L DQ Group for DQS X16/X18 Mode (2) DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQS14L/CQ14L DQSn14L/DQ14L DQ14L Page 2 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A VREF Group VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nCONFIG nSTATUS CONF_DONE PORSEL nCE IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) RUP2A RDN2A Dedicated Tx_Rx Channel (2) DIFFIO_TX_L24n DIFFIO_RX_L25p DIFFIO_RX_L25n DIFFIO_TX_L25p DIFFIO_TX_L25n DIFFIO_RX_L26p DIFFIO_RX_L26n DIFFIO_TX_L26p DIFFIO_TX_L26n DIFFIO_RX_L27p DIFFIO_RX_L27n DIFFIO_TX_L27p DIFFIO_TX_L27n DIFFIO_RX_L28p DIFFIO_RX_L28n DIFFIO_TX_L28p DIFFIO_TX_L28n Emulated LVDS Output Channel (2) DIFFOUT_L48n DIFFOUT_L49p DIFFOUT_L49n DIFFOUT_L50p DIFFOUT_L50n DIFFOUT_L51p DIFFOUT_L51n DIFFOUT_L52p DIFFOUT_L52n DIFFOUT_L53p DIFFOUT_L53n DIFFOUT_L54p DIFFOUT_L54n DIFFOUT_L55p DIFFOUT_L55n DIFFOUT_L56p DIFFOUT_L56n nCONFIG nSTATUS CONF_DONE PORSEL nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFIO_RX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p Pin List DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p F780 Y26 AA25 AA26 AB25 AC26 AE27 AE28 Y23 Y24 AF27 AF28 AB23 AB24 AH27 AG28 AC25 AD26 AA22 AC23 AC24 W20 Y21 AB21 AC21 AD22 AC22 AA20 AB20 AE23 AD23 AE24 AE25 AG23 AF24 AF25 AF26 AH25 AG25 AG26 AH26 AH24 AH23 AG22 AH22 AF22 AE22 AH20 AH21 AF21 AE21 AG19 AG20 DQ Group for DQS X4 Mode (2) DQ12L DQ13L DQ13L DQ13L DQ13L DQS13L DQSn13L DQ14L DQ14L DQS14L DQSn14L DQ14L DQ14L DQ Group for DQS X8/X9 Mode (2) DQ13L DQ14L DQ14L DQ14L DQ14L DQS14L/CQ14L DQSn14L/DQ14L DQ14L DQ14L DQ14L/CQn14L DQ14L DQ14L DQ14L DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQ Group for DQS X16/X18 Mode (2) DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L/CQn14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B Page 3 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C VREF Group VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_B8n DIFFIO_RX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_RX_B12n DIFFIO_RX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 DIFFIO_RX_B14n DIFFIO_RX_B14p PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p CLK6p CLK6n CLK7p CLK7n DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_RX_B16n DIFFIO_RX_B16p DIFFIO_RX_B17p DIFFIO_RX_B17n DIFFIO_RX_B18p DIFFIO_RX_B18n DIFFIO_RX_B19p DIFFIO_RX_B19n DIFFIO_RX_B20p DIFFIO_RX_B20n DIFFIO_RX_B21p DIFFIO_RX_B21n Pin List Emulated LVDS Output Channel (2) DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33p DIFFOUT_B33n DIFFOUT_B34p DIFFOUT_B34n DIFFOUT_B35p DIFFOUT_B35n DIFFOUT_B36p DIFFOUT_B36n DIFFOUT_B37p DIFFOUT_B37n DIFFOUT_B38p DIFFOUT_B38n DIFFOUT_B39p DIFFOUT_B39n DIFFOUT_B40p DIFFOUT_B40n DIFFOUT_B41p DIFFOUT_B41n F780 AF19 AE20 AD19 AC19 AE19 AD20 AA19 AB18 Y18 Y17 AA17 AA16 AC18 AB17 Y15 Y16 AH19 AH18 AE17 AG17 AF18 AE18 AD17 AD16 AF16 AE16 AC16 AB15 AF15 AE15 AH17 AG16 AH16 AH15 AG14 AH14 AH12 AH13 AF14 AG13 Y13 Y14 AA13 AA14 AB12 AB11 AD13 AE12 AE13 AE14 AC12 AD11 DQ Group for DQS X4 Mode (2) DQSn6B DQS6B DQ6B DQ6B DQ6B DQ6B DQ Group for DQS X8/X9 Mode (2) DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ3B DQ3B DQ3B DQ7B DQ7B DQSn7B DQS7B DQ7B DQ7B DQSn8B DQS8B DQ8B DQ8B DQ8B DQ8B DQ7B DQ7B DQ7B DQ7B/CQn7B DQ7B DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ9B DQ9B DQS9B DQSn9B DQ9B DQ9B DQ10B DQ10B DQ10B DQ10B DQS10B DQSn10B DQ11B DQ11B DQ11B DQ11B DQS11B/CQ11B DQSn11B/DQ11B DQ Group for DQS X16/X18 Mode (2) Page 4 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number 4C 4C 4C 4C 4C 4C 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 7A VREF Group VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB7AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nIO_PULLUP nCEO DCLK nCSO ASDO IO PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_B22p DIFFIO_RX_B22n DIFFIO_RX_B23p DIFFIO_RX_B23n DIFFIO_RX_B24p DIFFIO_RX_B24n DIFFIO_RX_B25p DIFFIO_RX_B25n DIFFIO_RX_B26p DIFFIO_RX_B26n DIFFIO_RX_B27p DIFFIO_RX_B27n DIFFIO_RX_B28p DIFFIO_RX_B28n DIFFIO_RX_B29p DIFFIO_RX_B29n DIFFIO_RX_B30p DIFFIO_RX_B30n DIFFIO_RX_B31p DIFFIO_RX_B31n RUP4A RDN4A DIFFIO_RX_B32p DIFFIO_RX_B32n Emulated LVDS Output Channel (2) DIFFOUT_B42p DIFFOUT_B42n DIFFOUT_B43p DIFFOUT_B43n DIFFOUT_B44p DIFFOUT_B44n DIFFOUT_B45p DIFFOUT_B45n DIFFOUT_B46p DIFFOUT_B46n DIFFOUT_B47p DIFFOUT_B47n DIFFOUT_B48p DIFFOUT_B48n DIFFOUT_B49p DIFFOUT_B49n DIFFOUT_B50p DIFFOUT_B50n DIFFOUT_B51p DIFFOUT_B51n DIFFOUT_B52p DIFFOUT_B52n DIFFOUT_B53p DIFFOUT_B53n DIFFOUT_B54p DIFFOUT_B54n DIFFOUT_B55p DIFFOUT_B55n DIFFOUT_B56p DIFFOUT_B56n DIFFOUT_B57p DIFFOUT_B57n DIFFOUT_B58p DIFFOUT_B58n DIFFOUT_B59p DIFFOUT_B59n DIFFOUT_B60p DIFFOUT_B60n DIFFOUT_B61p DIFFOUT_B61n DIFFOUT_B62p DIFFOUT_B62n DIFFOUT_B63p DIFFOUT_B63n DIFFOUT_B64p DIFFOUT_B64n nIO_PULLUP nCEO DCLK nCSO ASDO DIFFOUT_T1n Pin List F780 AF12 AH11 AE11 AF11 AH10 AG11 Y12 AA11 Y10 Y11 AC10 AD10 AB9 AB10 AE9 AE10 AF10 AF9 AG8 AH8 AH9 AG10 AG7 AH6 AH5 AH7 AF6 AG5 AE7 AE8 AE6 AF7 AD7 AD8 AG4 AH4 AF3 AF4 AH2 AH3 AC6 AC8 AA8 AB7 Y9 AA10 Y8 W6 Y6 W7 Y7 F7 DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X4 Mode (2) DQ11B DQ11B DQS11B DQSn11B DQ11B DQ11B DQ Group for DQS X8/X9 Mode (2) DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQ11B DQ12B DQ12B DQ12B DQ12B DQS12B DQSn12B DQ13B DQ13B DQS13B DQSn13B DQ13B DQ13B DQ14B DQ14B DQ14B DQ14B DQS14B DQSn14B DQ15B DQ15B DQS15B DQSn15B DQ15B DQ15B DQ16B DQ16B DQ16B DQ16B DQS16B DQSn16B DQ17B DQ17B DQS17B DQSn17B DQ17B DQ17B DQ15B DQ15B DQ15B DQ15B DQS15B/CQ15B DQSn15B/DQ15B DQ15B DQ15B DQ15B/CQn15B DQ15B DQ15B DQ15B DQ16B DQ16B DQ16B DQ16B DQS16B/CQ16B DQSn16B/DQ16B DQ16B DQ16B DQ16B/CQn16B DQ16B DQ16B DQ16B DQ17B DQ17B DQ17B DQ17B DQS17B/CQ17B DQSn17B/DQ17B DQ17B DQ17B DQ17B/CQn17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQS17B/CQ17B DQSn17B/DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B/CQn17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ1T DQ1T DQ1T Page 5 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C VREF Group VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) RDN7A RUP7A Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n DIFFIO_RX_T3p DIFFIO_RX_T4n DIFFIO_RX_T4p DIFFIO_RX_T5n DIFFIO_RX_T5p DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n DIFFIO_RX_T7p DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFIO_RX_T9n DIFFIO_RX_T9p DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T11n DIFFIO_RX_T11p DIFFIO_RX_T12n DIFFIO_RX_T12p DIFFIO_RX_T13n DIFFIO_RX_T13p Pin List Emulated LVDS Output Channel (2) DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p DIFFOUT_T8n DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T21n DIFFOUT_T21p DIFFOUT_T22n DIFFOUT_T22p DIFFOUT_T23n DIFFOUT_T23p DIFFOUT_T24n DIFFOUT_T24p DIFFOUT_T25n DIFFOUT_T25p DIFFOUT_T26n DIFFOUT_T26p DIFFOUT_T27n F780 G8 E7 F8 G9 H9 D6 E6 D5 F6 C4 C5 A2 B3 A3 B4 A5 A4 A6 B6 C7 D7 A7 B7 B9 A8 C8 D8 B10 A9 D10 E9 F10 E10 C10 D9 H10 G11 J11 J12 A11 A10 C11 D11 B12 D12 E12 F11 F13 E13 C13 D13 H12 DQ Group for DQS X4 Mode (2) DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQSn3T DQS3T DQ3T DQ3T DQSn4T DQS4T DQ4T DQ4T DQ4T DQ4T DQ5T DQ5T DQSn5T DQS5T DQ5T DQ5T DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQ Group for DQS X8/X9 Mode (2) DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQ7T DQ7T DQSn7T DQS7T DQ7T DQ7T DQSn8T DQS8T DQ8T DQ8T DQ8T DQ8T DQ9T DQ7T DQ7T DQ7T DQ7T/CQn7T DQ7T DQ7T DQSn7T/DQ7T DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQ Group for DQS X16/X18 Mode (2) DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T Page 6 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREF Group VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_T14n DIFFIO_RX_T14p DIFFIO_RX_T15n DIFFIO_RX_T15p CLK13n CLK13p CLK12n CLK12p CLK14p CLK14n CLK15p CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n DIFFIO_RX_T16n DIFFIO_RX_T16p DIFFIO_RX_T17p DIFFIO_RX_T17n DIFFIO_RX_T18p DIFFIO_RX_T18n DIFFIO_RX_T19p DIFFIO_RX_T19n PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 DIFFIO_RX_T20p DIFFIO_RX_T20n DIFFIO_RX_T21p DIFFIO_RX_T21n DIFFIO_RX_T22p DIFFIO_RX_T22n DIFFIO_RX_T23p DIFFIO_RX_T23n DIFFIO_RX_T24p DIFFIO_RX_T24n DIFFIO_RX_T25p DIFFIO_RX_T25n DIFFIO_RX_T26p DIFFIO_RX_T26n DIFFIO_RX_T27p Pin List Emulated LVDS Output Channel (2) DIFFOUT_T27p DIFFOUT_T28n DIFFOUT_T28p DIFFOUT_T29n DIFFOUT_T29p DIFFOUT_T30n DIFFOUT_T30p DIFFOUT_T31n DIFFOUT_T31p DIFFOUT_T32n DIFFOUT_T32p DIFFOUT_T33p DIFFOUT_T33n DIFFOUT_T34p DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T35n DIFFOUT_T36p DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T37n DIFFOUT_T38p DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T39n DIFFOUT_T40p DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T41n DIFFOUT_T42p DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T43n DIFFOUT_T44p DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T45n DIFFOUT_T46p DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T47n DIFFOUT_T48p DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p F780 G12 G14 H13 J14 J13 C14 D14 A14 B13 A12 A13 B15 A15 B16 A16 D15 C15 J15 H15 E16 D16 J16 H16 A19 A18 A17 B18 C18 C17 G17 D17 F17 E18 D18 F18 J17 H18 H19 J18 C19 B19 A20 A21 C20 B21 F19 G19 E19 D19 D20 F20 D21 DQ Group for DQS X4 Mode (2) DQ9T DQSn9T DQS9T DQ9T DQ9T DQ Group for DQS X8/X9 Mode (2) DQ10T DQ10T DQ10T DQ10T DQS10T DQSn10T DQ11T DQ11T DQS11T DQSn11T DQ11T DQ11T DQ11T DQ11T DQ11T DQ11T DQS11T/CQ11T DQSn11T/DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQ11T DQ12T DQ12T DQ12T DQ12T DQS12T DQSn12T DQ13T DQ13T DQS13T DQSn13T DQ13T DQ13T DQ14T DQ15T DQ15T DQ15T DQ15T DQS15T/CQ15T DQSn15T/DQ15T DQ15T DQ15T DQ15T/CQn15T DQ15T DQ15T DQ15T DQ16T DQ Group for DQS X16/X18 Mode (2) DQ17T Page 7 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 VREF Group VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name Optional /Function Function(s) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO RUP8A IO RDN8A IO IO GXB_RX_R0p GXB_RX_R0n GXB_TX_R0p GXB_TX_R0n GXB_RX_R1p GXB_RX_R1n GXB_TX_R1p GXB_TX_R1n REFCLK_R0p, GXB_CMURX_R0p REFCLK_R0n, GXB_CMURX_R0n REFCLK_R1p, GXB_CMURX_R1p REFCLK_R1n, GXB_CMURX_R1n GXB_RX_R2p GXB_RX_R2n GXB_TX_R2p GXB_TX_R2n GXB_RX_R3p GXB_RX_R3n GXB_TX_R3p GXB_TX_R3n GXB_RX_R4p GXB_RX_R4n GXB_TX_R4p GXB_TX_R4n GXB_RX_R5p GXB_RX_R5n GXB_TX_R5p GXB_TX_R5n REFCLK_R2p, GXB_CMURX_R2p PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_T27n DIFFIO_RX_T28p DIFFIO_RX_T28n DIFFIO_RX_T29p DIFFIO_RX_T29n DIFFIO_RX_T30p DIFFIO_RX_T30n DIFFIO_RX_T31p DIFFIO_RX_T31n DIFFIO_RX_T32p DIFFIO_RX_T32n Pin List Emulated LVDS Output Channel (2) DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T55n DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n F780 C21 A22 A23 C22 B22 H21 E21 E22 D22 G21 F21 B24 A24 D24 C25 D23 C24 A26 C26 B25 A25 A27 B27 AD2 AD1 AC4 AC3 AB2 AB1 AA4 AA3 Y2 Y1 W4 W3 V2 V1 U4 U3 T2 T1 R4 R3 P2 P1 N4 N3 M2 M1 L4 L3 K2 DQ Group for DQS X4 Mode (2) DQ14T DQ14T DQ14T DQS14T DQSn14T DQ15T DQ15T DQS15T DQSn15T DQ15T DQ15T DQ16T DQ16T DQ16T DQ16T DQS16T DQSn16T DQ17T DQ17T DQS17T DQSn17T DQ17T DQ17T DQ Group for DQS X8/X9 Mode (2) DQ16T DQ16T DQ16T DQS16T/CQ16T DQSn16T/DQ16T DQ16T DQ16T DQ16T/CQn16T DQ16T DQ16T DQ16T DQ17T DQ17T DQ17T DQ17T DQS17T/CQ17T DQSn17T/DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQ17T DQ17T DQ Group for DQS X16/X18 Mode (2) DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQS17T/CQ17T DQSn17T/DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T Page 8 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 VREF Group Pin Name Optional /Function Function(s) REFCLK_R2n, GXB_CMURX_R2n REFCLK_R3p, GXB_CMURX_R3p REFCLK_R3n, GXB_CMURX_R3n GXB_RX_R6p GXB_RX_R6n GXB_TX_R6p GXB_TX_R6n GXB_RX_R7p GXB_RX_R7n GXB_TX_R7p GXB_TX_R7n GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Pin List Emulated LVDS Output Channel (2) F780 K1 J4 J3 H2 H1 G4 G3 F2 F1 E4 E3 M17 W8 P15 AG3 AG6 AG9 AG12 AG15 AG18 AG21 AG24 AG27 AD6 AD9 AD12 AD15 AD18 AD21 AD24 AD27 AA6 AA9 AA12 AA15 AA18 AA21 AA24 AA27 W12 W14 W16 W18 W19 V9 V11 V13 V15 V17 V19 V21 V24 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) Page 9 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number VREF Group Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Pin List Emulated LVDS Output Channel (2) F780 V27 U12 U14 U16 U18 T11 T13 T15 T17 T19 R12 R16 R18 R21 R24 R27 P11 P13 P17 P19 N12 N14 N16 N18 M11 M13 M15 M19 M21 M24 M27 L8 L12 L14 L16 L18 K11 K13 K15 K17 K19 J21 J24 J27 H5 H8 H11 H14 H17 H20 F24 F27 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) Page 10 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number VREF Group Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Pin List Emulated LVDS Output Channel (2) F780 E5 E8 E11 E14 E17 E20 E23 C27 B2 B5 B8 B11 B14 B17 B20 B23 B26 C2 C1 D4 D3 D2 E2 E1 F4 F3 G2 G1 H4 H3 J2 J1 K4 K3 L5 L2 L1 M6 M4 M3 N7 N5 N2 N1 P8 P6 P4 P3 R7 R5 R2 R1 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) Page 11 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number VREF Group Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Pin List Emulated LVDS Output Channel (2) F780 T8 T6 T4 T3 U5 U2 U1 V6 V4 V3 W2 W1 Y4 Y3 AA2 AA1 AB4 AB3 AC2 AC1 AD4 AD3 AE2 AE1 AF2 AG2 AG1 P14 V12 V14 V16 V18 U11 U13 U15 U17 T12 T14 T16 T18 R11 R13 R15 R17 P12 P16 P18 N11 N13 N15 N17 M12 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) Page 12 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number VREF Group Pin Name /Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPGM VCCPGM TEMPDIODEn TEMPDIODEp VCC_CLKIN3C VCC_CLKIN4C VCC_CLKIN7C VCC_CLKIN8C VCCA_PLL_B1 VCCA_PLL_L2 VCCA_PLL_T1 VCCD_PLL_B1 VCCD_PLL_L2 VCCD_PLL_T1 VCCIO1A VCCIO1A VCCIO1A VCCIO1C VCCIO1C VCCIO2A VCCIO2A VCCIO2A VCCIO2C VCCIO2C VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3C VCCIO3C VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4C VCCIO4C VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7C PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Pin List Emulated LVDS Output Channel (2) F780 M14 M16 M18 L11 L13 L15 L17 U7 U8 M7 M8 Y20 W9 H7 G6 AD14 AC13 F14 F16 AC14 R23 E15 AC15 P23 F15 J23 H26 E26 P24 N26 AD25 AB26 AA23 T24 T26 AF20 AF23 AC20 Y19 AF17 AC17 AF5 AF8 AC7 AC9 AF13 AC11 J10 F9 C6 C9 F12 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) Page 13 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number VREF Group 1A 1C 2A 2C 3A 3C 4A 4C 7A 7C 8A 8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 Pin Name /Function VCCIO7C VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8C VCCIO8C VCCPD1A VCCPD1C VCCPD2A VCCPD2C VCCPD3A VCCPD3C VCCPD4A VCCPD4C VCCPD7A VCCPD7C VCCPD8A VCCPD8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 Pin List Emulated LVDS Output Channel (2) F780 C12 J19 F22 E24 C23 G18 C16 L19 N19 U19 R19 W17 W15 W11 W13 K12 K14 K18 K16 J22 M22 Y22 U22 AB19 AB16 AB8 AB13 G10 G13 G20 G16 F23 AE26 AB6 J8 AE4 AE3 AE5 AD5 AC5 AB5 AA5 Y5 W5 W10 V7 V8 V10 U9 U10 U20 T9 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) Page 14 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number VREF Group Pin Name /Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC (4) NC (5) NC (5) NC (5) NC (5) NC (5) NC (5) NC (7) NC (6) NC (3) NC (3) NC (3) VCCAUX VCCAUX VCCAUX VCCAUX VCCA_R VCCA_R VCCH_GXBR0 VCCH_GXBR1 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBR1 VCCL_GXBR1 VCCR_R VCCR_R VCCT_R VCCT_R PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) MSEL2 MSEL1 MSEL0 Pin List Emulated LVDS Output Channel (2) F780 T10 N10 M9 M10 M20 L7 L9 L10 K5 K6 K7 K8 K10 K20 J5 J6 G5 F5 C3 B1 H6 R22 P22 AB14 R10 P10 G15 D1 R14 J7 J9 K9 G22 AB22 AA7 G7 N6 T5 V5 L6 R8 T7 N8 P7 M5 R6 P5 U6 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) Page 15 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Bank Number VREF Group Pin Name /Function VCCHIP_R VCCHIP_R VCCHIP_R RREF_R0 Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F780 N9 P9 R9 AF1 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) Notes: (1) These pins should be connected on the board to properly configure the FPGA prototype. For more information, refer to Stratix® IV device pin table. (2) The individual index number of the pin in this column may not be the same as its companion, the Stratix IV device, but the functionality of the pin is fully migratable. (3) These NO CONNECT (NC) pins are MSEL configuration input pins in the Stratix IV device and should be connected on the board to configure the FPGA prototype. (4) This NC pin is a VCCBAT pin in the Stratix IV device and should be connected for the FPGA prototype. (5) This NC pin is a VCCPT pin in the Stratix IV device and should be connected for the FPGA prototype. (6) This NC pin is a DNU pin in the Stratix IV device and must be left floating. (7) This NC pin is a RREF pin in the Stratix IV device and should be connected to GND for the FPGA prototype. PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Pin List Page 16 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Notes (1), (2) Pin Name Pin Type (1st and 2nd Function) Pin Description CLK[1,3,8,10]p CLK[1,3,8,10]n Clock, Input Clock, Input Clock and PLL Pins Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins. Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins. CLK[0,2,9,11]p CLK[0,2,9,11]n CLK[4:7,12:15]p I/O, Clock I/O, Clock I/O, Clock These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is supported on these pins. These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins. CLK[4:7,12:15]n PLL_[L1,L4,R1,R4]_CLKp PLL_[L1,L4,R1,R4]_CLKn PLL_[L1, L2, L3, L4]_CLKOUT0n PLL_[R1, R2, R3, R4]_CLKOUT0n PLL_[L1, L2, ,L3, L4]_FB_CLKOUT0p PLL_[R1, R2, R3, R4]_FB_CLKOUT0p PLL_[T1,T2,B1,B2]_FBp/CLKOUT1 PLL_[T1,T2,B1,B2]_FBn/CLKOUT2 PLL_[T1,T2,B1,B2]_CLKOUT[3,4] PLL_[T1,T2,B1,B2]_CLKOUT0p PLL_[T1,T2,B1,B2]_CLKOUT0n I/O, Clock Clock, Input Clock, Input I/O, Clock These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins. Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively. Dedicated negative clock input pins for differential clock input to PLL L1, L4, R1, and R4 respectively. Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin. nIO_PULLUP Input I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin. These pins can be used as I/O pins or two single-ended clock output pins. I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. TEMPDIODEp Input Dedicated Configuration/JTAG Pins Dedicated input that chooses whether the internal pull-up resistors on the user I/O pins are on or off during power up. A logic high turns off the weak pull-ups, while a logic low turns them on. Pin used in conjunction with the temperature sensing diode (bias-high input) inside the HardCopy IV device. TEMPDIODEn Input Pin used in conjunction with the temperature sensing diode (bias-low input) inside the HardCopy IV device. nCE nCONFIG Input Input Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Dedicated power up block control input. Pulling this pin low during user-mode will cause the HardCopy IV to enter a reset state & tri-state all I/O pins. Returning this pin to a logic high level will initiate the power up and initialization sequence. It is not available as a user I/O pin. CONF_DONE Bidirectional (open-drain) Output Bidirectional (open-drain) This is a dedicated power up block status pin. As a status output, the CONF_DONE pin drives low before and during initialization. Driven this pin high indicates that the device is entering user mode. Output that drives low when device initialization is complete. This is a dedicated power up block status pin. The HardCopy IV drives nSTATUS low indicates that the device is being initialized. As a status output, the nSTATUS is pulled low if an error occurs during initialization. As a status input, this pin delays the completion of the Initialization phase when nSTATUS is driven low by an external source during initialization. It is not available as a user I/O pin. PORSEL Input Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high selects a POR time of 12 ms and a logic low selects POR time of 100 ms. TCK TMS TDI TDO TRST Input Input Input Output Input nCSO ASDO DCLK I/O, Output I/O, Output Input (PS, FPP) Output (AS) Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG output pin. Dedicated active low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. Optional/Dual-Purpose Configuration Pins Dedicated control signal from Stratix IV devices, but kept in HardCopy IV for compatibility reasons. Dedicated control signal from Stratix IV devices, but kept in HardCopy IV for compatibility reasons. Dedicated configuration clock pin on Stratix IV devices, but kept in HardCopy IV for compatibility reasons. It's not required to clock this pin for HardCopy IV. DIFFIO_RX[##]p, DIFFIO_RX[##]n DIFFIO_TX[##]p, DIFFIO_TX[##]n DIFFOUT_[##]p, DIFFOUT_[##]n I/O, RX channel nCEO nSTATUS PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. I/O, TX channel I/O, TX channel Differential I/O Pins These are true LVDS receiver channels on side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signa for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. Pin Definitions Page 17 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Notes (1), (2) Pin Type (1st and 2nd Function) Pin Description DQS[1:38][T,B], DQS[1:34][L,R] I/O,DQS External Memory Interface Pins Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic. DQSn[1:38][T,B], DQSn[1:34][L,R] I/O,DQSn Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. DQ[1:38][T,B], DQ[1:34][L,R] I/O,DQ Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. CQ[1:38][T,B], CQ[1:34][L,R] DQS Optional data strobe signal for use in QDRII SRAM. These are the pins for echo clocks. CQn[1:38][T,B], CQn[1:34][L,R] DQS Optional complementary data strobe signal for use in QDRII SRAM. These are the pins for echo clocks. RUP[1:8]A, RUP[3,8]C RDN[1:8]A, RDN[3,8]C DNU NC I/O, Input VCC VCCD_PLL_[L,R][1:4], VCCD_PLL_[T,B][1:2] VCCA_PLL_[L,R][1:4], VCCA_PLL_[T,B][1:2] VCCAUX VCCIO[1:8][A,C], VCCIO[2,3,4,5,7,8]B Power Power VCCPGM VCCPD[1:8][A,C], VCCPD[2,3,4,5,7,8]B VCC_CLKIN[3,4,7,8]C GND VREFB[1:8][A,C]N0, VREFB[2,3,4,5,7,8]BN0 Power Power Analog power for PLL [L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in datasheet, even if the PLL is not used. It is advised to keep this pin isolated from other VCC for better jitter performance. Auxiliary supply for the programmable power technology. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), HSTL(12, 15, 18),SSTL(15, 18, 2), 3.0 V PCI/PCI-X I/O as well as LVTTL 3.3 V I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), 3.0 V PCI/PCI-X and LVTTL 3.3 V I/O standards. Configuration pins power supply. Dedicated power pins. This supply is used to power the I/O pre-drivers. Power Ground Power Differential clock input power supply for top and bottom I/O banks. Device ground pins. Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. VCCHIP_[L,R] VCCR_[L,R] VCCT_[L,R] VCCL_GXB[L,R][0:3] VCCH_GXB[L,R][0:3] VCCA_[L,R] GXB_RX_[L,R][0:15]p GXB_RX_[L,R][0:15]n GXB_TX_[L,R][0:15]p GXB_TX_[L,R][0:15]n Power Power Power Power Power Power Input Input Output Output Transceiver (I/O Banks) Pins PCIe Hard IP digital power supply, specific to the left (L) side or right (R) side of the device. Analog power, receiver, specific to the left (L) side or right (R) side of the device. Analog power, transmitter, specific to the left (L) side or right (R) side of the device. Analog power, block level clock distribution. Analog power, block level TX buffers. Analog power, TX driver, RX receiver, CDR, specific to the left (L) side or right (R) side of the device. High speed positive differential receiver channels. Specific to the left (L) side or right (R) side of the device. High speed negative differential receiver channels. Specific to the left (L) side or right (R) side of the device. High speed positive differential transmitter channels. Specific to the left (L) side or right (R) side of the device. High speed negative differential transmitter channels. Specific to the left (L) side or right (R) side of the device. Pin Name PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. I/O, Input Do Not Use No Connect Power Power Power Reference Pins Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin. Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin. Do not connect to power or ground or any other signal; must be left floating. Do not drive signals into these pins. Supply Pins VCC supplies power to the core and periphery. Digital power for PLL[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in datasheet, even if the PLL is not used. Pin Definitions Page 18 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Notes (1), (2) Pin Name REFCLK_[L,R][0:7]p GXB_CMURX_[L,R][0:7]p REFCLK_[L,R][0:7]n GXB_CMURX_[L,R][0:7]n GXB_CMUTX_[L,R][0:7]p GXB_CMUTX_[L,R][0:7]n RREF_[L,R][0:1] Pin Type (1st and 2nd Function) Input Pin Description High speed differential reference clock positive, or CMU receiver channels, specific to the left (L) side or right (R) side of the device. Input High speed differential reference clock complement, or CMU complementary receiver channel, specific to the left (L) side or right (R) side of the device. Output CMU transmitter channels, specific to the left (L) side or right (R) side of the device. Input Reference resistor for transceiver, specific to the left (L) side or right (R) side of the device. Notes: (1) These pin definitions are prepared based on the device with the largest density, HC4GX35. Refer to the pin list for the availability of pins in each density. (2) For the recommended power supply operating conditions, refer to HardCopy IV handbook and for the recommended transceiver power supply operating conditions, refer to the Stratix IV GX pin connections guidelines and datasheet. PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Pin Definitions Page 19 of 21 VREFB8AN0 VREFB8CN0 3A 3C VREFB3AN0 VREFB3CN0 PLL_T1 7C 7A VREFB7CN0 VREFB7AN0 4C 4A VREFB4CN0 VREFB4AN0 2C 2A VREFB2AN0 VREFB2CN0 PLL_L2 PLL_B1 Transceiver Block (QR1) 8C Transceiver Block (QR0) 1A 8A 1C VREFB1CN0 VREFB1AN0 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Notes: 1. This is a top view of the silicon die. For flip chip packages, the die is mounted upside down in the package; therefore, to obtain the top package view, flip this diagram on its vertical axis. 2. This is a pictorial representation only to get an idea of placement on the device. Refer to the pin list and the Quartus ® II software for exact locations. PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Bank & PLL Diagram Page 20 of 21 Pin Information for HardCopy® IV HC4GX15LAF780 Version 1.1 Version Number 1.0 1.1 Date 7/10/2009 7/30/2010 PT-HC4GX15LAF780-1.1 Copyright © 2010 Altera Corp. Changes Made Preliminary release. Initial release. Revision History Page 21 of 21