Pin-Outs

Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
VREF Group
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
Pin Name
/Function
TDI
TMS
TRST
TCK
TDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
TDI
TMS
TRST
TCK
TDO
RDN1A
RUP1A
CLKUSR
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
DIFFIO_TX_L1n
DIFFIO_TX_L1p
DIFFIO_RX_L1n
DIFFIO_RX_L1p
DIFFIO_TX_L2n
DIFFIO_TX_L2p
DIFFIO_RX_L2n
DIFFIO_RX_L2p
DIFFIO_TX_L3n
DIFFIO_TX_L3p
DIFFIO_RX_L3n
DIFFIO_RX_L3p
DIFFIO_TX_L4n
DIFFIO_TX_L4p
DIFFIO_RX_L4n
DIFFIO_RX_L4p
DIFFIO_TX_L5n
DIFFIO_TX_L5p
DIFFIO_RX_L5n
DIFFIO_RX_L5p
DIFFIO_TX_L6n
DIFFIO_TX_L6p
DIFFIO_RX_L6n
DIFFIO_RX_L6p
DIFFIO_TX_L7n
DIFFIO_TX_L7p
DIFFIO_RX_L7n
DIFFIO_RX_L7p
DIFFIO_TX_L8n
DIFFIO_TX_L8p
DIFFIO_RX_L8n
DIFFIO_RX_L8p
DIFFIO_TX_L9n
DIFFIO_TX_L9p
DIFFIO_RX_L9n
DIFFIO_RX_L9p
DIFFIO_TX_L10n
DIFFIO_TX_L10p
DIFFIO_RX_L10n
DIFFIO_RX_L10p
DIFFIO_TX_L11n
DIFFIO_TX_L11p
DIFFIO_RX_L11n
DIFFIO_RX_L11p
DIFFIO_TX_L12n
DIFFIO_TX_L12p
DIFFOUT_L1n
DIFFOUT_L1p
DIFFOUT_L2n
DIFFOUT_L2p
DIFFOUT_L3n
DIFFOUT_L3p
DIFFOUT_L4n
DIFFOUT_L4p
DIFFOUT_L5n
DIFFOUT_L5p
DIFFOUT_L6n
DIFFOUT_L6p
DIFFOUT_L7n
DIFFOUT_L7p
DIFFOUT_L8n
DIFFOUT_L8p
DIFFOUT_L9n
DIFFOUT_L9p
DIFFOUT_L10n
DIFFOUT_L10p
DIFFOUT_L11n
DIFFOUT_L11p
DIFFOUT_L12n
DIFFOUT_L12p
DIFFOUT_L13n
DIFFOUT_L13p
DIFFOUT_L14n
DIFFOUT_L14p
DIFFOUT_L15n
DIFFOUT_L15p
DIFFOUT_L16n
DIFFOUT_L16p
DIFFOUT_L17n
DIFFOUT_L17p
DIFFOUT_L18n
DIFFOUT_L18p
DIFFOUT_L19n
DIFFOUT_L19p
DIFFOUT_L20n
DIFFOUT_L20p
DIFFOUT_L21n
DIFFOUT_L21p
DIFFOUT_L22n
DIFFOUT_L22p
DIFFOUT_L23n
DIFFOUT_L23p
Pin List
F780
F24
H22
D26
C26
G24
F26
F25
C28
D27
G26
G25
B28
C27
H25
J24
D28
E28
J23
J22
F28
F27
K21
K20
G28
G27
K26
K25
J26
J25
K24
K23
H28
J27
L23
L22
J28
K27
M23
M22
L26
L25
M21
M20
K28
L28
N21
N20
M26
M25
N25
M24
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ Group for
DQS X16/X18 Mode (2)
DQ1L
DQ1L
DQSn1L
DQS1L
DQ1L
DQ1L
DQSn2L
DQS2L
DQ2L
DQ2L
DQ2L
DQ2L
DQ3L
DQ3L
DQSn3L
DQS3L
DQ3L
DQ3L
DQSn4L
DQS4L
DQ4L
DQ4L
DQ4L
DQ4L
DQ1L
DQ1L
DQ1L
DQ1L/CQn1L
DQ1L
DQ1L
DQSn1L/DQ1L
DQS1L/CQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ2L
DQ2L
DQ2L
DQ2L/CQn2L
DQ2L
DQ2L
DQSn2L/DQ2L
DQS2L/CQ2L
DQ2L
DQ2L
DQ2L
DQ2L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L/CQn1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQSn1L/DQ1L
DQS1L/CQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQSn5L
DQS5L
DQ5L
DQ5L
DQ5L
DQ5L
DQ6L
DQ6L
DQSn6L
DQS6L
DQ6L
DQ6L
DQ5L
DQ5L
DQ5L
DQ5L/CQn5L
DQ5L
DQ5L
Page 1 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
VREF Group
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK1n
CLK1p
CLK3p
CLK3n
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
PLL_L2_CLKOUT0n
PLL_L2_FB_CLKOUT0p
CLK0n
CLK0p
CLK1n
CLK1p
CLK3p
CLK3n
CLK2p
CLK2n
Configuration Function for
Stratix IV Only (1)
DATA6
DATA7
INIT_DONE
CRC_ERROR
DEV_OE
DEV_CLRn
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_L12n
DIFFIO_RX_L12p
DIFFIO_TX_L13n
DIFFIO_TX_L13p
DIFFIO_RX_L13n
DIFFIO_RX_L13p
DIFFIO_TX_L14n
DIFFIO_TX_L14p
DIFFIO_RX_L14n
DIFFIO_RX_L14p
Emulated LVDS
Output Channel (2)
DIFFOUT_L24n
DIFFOUT_L24p
DIFFOUT_L25n
DIFFOUT_L25p
DIFFOUT_L26n
DIFFOUT_L26p
DIFFOUT_L27n
DIFFOUT_L27p
DIFFOUT_L28n
DIFFOUT_L28p
DIFFIO_RX_L15p
DIFFIO_RX_L15n
DIFFIO_TX_L15p
DIFFIO_TX_L15n
DIFFIO_RX_L16p
DIFFIO_RX_L16n
DIFFIO_TX_L16p
DIFFIO_TX_L16n
DIFFIO_RX_L17p
DIFFIO_RX_L17n
DIFFIO_TX_L17p
DIFFIO_TX_L17n
DIFFIO_RX_L18p
DIFFIO_RX_L18n
DIFFIO_TX_L18p
DIFFIO_TX_L18n
DIFFIO_RX_L19p
DIFFIO_RX_L19n
DIFFIO_TX_L19p
DIFFIO_TX_L19n
DIFFIO_RX_L20p
DIFFIO_RX_L20n
DIFFIO_TX_L20p
DIFFIO_TX_L20n
DIFFIO_RX_L21p
DIFFIO_RX_L21n
DIFFIO_TX_L21p
DIFFIO_TX_L21n
DIFFIO_RX_L22p
DIFFIO_RX_L22n
DIFFIO_TX_L22p
DIFFIO_TX_L22n
DIFFIO_RX_L23p
DIFFIO_RX_L23n
DIFFIO_TX_L23p
DIFFIO_TX_L23n
DIFFIO_RX_L24p
DIFFOUT_L29p
DIFFOUT_L29n
DIFFOUT_L30p
DIFFOUT_L30n
DIFFOUT_L31p
DIFFOUT_L31n
DIFFOUT_L32p
DIFFOUT_L32n
DIFFOUT_L33p
DIFFOUT_L33n
DIFFOUT_L34p
DIFFOUT_L34n
DIFFOUT_L35p
DIFFOUT_L35n
DIFFOUT_L36p
DIFFOUT_L36n
DIFFOUT_L37p
DIFFOUT_L37n
DIFFOUT_L38p
DIFFOUT_L38n
DIFFOUT_L39p
DIFFOUT_L39n
DIFFOUT_L40p
DIFFOUT_L40n
DIFFOUT_L41p
DIFFOUT_L41n
DIFFOUT_L42p
DIFFOUT_L42n
DIFFOUT_L43p
DIFFOUT_L43n
DIFFOUT_L44p
DIFFOUT_L44n
DIFFOUT_L45p
DIFFOUT_L45n
DIFFOUT_L46p
DIFFOUT_L46n
DIFFOUT_L47p
Pin List
F780
M28
M27
N23
P23
P25
N24
P20
P19
N27
N26
N28
P28
R27
R28
U28
T28
R20
R21
R26
T27
T25
R25
V27
V28
T20
T21
V26
U26
T24
U25
W27
W28
T22
T23
V24
V25
V23
U23
AA27
Y28
W22
W23
AB27
AA28
W24
W25
Y25
Y26
V20
V21
AC28
DQ Group for
DQS X4 Mode (2)
DQSn7L
DQS7L
DQ7L
DQ7L
DQ7L
DQ7L
DQ Group for
DQS X8/X9 Mode (2)
DQSn5L/DQ5L
DQS5L/CQ5L
DQ5L
DQ5L
DQ5L
DQ5L
DQ8L
DQ8L
DQ8L
DQ8L
DQS8L
DQSn8L
DQ9L
DQ9L
DQS9L
DQSn9L
DQ9L
DQ9L
DQ10L
DQ10L
DQ10L
DQ10L
DQS10L
DQSn10L
DQ10L
DQ10L
DQ10L
DQ10L
DQS10L/CQ10L
DQSn10L/DQ10L
DQ10L
DQ10L
DQ10L/CQn10L
DQ10L
DQ10L
DQ10L
DQ11L
DQ11L
DQ11L
DQ11L
DQS11L
DQSn11L
DQ12L
DQ12L
DQS12L
DQ13L
DQ13L
DQ13L
DQ13L
DQS13L/CQ13L
DQSn13L/DQ13L
DQ13L
DQ13L
DQ13L/CQn13L
DQ Group for
DQS X16/X18 Mode (2)
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQS14L/CQ14L
Page 2 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
VREF Group
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
nCONFIG
nSTATUS
CONF_DONE
PORSEL
nCE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
RUP2A
RDN2A
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_L24n
DIFFIO_TX_L24p
DIFFIO_TX_L24n
DIFFIO_RX_L25p
DIFFIO_RX_L25n
DIFFIO_TX_L25p
DIFFIO_TX_L25n
DIFFIO_RX_L26p
DIFFIO_RX_L26n
DIFFIO_TX_L26p
DIFFIO_TX_L26n
DIFFIO_RX_L27p
DIFFIO_RX_L27n
DIFFIO_TX_L27p
DIFFIO_TX_L27n
DIFFIO_RX_L28p
DIFFIO_RX_L28n
DIFFIO_TX_L28p
DIFFIO_TX_L28n
Emulated LVDS
Output Channel (2)
DIFFOUT_L47n
DIFFOUT_L48p
DIFFOUT_L48n
DIFFOUT_L49p
DIFFOUT_L49n
DIFFOUT_L50p
DIFFOUT_L50n
DIFFOUT_L51p
DIFFOUT_L51n
DIFFOUT_L52p
DIFFOUT_L52n
DIFFOUT_L53p
DIFFOUT_L53n
DIFFOUT_L54p
DIFFOUT_L54n
DIFFOUT_L55p
DIFFOUT_L55n
DIFFOUT_L56p
DIFFOUT_L56n
nCONFIG
nSTATUS
CONF_DONE
PORSEL
nCE
RDN3A
RUP3A
DIFFIO_RX_B1n
DIFFIO_RX_B1p
DIFFIO_RX_B2n
DIFFIO_RX_B2p
DIFFIO_RX_B3n
DIFFIO_RX_B3p
DIFFIO_RX_B4n
DIFFIO_RX_B4p
DIFFIO_RX_B5n
DIFFIO_RX_B5p
DIFFIO_RX_B6n
DIFFIO_RX_B6p
DIFFIO_RX_B7n
Pin List
DIFFOUT_B1n
DIFFOUT_B1p
DIFFOUT_B2n
DIFFOUT_B2p
DIFFOUT_B3n
DIFFOUT_B3p
DIFFOUT_B4n
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B5p
DIFFOUT_B6n
DIFFOUT_B6p
DIFFOUT_B7n
DIFFOUT_B7p
DIFFOUT_B8n
DIFFOUT_B8p
DIFFOUT_B9n
DIFFOUT_B9p
DIFFOUT_B10n
DIFFOUT_B10p
DIFFOUT_B11n
DIFFOUT_B11p
DIFFOUT_B12n
DIFFOUT_B12p
DIFFOUT_B13n
DIFFOUT_B13p
DIFFOUT_B14n
F780
AB28
AA25
AA26
AB25
AB26
AC25
AC26
AD27
AD28
W20
W21
AG28
AF28
Y23
AA24
AE27
AE28
AA23
AB24
W19
AD25
AE26
AB23
Y20
AF26
AH27
AH25
AG25
AG27
AH26
AE22
AD22
AB20
AB21
AD21
AC21
AD24
AE23
AF24
AE24
AF23
AG24
AH24
AH23
AH20
AH21
AH22
AG22
AC20
AG21
AF21
DQ Group for
DQS X4 Mode (2)
DQSn12L
DQ12L
DQ12L
DQ13L
DQ13L
DQ13L
DQ13L
DQS13L
DQSn13L
DQ14L
DQ14L
DQS14L
DQSn14L
DQ14L
DQ14L
DQ Group for
DQS X8/X9 Mode (2)
DQ13L
DQ13L
DQ13L
DQ14L
DQ14L
DQ14L
DQ14L
DQS14L/CQ14L
DQSn14L/DQ14L
DQ14L
DQ14L
DQ14L/CQn14L
DQ14L
DQ14L
DQ14L
DQ Group for
DQS X16/X18 Mode (2)
DQSn14L/DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L/CQn14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ1B
DQ1B
DQSn1B
DQS1B
DQ1B
DQ1B
DQSn2B
DQS2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ3B
DQ3B
DQSn3B
DQS3B
DQ3B
DQ3B
DQSn4B
DQS4B
DQ4B
DQ4B
DQ4B
DQ4B
DQ5B
DQ5B
DQSn5B
DQ1B
DQ1B
DQ1B
DQ1B/CQn1B
DQ1B
DQ1B
DQSn1B/DQ1B
DQS1B/CQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQ2B/CQn2B
DQ2B
DQ2B
DQSn2B/DQ2B
DQS2B/CQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B/CQn1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn1B/DQ1B
DQS1B/CQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
Page 3 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
VREF Group
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_B7p
DIFFIO_RX_B8n
DIFFIO_RX_B8p
DIFFIO_RX_B9n
DIFFIO_RX_B9p
DIFFIO_RX_B10n
DIFFIO_RX_B10p
DIFFIO_RX_B11n
DIFFIO_RX_B11p
DIFFIO_RX_B12n
DIFFIO_RX_B12p
DIFFIO_RX_B13n
DIFFIO_RX_B13p
PLL_B1_CLKOUT4
PLL_B1_CLKOUT3
DIFFIO_RX_B14n
DIFFIO_RX_B14p
PLL_B1_CLKOUT0n
PLL_B1_CLKOUT0p
PLL_B1_FBn/CLKOUT2
PLL_B1_FBp/CLKOUT1
CLK5n
CLK5p
CLK4n
CLK4p
CLK6p
CLK6n
CLK7p
CLK7n
DIFFIO_RX_B15n
DIFFIO_RX_B15p
DIFFIO_RX_B16n
DIFFIO_RX_B16p
DIFFIO_RX_B17p
DIFFIO_RX_B17n
DIFFIO_RX_B18p
DIFFIO_RX_B18n
DIFFIO_RX_B19p
DIFFIO_RX_B19n
DIFFIO_RX_B20p
DIFFIO_RX_B20n
Pin List
Emulated LVDS
Output Channel (2)
DIFFOUT_B14p
DIFFOUT_B15n
DIFFOUT_B15p
DIFFOUT_B16n
DIFFOUT_B16p
DIFFOUT_B17n
DIFFOUT_B17p
DIFFOUT_B18n
DIFFOUT_B18p
DIFFOUT_B19n
DIFFOUT_B19p
DIFFOUT_B20n
DIFFOUT_B20p
DIFFOUT_B21n
DIFFOUT_B21p
DIFFOUT_B22n
DIFFOUT_B22p
DIFFOUT_B23n
DIFFOUT_B23p
DIFFOUT_B24n
DIFFOUT_B24p
DIFFOUT_B25n
DIFFOUT_B25p
DIFFOUT_B26n
DIFFOUT_B26p
DIFFOUT_B27n
DIFFOUT_B27p
DIFFOUT_B28n
DIFFOUT_B28p
DIFFOUT_B29n
DIFFOUT_B29p
DIFFOUT_B30n
DIFFOUT_B30p
DIFFOUT_B31n
DIFFOUT_B31p
DIFFOUT_B32n
DIFFOUT_B32p
DIFFOUT_B33p
DIFFOUT_B33n
DIFFOUT_B34p
DIFFOUT_B34n
DIFFOUT_B35p
DIFFOUT_B35n
DIFFOUT_B36p
DIFFOUT_B36n
DIFFOUT_B37p
DIFFOUT_B37n
DIFFOUT_B38p
DIFFOUT_B38n
DIFFOUT_B39p
DIFFOUT_B39n
F780
AE21
AF20
AE20
AD19
AC19
AB19
AA19
AE19
AD18
Y19
AA18
Y18
Y17
AF19
AG19
AH19
AG18
AH17
AH18
AF17
AE18
AE16
AD16
AF16
AE17
AC17
AB17
AC16
AB16
AA15
Y15
AH16
AG16
AH15
AG15
AF15
AE15
AE14
AF14
AG13
AH14
AG12
AH13
Y13
Y14
AD13
AE13
AA13
AB13
AG10
AH10
DQ Group for
DQS X4 Mode (2)
DQS5B
DQ5B
DQ5B
DQSn6B
DQS6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ Group for
DQS X8/X9 Mode (2)
DQ3B/CQn3B
DQ3B
DQ3B
DQSn3B/DQ3B
DQS3B/CQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ7B
DQ7B
DQSn7B
DQS7B
DQ7B
DQ7B
DQSn8B
DQS8B
DQ8B
DQ8B
DQ8B
DQ8B
DQ7B
DQ7B
DQ7B
DQ7B/CQn7B
DQ7B
DQ7B
DQSn7B/DQ7B
DQS7B/CQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ9B
DQ9B
DQS9B
DQSn9B
DQ9B
DQ9B
DQ10B
DQ10B
DQ11B
DQ11B
DQ Group for
DQS X16/X18 Mode (2)
Page 4 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
VREF Group
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
nIO_PULLUP
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_B21p
DIFFIO_RX_B21n
DIFFIO_RX_B22p
DIFFIO_RX_B22n
DIFFIO_RX_B23p
DIFFIO_RX_B23n
DIFFIO_RX_B24p
DIFFIO_RX_B24n
DIFFIO_RX_B25p
DIFFIO_RX_B25n
DIFFIO_RX_B26p
DIFFIO_RX_B26n
DIFFIO_RX_B27p
DIFFIO_RX_B27n
DIFFIO_RX_B28p
DIFFIO_RX_B28n
DIFFIO_RX_B29p
DIFFIO_RX_B29n
DIFFIO_RX_B30p
DIFFIO_RX_B30n
DIFFIO_RX_B31p
DIFFIO_RX_B31n
RUP4A
RDN4A
DIFFIO_RX_B32p
DIFFIO_RX_B32n
nIO_PULLUP
Pin List
Emulated LVDS
Output Channel (2)
DIFFOUT_B40p
DIFFOUT_B40n
DIFFOUT_B41p
DIFFOUT_B41n
DIFFOUT_B42p
DIFFOUT_B42n
DIFFOUT_B43p
DIFFOUT_B43n
DIFFOUT_B44p
DIFFOUT_B44n
DIFFOUT_B45p
DIFFOUT_B45n
DIFFOUT_B46p
DIFFOUT_B46n
DIFFOUT_B47p
DIFFOUT_B47n
DIFFOUT_B48p
DIFFOUT_B48n
DIFFOUT_B49p
DIFFOUT_B49n
DIFFOUT_B50p
DIFFOUT_B50n
DIFFOUT_B51p
DIFFOUT_B51n
DIFFOUT_B52p
DIFFOUT_B52n
DIFFOUT_B53p
DIFFOUT_B53n
DIFFOUT_B54p
DIFFOUT_B54n
DIFFOUT_B55p
DIFFOUT_B55n
DIFFOUT_B56p
DIFFOUT_B56n
DIFFOUT_B57p
DIFFOUT_B57n
DIFFOUT_B58p
DIFFOUT_B58n
DIFFOUT_B59p
DIFFOUT_B59n
DIFFOUT_B60p
DIFFOUT_B60n
DIFFOUT_B61p
DIFFOUT_B61n
DIFFOUT_B62p
DIFFOUT_B62n
DIFFOUT_B63p
DIFFOUT_B63n
DIFFOUT_B64p
DIFFOUT_B64n
F780
AH11
AH12
AF10
AF11
AF12
AC12
AD12
AE12
AC11
AE11
AB11
AC10
Y10
Y11
AG9
AH8
AE10
AH9
AE9
AF9
AF8
AE8
AG7
AH7
AG6
AH6
AG4
AH3
AH4
AH5
AG3
AH2
AD9
AC9
AA9
AB9
Y9
AA10
AE6
AF6
AE4
AE7
AE5
AF5
AB8
AC8
AC7
AD7
AB7
AD6
AE3
DQ Group for
DQS X4 Mode (2)
DQ10B
DQ10B
DQS10B
DQSn10B
DQ11B
DQ11B
DQS11B
DQSn11B
DQ11B
DQ11B
DQ Group for
DQS X8/X9 Mode (2)
DQ11B
DQ11B
DQS11B/CQ11B
DQSn11B/DQ11B
DQ11B
DQ11B
DQ11B/CQn11B
DQ11B
DQ11B
DQ11B
DQ12B
DQ12B
DQ12B
DQ12B
DQS12B
DQSn12B
DQ13B
DQ13B
DQS13B
DQSn13B
DQ13B
DQ13B
DQ14B
DQ14B
DQ14B
DQ14B
DQS14B
DQSn14B
DQ15B
DQ15B
DQS15B
DQSn15B
DQ15B
DQ15B
DQ16B
DQ16B
DQ16B
DQ16B
DQS16B
DQSn16B
DQ17B
DQ17B
DQS17B
DQSn17B
DQ17B
DQ17B
DQ15B
DQ15B
DQ15B
DQ15B
DQS15B/CQ15B
DQSn15B/DQ15B
DQ15B
DQ15B
DQ15B/CQn15B
DQ15B
DQ15B
DQ15B
DQ16B
DQ16B
DQ16B
DQ16B
DQS16B/CQ16B
DQSn16B/DQ16B
DQ16B
DQ16B
DQ16B/CQn16B
DQ16B
DQ16B
DQ16B
DQ17B
DQ17B
DQ17B
DQ17B
DQS17B/CQ17B
DQSn17B/DQ17B
DQ17B
DQ17B
DQ17B/CQn17B
DQ17B
DQ17B
DQ17B
DQ Group for
DQS X16/X18 Mode (2)
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQS17B/CQ17B
DQSn17B/DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B/CQn17B
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQ17B
Page 5 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
VREF Group
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
Pin Name
/Function
nCEO
DCLK
nCSO
ASDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
RDN5A
RUP5A
Configuration Function for
Stratix IV Only (1)
nCEO
DCLK
nCSO
ASDO
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
DIFFIO_TX_R1n
DIFFIO_TX_R1p
DIFFIO_RX_R1n
DIFFIO_RX_R1p
DIFFIO_TX_R2n
DIFFIO_TX_R2p
DIFFIO_RX_R2n
DIFFIO_RX_R2p
DIFFIO_TX_R3n
DIFFIO_TX_R3p
DIFFIO_RX_R3n
DIFFIO_RX_R3p
DIFFIO_TX_R4n
DIFFIO_TX_R4p
DIFFIO_RX_R4n
DIFFIO_RX_R4p
DIFFIO_TX_R5n
DIFFIO_TX_R5p
DIFFIO_RX_R5n
DIFFIO_RX_R5p
DIFFIO_TX_R6n
DIFFIO_TX_R6p
DIFFIO_RX_R6n
DIFFIO_RX_R6p
DIFFIO_TX_R7n
DIFFIO_TX_R7p
DIFFIO_RX_R7n
DIFFIO_RX_R7p
DIFFIO_TX_R8n
DIFFIO_TX_R8p
DIFFIO_RX_R8n
DIFFIO_RX_R8p
DIFFIO_TX_R9n
DIFFIO_TX_R9p
DIFFIO_RX_R9n
DIFFIO_RX_R9p
DIFFIO_TX_R10n
DIFFIO_TX_R10p
DIFFIO_RX_R10n
DIFFIO_RX_R10p
DIFFIO_TX_R11n
DIFFIO_TX_R11p
DIFFIO_RX_R11n
DIFFIO_RX_R11p
DIFFIO_TX_R12n
DIFFIO_TX_R12p
DIFFIO_RX_R12n
DIFFOUT_R1n
DIFFOUT_R1p
DIFFOUT_R2n
DIFFOUT_R2p
DIFFOUT_R3n
DIFFOUT_R3p
DIFFOUT_R4n
DIFFOUT_R4p
DIFFOUT_R5n
DIFFOUT_R5p
DIFFOUT_R6n
DIFFOUT_R6p
DIFFOUT_R7n
DIFFOUT_R7p
DIFFOUT_R8n
DIFFOUT_R8p
DIFFOUT_R9n
DIFFOUT_R9p
DIFFOUT_R10n
DIFFOUT_R10p
DIFFOUT_R11n
DIFFOUT_R11p
DIFFOUT_R12n
DIFFOUT_R12p
DIFFOUT_R13n
DIFFOUT_R13p
DIFFOUT_R14n
DIFFOUT_R14p
DIFFOUT_R15n
DIFFOUT_R15p
DIFFOUT_R16n
DIFFOUT_R16p
DIFFOUT_R17n
DIFFOUT_R17p
DIFFOUT_R18n
DIFFOUT_R18p
DIFFOUT_R19n
DIFFOUT_R19p
DIFFOUT_R20n
DIFFOUT_R20p
DIFFOUT_R21n
DIFFOUT_R21p
DIFFOUT_R22n
DIFFOUT_R22p
DIFFOUT_R23n
DIFFOUT_R23p
DIFFOUT_R24n
Pin List
F780
AB5
AC5
AD4
AA6
AC3
AC4
AF1
AE2
AB3
AB4
AG1
AF2
Y6
Y7
AE1
AD1
AA4
Y5
AC1
AC2
Y3
Y4
AB1
AB2
W8
W9
AA1
Y2
W5
W6
Y1
W2
V6
V7
W3
W4
U6
U7
V3
V4
U8
U9
W1
V1
T4
U5
U3
U4
T8
T9
T2
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ Group for
DQS X16/X18 Mode (2)
DQ1R
DQ1R
DQSn1R
DQS1R
DQ1R
DQ1R
DQSn2R
DQS2R
DQ2R
DQ2R
DQ2R
DQ2R
DQ3R
DQ3R
DQSn3R
DQS3R
DQ3R
DQ3R
DQSn4R
DQS4R
DQ4R
DQ4R
DQ4R
DQ4R
DQ1R
DQ1R
DQ1R
DQ1R/CQn1R
DQ1R
DQ1R
DQSn1R/DQ1R
DQS1R/CQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ2R
DQ2R
DQ2R
DQ2R/CQn2R
DQ2R
DQ2R
DQSn2R/DQ2R
DQS2R/CQ2R
DQ2R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R/CQn1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn1R/DQ1R
DQS1R/CQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn5R
DQS5R
DQ5R
DQ5R
DQ5R
DQ5R
DQ6R
DQ6R
DQSn6R
DQS6R
DQ6R
DQ6R
DQSn7R
DQ5R
DQ5R
DQ5R
DQ5R/CQn5R
DQ5R
DQ5R
DQSn5R/DQ5R
Page 6 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREF Group
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK8n
CLK8p
CLK10p
CLK10n
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
CLK9n
CLK9p
CLK8n
CLK8p
CLK10p
CLK10n
CLK11p
CLK11n
PLL_R2_FB_CLKOUT0p
PLL_R2_CLKOUT0n
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_R12p
DIFFIO_TX_R13n
DIFFIO_TX_R13p
DIFFIO_RX_R13n
DIFFIO_RX_R13p
DIFFIO_TX_R14n
DIFFIO_TX_R14p
DIFFIO_RX_R14n
DIFFIO_RX_R14p
Emulated LVDS
Output Channel (2)
DIFFOUT_R24p
DIFFOUT_R25n
DIFFOUT_R25p
DIFFOUT_R26n
DIFFOUT_R26p
DIFFOUT_R27n
DIFFOUT_R27p
DIFFOUT_R28n
DIFFOUT_R28p
DIFFIO_RX_R15p
DIFFIO_RX_R15n
DIFFIO_TX_R15p
DIFFIO_TX_R15n
DIFFIO_RX_R16p
DIFFIO_RX_R16n
DIFFIO_TX_R16p
DIFFIO_TX_R16n
DIFFIO_RX_R17p
DIFFIO_RX_R17n
DIFFIO_TX_R17p
DIFFIO_TX_R17n
DIFFIO_RX_R18p
DIFFIO_RX_R18n
DIFFIO_TX_R18p
DIFFIO_TX_R18n
DIFFIO_RX_R19p
DIFFIO_RX_R19n
DIFFIO_TX_R19p
DIFFIO_TX_R19n
DIFFIO_RX_R20p
DIFFIO_RX_R20n
DIFFIO_TX_R20p
DIFFIO_TX_R20n
DIFFIO_RX_R21p
DIFFIO_RX_R21n
DIFFIO_TX_R21p
DIFFIO_TX_R21n
DIFFIO_RX_R22p
DIFFIO_RX_R22n
DIFFIO_TX_R22p
DIFFIO_TX_R22n
DIFFIO_RX_R23p
DIFFIO_RX_R23n
DIFFIO_TX_R23p
DIFFIO_TX_R23n
DIFFIO_RX_R24p
DIFFIO_RX_R24n
DIFFOUT_R29p
DIFFOUT_R29n
DIFFOUT_R30p
DIFFOUT_R30n
DIFFOUT_R31p
DIFFOUT_R31n
DIFFOUT_R32p
DIFFOUT_R32n
DIFFOUT_R33p
DIFFOUT_R33n
DIFFOUT_R34p
DIFFOUT_R34n
DIFFOUT_R35p
DIFFOUT_R35n
DIFFOUT_R36p
DIFFOUT_R36n
DIFFOUT_R37p
DIFFOUT_R37n
DIFFOUT_R38p
DIFFOUT_R38n
DIFFOUT_R39p
DIFFOUT_R39n
DIFFOUT_R40p
DIFFOUT_R40n
DIFFOUT_R41p
DIFFOUT_R41n
DIFFOUT_R42p
DIFFOUT_R42n
DIFFOUT_R43p
DIFFOUT_R43n
DIFFOUT_R44p
DIFFOUT_R44n
DIFFOUT_R45p
DIFFOUT_R45n
DIFFOUT_R46p
DIFFOUT_R46n
DIFFOUT_R47p
DIFFOUT_R47n
Pin List
F780
T3
T6
R6
R4
T5
R9
R10
U1
U2
T1
R1
P2
P1
M1
N1
P9
P8
N4
P4
N7
N6
P3
N2
N5
M4
L2
L1
N9
N8
L3
M3
L5
L4
K2
K1
L6
M6
H2
J1
K7
K6
G2
H1
K5
K4
F1
G1
J4
J3
E2
E1
DQ Group for
DQS X4 Mode (2)
DQS7R
DQ7R
DQ7R
DQ7R
DQ7R
DQ Group for
DQS X8/X9 Mode (2)
DQS5R/CQ5R
DQ5R
DQ5R
DQ5R
DQ5R
DQ8R
DQ8R
DQ8R
DQ8R
DQS8R
DQSn8R
DQ9R
DQ9R
DQS9R
DQSn9R
DQ9R
DQ9R
DQ10R
DQ10R
DQ10R
DQ10R
DQS10R
DQSn10R
DQ10R
DQ10R
DQ10R
DQ10R
DQS10R/CQ10R
DQSn10R/DQ10R
DQ10R
DQ10R
DQ10R/CQn10R
DQ10R
DQ10R
DQ10R
DQ11R
DQ11R
DQ11R
DQ11R
DQS11R
DQSn11R
DQ12R
DQ12R
DQS12R
DQSn12R
DQ13R
DQ13R
DQ13R
DQ13R
DQS13R/CQ13R
DQSn13R/DQ13R
DQ13R
DQ13R
DQ13R/CQn13R
DQ13R
DQ Group for
DQS X16/X18 Mode (2)
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQS14R/CQ14R
DQSn14R/DQ14R
Page 7 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
VREF Group
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
RUP6A
RDN6A
RDN7A
RUP7A
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_TX_R24p
DIFFIO_TX_R24n
DIFFIO_RX_R25p
DIFFIO_RX_R25n
DIFFIO_TX_R25p
DIFFIO_TX_R25n
DIFFIO_RX_R26p
DIFFIO_RX_R26n
DIFFIO_TX_R26p
DIFFIO_TX_R26n
DIFFIO_RX_R27p
DIFFIO_RX_R27n
DIFFIO_TX_R27p
DIFFIO_TX_R27n
DIFFIO_RX_R28p
DIFFIO_RX_R28n
DIFFIO_TX_R28p
DIFFIO_TX_R28n
DIFFIO_RX_T1n
DIFFIO_RX_T1p
DIFFIO_RX_T2n
DIFFIO_RX_T2p
DIFFIO_RX_T3n
DIFFIO_RX_T3p
DIFFIO_RX_T4n
DIFFIO_RX_T4p
DIFFIO_RX_T5n
DIFFIO_RX_T5p
DIFFIO_RX_T6n
DIFFIO_RX_T6p
DIFFIO_RX_T7n
DIFFIO_RX_T7p
DIFFIO_RX_T8n
DIFFIO_RX_T8p
Pin List
Emulated LVDS
Output Channel (2)
DIFFOUT_R48p
DIFFOUT_R48n
DIFFOUT_R49p
DIFFOUT_R49n
DIFFOUT_R50p
DIFFOUT_R50n
DIFFOUT_R51p
DIFFOUT_R51n
DIFFOUT_R52p
DIFFOUT_R52n
DIFFOUT_R53p
DIFFOUT_R53n
DIFFOUT_R54p
DIFFOUT_R54n
DIFFOUT_R55p
DIFFOUT_R55n
DIFFOUT_R56p
DIFFOUT_R56n
DIFFOUT_T1n
DIFFOUT_T1p
DIFFOUT_T2n
DIFFOUT_T2p
DIFFOUT_T3n
DIFFOUT_T3p
DIFFOUT_T4n
DIFFOUT_T4p
DIFFOUT_T5n
DIFFOUT_T5p
DIFFOUT_T6n
DIFFOUT_T6p
DIFFOUT_T7n
DIFFOUT_T7p
DIFFOUT_T8n
DIFFOUT_T8p
DIFFOUT_T9n
DIFFOUT_T9p
DIFFOUT_T10n
DIFFOUT_T10p
DIFFOUT_T11n
DIFFOUT_T11p
DIFFOUT_T12n
DIFFOUT_T12p
DIFFOUT_T13n
DIFFOUT_T13p
DIFFOUT_T14n
DIFFOUT_T14p
DIFFOUT_T15n
DIFFOUT_T15p
DIFFOUT_T16n
DIFFOUT_T16p
DIFFOUT_T17n
F780
L9
L8
H4
H3
K9
K8
D2
D1
J6
H5
F4
F3
G4
G3
B1
C1
H6
G5
A2
C3
A4
B4
A3
B2
D7
E7
G8
G9
E8
F8
D6
E5
C5
D5
B5
C6
A5
A6
A8
A9
A7
B7
B8
F9
C8
D8
D9
C9
E10
F10
H10
DQ Group for
DQS X4 Mode (2)
DQ12R
DQ12R
DQ13R
DQ13R
DQ13R
DQ13R
DQS13R
DQSn13R
DQ14R
DQ14R
DQS14R
DQSn14R
DQ14R
DQ14R
DQ Group for
DQS X8/X9 Mode (2)
DQ13R
DQ13R
DQ14R
DQ14R
DQ14R
DQ14R
DQS14R/CQ14R
DQSn14R/DQ14R
DQ14R
DQ14R
DQ14R/CQn14R
DQ14R
DQ14R
DQ14R
DQ Group for
DQS X16/X18 Mode (2)
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R/CQn14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ1T
DQ1T
DQSn1T
DQS1T
DQ1T
DQ1T
DQSn2T
DQS2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ3T
DQ3T
DQSn3T
DQS3T
DQ3T
DQ3T
DQSn4T
DQS4T
DQ4T
DQ4T
DQ4T
DQ4T
DQ5T
DQ5T
DQSn5T
DQS5T
DQ5T
DQ5T
DQSn6T
DQS6T
DQ6T
DQ1T
DQ1T
DQ1T
DQ1T/CQn1T
DQ1T
DQ1T
DQSn1T/DQ1T
DQS1T/CQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ2T
DQ2T
DQ2T
DQ2T/CQn2T
DQ2T
DQ2T
DQSn2T/DQ2T
DQS2T/CQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ3T
DQ3T
DQ3T
DQ3T/CQn3T
DQ3T
DQ3T
DQSn3T/DQ3T
DQS3T/CQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T/CQn1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQSn1T/DQ1T
DQS1T/CQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
Page 8 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
7A
7A
7A
7A
7A
7A
7A
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
VREF Group
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_T9n
DIFFIO_RX_T9p
DIFFIO_RX_T10n
DIFFIO_RX_T10p
DIFFIO_RX_T11n
DIFFIO_RX_T11p
DIFFIO_RX_T12n
DIFFIO_RX_T12p
DIFFIO_RX_T13n
DIFFIO_RX_T13p
DIFFIO_RX_T14n
DIFFIO_RX_T14p
DIFFIO_RX_T15n
DIFFIO_RX_T15p
CLK13n
CLK13p
CLK12n
CLK12p
CLK14p
CLK14n
CLK15p
CLK15n
PLL_T1_FBp/CLKOUT1
PLL_T1_FBn/CLKOUT2
PLL_T1_CLKOUT0p
PLL_T1_CLKOUT0n
DIFFIO_RX_T16n
DIFFIO_RX_T16p
DIFFIO_RX_T17p
DIFFIO_RX_T17n
DIFFIO_RX_T18p
DIFFIO_RX_T18n
DIFFIO_RX_T19p
DIFFIO_RX_T19n
PLL_T1_CLKOUT3
PLL_T1_CLKOUT4
DIFFIO_RX_T20p
DIFFIO_RX_T20n
DIFFIO_RX_T21p
DIFFIO_RX_T21n
Pin List
Emulated LVDS
Output Channel (2)
DIFFOUT_T17p
DIFFOUT_T18n
DIFFOUT_T18p
DIFFOUT_T19n
DIFFOUT_T19p
DIFFOUT_T20n
DIFFOUT_T20p
DIFFOUT_T21n
DIFFOUT_T21p
DIFFOUT_T22n
DIFFOUT_T22p
DIFFOUT_T23n
DIFFOUT_T23p
DIFFOUT_T24n
DIFFOUT_T24p
DIFFOUT_T25n
DIFFOUT_T25p
DIFFOUT_T26n
DIFFOUT_T26p
DIFFOUT_T27n
DIFFOUT_T27p
DIFFOUT_T28n
DIFFOUT_T28p
DIFFOUT_T29n
DIFFOUT_T29p
DIFFOUT_T30n
DIFFOUT_T30p
DIFFOUT_T31n
DIFFOUT_T31p
DIFFOUT_T32n
DIFFOUT_T32p
DIFFOUT_T33p
DIFFOUT_T33n
DIFFOUT_T34p
DIFFOUT_T34n
DIFFOUT_T35p
DIFFOUT_T35n
DIFFOUT_T36p
DIFFOUT_T36n
DIFFOUT_T37p
DIFFOUT_T37n
DIFFOUT_T38p
DIFFOUT_T38n
DIFFOUT_T39p
DIFFOUT_T39n
DIFFOUT_T40p
DIFFOUT_T40n
DIFFOUT_T41p
DIFFOUT_T41n
DIFFOUT_T42p
DIFFOUT_T42n
F780
G10
D10
E11
H11
J10
J11
J12
B10
C10
A10
B11
A11
A12
C12
D11
E13
D13
C13
D12
G12
F12
F13
G13
H14
J14
A13
B13
A14
B14
C14
D14
D15
C15
B16
A15
B17
A16
J16
J15
E16
D16
G16
H16
B19
A19
A17
A18
C19
C18
F17
C17
DQ Group for
DQS X4 Mode (2)
DQ6T
DQ6T
DQ6T
DQ Group for
DQS X8/X9 Mode (2)
DQ3T
DQ3T
DQ3T
DQ7T
DQ7T
DQSn7T
DQS7T
DQ7T
DQ7T
DQSn8T
DQS8T
DQ8T
DQ8T
DQ8T
DQ8T
DQ9T
DQ9T
DQSn9T
DQS9T
DQ9T
DQ9T
DQ7T
DQ7T
DQ7T
DQ7T/CQn7T
DQ7T
DQ7T
DQSn7T/DQ7T
DQS7T/CQ7T
DQ7T
DQ7T
DQ7T
DQ7T
DQ10T
DQ10T
DQ10T
DQ10T
DQS10T
DQSn10T
DQ11T
DQ11T
DQ11T
DQ11T
DQ11T
DQ11T
DQS11T/CQ11T
DQSn11T/DQ11T
DQ11T
DQ11T
DQ Group for
DQS X16/X18 Mode (2)
Page 9 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
8C
8C
8C
8C
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
VREF Group
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
GND
GND
GND
GND
GND
GND
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_T22p
DIFFIO_RX_T22n
DIFFIO_RX_T23p
DIFFIO_RX_T23n
DIFFIO_RX_T24p
DIFFIO_RX_T24n
DIFFIO_RX_T25p
DIFFIO_RX_T25n
DIFFIO_RX_T26p
DIFFIO_RX_T26n
DIFFIO_RX_T27p
DIFFIO_RX_T27n
DIFFIO_RX_T28p
DIFFIO_RX_T28n
DIFFIO_RX_T29p
DIFFIO_RX_T29n
DIFFIO_RX_T30p
DIFFIO_RX_T30n
DIFFIO_RX_T31p
DIFFIO_RX_T31n
RUP8A
RDN8A
DIFFIO_RX_T32p
DIFFIO_RX_T32n
Pin List
Emulated LVDS
Output Channel (2)
DIFFOUT_T43p
DIFFOUT_T43n
DIFFOUT_T44p
DIFFOUT_T44n
DIFFOUT_T45p
DIFFOUT_T45n
DIFFOUT_T46p
DIFFOUT_T46n
DIFFOUT_T47p
DIFFOUT_T47n
DIFFOUT_T48p
DIFFOUT_T48n
DIFFOUT_T49p
DIFFOUT_T49n
DIFFOUT_T50p
DIFFOUT_T50n
DIFFOUT_T51p
DIFFOUT_T51n
DIFFOUT_T52p
DIFFOUT_T52n
DIFFOUT_T53p
DIFFOUT_T53n
DIFFOUT_T54p
DIFFOUT_T54n
DIFFOUT_T55p
DIFFOUT_T55n
DIFFOUT_T56p
DIFFOUT_T56n
DIFFOUT_T57p
DIFFOUT_T57n
DIFFOUT_T58p
DIFFOUT_T58n
DIFFOUT_T59p
DIFFOUT_T59n
DIFFOUT_T60p
DIFFOUT_T60n
DIFFOUT_T61p
DIFFOUT_T61n
DIFFOUT_T62p
DIFFOUT_T62n
DIFFOUT_T63p
DIFFOUT_T63n
DIFFOUT_T64p
DIFFOUT_T64n
F780
E17
D17
D18
F18
G18
F19
J18
J19
B20
A21
A20
D19
D20
C20
D21
C21
B22
A22
A23
B23
B25
A26
A24
A25
B26
A27
F20
E20
H20
G20
H19
J20
D23
C23
D22
D25
D24
C24
F21
G21
F22
E22
E23
G22
M17
AF3
R14
K11
B24
AG2
AG5
DQ Group for
DQS X4 Mode (2)
DQS11T
DQSn11T
DQ11T
DQ11T
DQ Group for
DQS X8/X9 Mode (2)
DQ11T/CQn11T
DQ11T
DQ11T
DQ11T
DQ12T
DQ12T
DQ12T
DQ12T
DQS12T
DQSn12T
DQ13T
DQ13T
DQS13T
DQSn13T
DQ13T
DQ13T
DQ14T
DQ14T
DQ14T
DQ14T
DQS14T
DQSn14T
DQ15T
DQ15T
DQS15T
DQSn15T
DQ15T
DQ15T
DQ16T
DQ16T
DQ16T
DQ16T
DQS16T
DQSn16T
DQ17T
DQ17T
DQS17T
DQSn17T
DQ17T
DQ17T
DQ15T
DQ15T
DQ15T
DQ15T
DQS15T/CQ15T
DQSn15T/DQ15T
DQ15T
DQ15T
DQ15T/CQn15T
DQ15T
DQ15T
DQ15T
DQ16T
DQ16T
DQ16T
DQ16T
DQS16T/CQ16T
DQSn16T/DQ16T
DQ16T
DQ16T
DQ16T/CQn16T
DQ16T
DQ16T
DQ16T
DQ17T
DQ17T
DQ17T
DQ17T
DQS17T/CQ17T
DQSn17T/DQ17T
DQ17T
DQ17T
DQ17T/CQn17T
DQ17T
DQ17T
DQ17T
DQ Group for
DQS X16/X18 Mode (2)
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQS17T/CQ17T
DQSn17T/DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T/CQn17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ17T
Page 10 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
Pin List
Emulated LVDS
Output Channel (2)
F780
AG8
AG11
AG14
AG17
AG20
AG23
AG26
AF27
AD2
AD5
AD8
AD11
AD14
AD17
AD20
AD23
AC24
AC27
AA2
AA5
AA8
AA11
AA14
AA17
AA20
Y12
Y16
Y21
Y24
Y27
W12
W14
W16
W18
V2
V5
V8
V11
V13
V15
V17
V19
U10
U12
U14
U16
U18
U21
U24
U27
T11
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ Group for
DQS X16/X18 Mode (2)
Page 11 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
Pin List
Emulated LVDS
Output Channel (2)
F780
T13
T15
T17
T19
R2
R5
R8
R12
R16
R18
P11
P13
P17
P21
P24
P27
N10
N12
N14
N16
N18
M2
M5
M8
M11
M13
M15
M19
L10
L12
L14
L16
L18
L21
L24
L27
K13
K15
K17
K19
J2
J5
J8
J13
J17
H9
H12
H15
H18
H21
H24
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ Group for
DQS X16/X18 Mode (2)
Page 12 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
Pin List
Emulated LVDS
Output Channel (2)
F780
H27
F2
F5
E6
E9
E12
E15
E18
E21
E24
E27
C2
B3
B6
B9
B12
B15
B18
B21
B27
R15
L17
V14
V18
U11
U13
U15
U17
T12
T14
T16
R13
R17
P12
P14
P16
P18
N13
N15
N17
M12
M14
M16
L11
T18
V12
V16
R11
N11
M18
L13
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ Group for
DQS X16/X18 Mode (2)
Page 13 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
VCC
DNU
VCCPGM
VCCPGM
TEMPDIODEn
TEMPDIODEp
VCC_CLKIN3C
VCC_CLKIN4C
VCC_CLKIN7C
VCC_CLKIN8C
VCCA_PLL_B1
VCCA_PLL_L2
VCCA_PLL_R2
VCCA_PLL_T1
VCCD_PLL_B1
VCCD_PLL_L2
VCCD_PLL_R2
VCCD_PLL_T1
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1C
VCCIO1C
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2C
VCCIO2C
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3C
VCCIO3C
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4C
VCCIO4C
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5C
VCCIO5C
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6C
VCCIO6C
VCCIO7A
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
Pin List
Emulated LVDS
Output Channel (2)
F780
L15
P15
AA21
Y8
D4
D3
AB14
AC13
F14
F16
AC14
R22
R7
F15
AB15
P22
P7
G15
E26
H23
H26
P26
R23
W26
AD26
AA22
T26
V22
AC22
AF22
AF25
AC18
AF18
AC15
AC6
AF4
AF7
AD10
AB12
AF13
AA7
AD3
AA3
P6
R3
E3
K3
H7
L7
N3
C7
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ Group for
DQS X16/X18 Mode (2)
Page 14 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
VREF Group
1A
1C
2A
2C
3A
3C
4A
4C
5A
5C
6A
6C
7A
7C
8A
8C
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3CN0
VREFB4AN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
VREFB6CN0
VREFB7AN0
VREFB7CN0
VREFB8AN0
VREFB8CN0
Pin Name
/Function
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7C
VCCIO7C
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8C
VCCIO8C
VCCPD1A
VCCPD1C
VCCPD2A
VCCPD2C
VCCPD3A
VCCPD3C
VCCPD4A
VCCPD4C
VCCPD5A
VCCPD5C
VCCPD6A
VCCPD6C
VCCPD7A
VCCPD7C
VCCPD8A
VCCPD8C
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3CN0
VREFB4AN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
VREFB6CN0
VREFB7AN0
VREFB7CN0
VREFB8AN0
VREFB8CN0
NC
NC
NC
NC
NC
NC (4)
NC (5)
NC (5)
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3CN0
VREFB4AN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
VREFB6CN0
VREFB7AN0
VREFB7CN0
VREFB8AN0
VREFB8CN0
Pin List
Emulated LVDS
Output Channel (2)
F780
F7
F11
C4
C11
G14
C25
F23
E19
C22
C16
G17
L19
N19
U19
R19
W17
W15
W11
W13
V10
T10
M10
P10
K12
K14
K18
K16
K22
N22
Y22
U22
AB18
AA16
AB10
AA12
W7
T7
J7
M7
G11
H13
G19
H17
E25
AB22
W10
E4
V9
F6
R24
AD15
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ Group for
DQS X16/X18 Mode (2)
Page 15 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
NC (5)
NC (5)
NC
NC (5)
NC (5)
NC
NC
NC
NC (3)
NC (3)
NC (3)
VCCAUX
VCCAUX
VCCAUX
VCCAUX
Optional
Function(s)
Configuration Function for
Stratix IV Only (1)
Dedicated Tx_Rx
Channel (2)
MSEL2
MSEL1
MSEL0
Emulated LVDS
Output Channel (2)
F780
P5
E14
AE25
U20
M9
L20
K10
J21
G7
J9
H8
G23
AC23
AB6
G6
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ Group for
DQS X16/X18 Mode (2)
Notes:
(1) These pins should be connected on the board to properly configure the FPGA prototype. See Stratix ® IV device pin table for details.
(2) The individual index number of the pin in this column may not be the same as its companion Stratix IV device, but the functionality of the pin is fully migratable.
(3) These NO CONNECT (NC) pins are MSEL configuration input pins in the Stratix IV device and should be connected on the board to configure the FPGA prototype.
(4) This NC pin is a VCCBAT pin in the Stratix IV device and should be connected for the FPGA prototype.
(5) This NC pin is a VCCPT pin in the Stratix IV device and should be connected for the FPGA prototype.
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Pin List
Page 16 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Notes (1), (2)
Pin Name
Pin Type (1st and 2nd
Function)
Pin Description
CLK[1,3,8,10]p
Clock, Input
Clock and PLL Pins
Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins.
CLK[1,3,8,10]n
CLK[0,2,9,11]p
CLK[0,2,9,11]n
Clock, Input
I/O, Clock
I/O, Clock
Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins.
These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these pins.
These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is supported on these pins.
CLK[4:7,12:15]p
CLK[4:7,12:15]n
PLL_[L1,L4,R1,R4]_CLKp
PLL_[L1,L4,R1,R4]_CLKn
PLL_[L1, L2, L3, L4]_CLKOUT0n
PLL_[R1, R2, R3, R4]_CLKOUT0n
PLL_[L1, L2, ,L3, L4]_FB_CLKOUT0p
PLL_[T1,T2,B1,B2]_FBp/CLKOUT1
PLL_[T1,T2,B1,B2]_FBn/CLKOUT2
PLL_[T1,T2,B1,B2]_CLKOUT[3,4]
PLL_[T1,T2,B1,B2]_CLKOUT0p
PLL_[T1,T2,B1,B2]_CLKOUT0n
I/O, Clock
I/O, Clock
Clock, Input
Clock, Input
I/O, Clock
These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins.
These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins.
Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively.
Dedicated negative clock input pins for differential clock input to PLL L1, L4, R1, and R4 respectively.
Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can
be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin.
I/O, Clock
I/O, Clock
I/O, Clock
I/O, Clock
I/O, Clock
I/O, Clock
nIO_PULLUP
Input
TEMPDIODEp
Input
TEMPDIODEn
nCE
nCONFIG
Input
Input
Input
CONF_DONE
Bidirectional
(open-drain)
Output
Bidirectional
(open-drain)
nCEO
Nstatus
PORSEL
TCK
TMS
TDI
TDO
TRST
Input
Input
Input
Input
Output
Input
nCSO
ASDO
DCLK
Output
Output
Input (PS, FPP)
Output (AS)
DIFFIO_RX[##]p,
DIFFIO_RX[##]n
DIFFIO_TX[##]p,
DIFFIO_TX[##]n
DIFFOUT_[##]p,
DIFFOUT_[##]n
I/O, RX channel
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
I/O, TX channel
I/O, TX channel
Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin.
These pins can be used as I/O pins or two single-ended clock output pins.
I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.
Dedicated Configuration/JTAG Pins
Dedicated input that chooses whether the internal pull-up resistors on the user I/O pins are on or off during power up. A logic high turns off the weak pull-ups, while a logic low turns them
on.
Pin used in conjunction with the temperature sensing diode (bias-high input) inside the HardCopy IV device.
Pin used in conjunction with the temperature sensing diode (bias-low input) inside the HardCopy IV device.
Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled.
Dedicated power up block control input. Pulling this pin low during user-mode will cause the HardCopy IV to enter a reset state and tri-state all I/O pins. Returning this pin to a logic high
level will initiate the power up and initialization sequence. It is not available as a user I/O pin.
This is a dedicated power up block status pin. As a status output, the CONF_DONE pin drives low before and during initialization. Driven this pin high indicates that the device is entering
user mode.
Output that drives low when device initialization is complete.
This is a dedicated power up block status pin. The HardCopy IV drives nSTATUS low indicates that the device is being initialized. As a status output, the nSTATUS is pulled low if an
error occurs during initialization. As a status input, this pin delays the completion of the Initialization phase when nSTATUS is driven low by an external source during initialization. It is not
available as a user I/O pin.
Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high selects a POR time of 12 ms and a logic low selects POR time of 100 ms.
Dedicated JTAG input pin.
Dedicated JTAG input pin.
Dedicated JTAG input pin.
Dedicated JTAG output pin.
Dedicated active low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit.
Optional/Dual-Purpose Configuration Pins
Dedicated control signal from Stratix IV devices, but kept in HardCopy IV for compatibility reasons.
Dedicated control signal from Stratix IV devices, but kept in HardCopy IV for compatibility reasons.
Dedicated configuration clock pin on Stratix IV devices, but kept in HardCopy IV for compatibility reasons. It's not required to clock this pin for HardCopy IV.
Differential I/O Pins
These are true LVDS receiver channels on side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative
signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.
These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for
the differential channel. If not used for differential signaling, these pins are available as user I/O pins.
These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with
true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the
negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.
Pin Definitions
Page 17 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Notes (1), (2)
Pin Type (1st and 2nd
Function)
Pin Description
DQS[1:38][T,B],
DQS[1:34][L,R]
I/O,DQS
External Memory Interface Pins
Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic.
DQSn[1:38][T,B],
DQSn[1:34][L,R]
I/O,DQSn
Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry.
DQ[1:38][T,B],
DQ[1:34][L,R]
I/O,DQ
Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if
you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list.
CQ[1:38][T,B],
CQ[1:34][L,R]
DQS
Optional data strobe signal for use in QDR II SRAM. These are the pins for echo clocks.
CQn[1:38][T,B],
CQn[1:34][L,R]
DQS
Optional complementary data strobe signal for use in QDR II SRAM. These are the pins for echo clocks.
RUP[1:8]A,
RUP[3,8]C
RDN[1:8]A,
RDN[3,8]C
I/O, Input
Pin Name
I/O, Input
DNU
NC
Do Not Use
No Connect
VCC
VCCD_PLL_[L,R][1:4],
VCCD_PLL_[T,B][1:2]
VCCA_PLL_[L,R][1:4],
VCCA_PLL_[T,B][1:2]
VCCAUX
VCCIO[1:8][A,B,C]
Power
Power
Power
Power
VCCPGM
VCCPD[1:8][A,B,C]
VCC_CLKIN[3,4,7,8]C
GND
VREFB[1:8][A,B,C]N0
Power
Power
Power
Ground
Power
Power
Reference Pins
Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated
RUP pin within the bank. If not required, this pin is a regular I/O pin.
Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated
RDN pin within the bank. If not required, this pin is a regular I/O pin.
Do not connect to power or ground or any other signal; must be left floating.
Do not drive signals into these pins.
Supply Pins
VCC supplies power to the core and periphery.
Digital power for PLL[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in datasheet, even if the PLL is not used.
Analog power for PLL [L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in datasheet, even if the PLL is not used. It is advised to
keep this pin isolated from other VCC for better jitter performance.
Auxiliary supply for the programmable power technology.
These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2 V, 1.5 V,
1.8 V, 2.5 V, 3.3 V), HSTL(12, 15, 18),SSTL(15, 18, 2), 3.0 V PCI/PCI-X I/O as well as LVTTL 3.3 V I/O standards. VCCIO also supplies power to the input buffers used for
LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), 3.0 V PCI/PCI-X and LVTTL 3.3 V I/O standards.
Configuration pins power supply.
Dedicated power pins. This supply is used to power the I/O pre-drivers.
Differential clock input power supply for top and bottom I/O banks.
Device ground pins.
Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank.
Notes:
(1) These pin definitions are prepared based on the device with the largest density, HC4E35. Refer to the pin list for the availability of pins in each density.
(2) Refer to HardCopy IV handbook for the power supply recommended operating conditions.
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Pin Definitions
Page 18 of 20
VREFB8AN0
VREFB8CN0
PLL_T1
7C
7A
VREFB7CN0
VREFB7AN0
6C
1A
3A
3C
VREFB3AN0
VREFB3CN0
PLL_B1
4C
4A
VREFB4CN0
VREFB4AN0
VREFB5AN0 VREFB5CN0
5A
5C
2C
PLL_R2
2A
VREFB2AN0 VREFB2CN0
PLL_L2
VREFB6CN0 VREFB6AN0
8C
6A
8A
1C
VREFB1CN0 VREFB1AN0
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Notes:
1. This is a top view of the silicon die. For flip chip packages, the die is mounted upside down in the package; therefore, to obtain the top package view, flip this diagram on its
vertical axis.
®
2. This is a pictorial representation only to get an idea of placement on the device. Refer to the pin list and the Quartus II software for exact locations.
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Bank & PLL Diagram
Page 19 of 20
Pin Information for HardCopy® IV HC4E25FF780
Version 1.0
Version Number
1.0
Date
10/28/2009
PT-HC4E25FF780-1.0
Copyright © 2009 Altera Corp.
Changes Made
Initial release.
Revision History
Page 20 of 20