Pin Information for HardCopy III HC325FF484

Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
VREF Group
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
Pin Name
/Function
TDI
TMS
TRST
TCK
TDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
RDN1A
RUP1A
Configuration Function for
Stratix III Only (1)
TDI
TMS
TRST
TCK
TDO
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
DIFFIO_TX_L1n
DIFFIO_TX_L1p
DIFFIO_RX_L1n
DIFFIO_RX_L1p
DIFFIO_TX_L2n
DIFFIO_TX_L2p
DIFFIO_RX_L2n
DIFFIO_RX_L2p
DIFFIO_TX_L3n
DIFFIO_TX_L3p
DIFFIO_RX_L3n
DIFFIO_RX_L3p
DIFFIO_TX_L4n
DIFFIO_TX_L4p
DIFFIO_RX_L4n
DIFFIO_RX_L4p
DIFFIO_TX_L5n
DIFFIO_TX_L5p
DIFFIO_RX_L5n
DIFFIO_RX_L5p
DIFFIO_TX_L6n
DIFFIO_TX_L6p
DIFFIO_RX_L6n
DIFFIO_RX_L6p
DIFFOUT_L1n
DIFFOUT_L1p
DIFFOUT_L2n
DIFFOUT_L2p
DIFFOUT_L3n
DIFFOUT_L3p
DIFFOUT_L4n
DIFFOUT_L4p
DIFFOUT_L5n
DIFFOUT_L5p
DIFFOUT_L6n
DIFFOUT_L6p
DIFFOUT_L7n
DIFFOUT_L7p
DIFFOUT_L8n
DIFFOUT_L8p
DIFFOUT_L9n
DIFFOUT_L9p
DIFFOUT_L10n
DIFFOUT_L10p
DIFFOUT_L11n
DIFFOUT_L11p
DIFFOUT_L12n
DIFFOUT_L12p
Pin List
FF484
E17
D17
F18
D18
A18
B19
C19
A20
A19
G17
G16
B20
C20
D19
E19
A22
A21
D20
E20
B22
C22
F16
F15
C21
D21
H16
G15
D22
E22
F780/H780
for Stratix
III only
F24
H22
D26
C26
G24
F26
F25
C28
D27
G26
G25
B28
C27
H25
J24
D28
E28
J23
J22
F28
F27
K21
K20
G28
G27
K26
K25
J26
J25
K24
K23
H28
J27
L23
L22
J28
K27
H1152 for
Stratix III
only
G28
H28
J28
F30
G29
G31
G30
E32
E31
J30
J29
F32
F31
K28
K27
C34
C33
N25
M24
H32
H31
M27
M26
D34
D33
K30
K29
J32
J31
N26
P25
K32
K31
L32
L31
G34
H34
N24
P23
J34
J33
M30
M29
K34
K33
E34
F33
F34
L28
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ1L
DQ1L
DQSn1L
DQS1L
DQ1L
DQ1L
DQSn2L
DQS2L
DQ2L
DQ2L
DQ2L
DQ2L
DQ3L
DQ3L
DQSn3L
DQS3L
DQ3L
DQ3L
DQ1L
DQ1L
DQ1L
DQ1L/CQn1L
DQ1L
DQ1L
DQSn1L/DQ1L
DQS1L/CQ1L
DQ1L
DQ1L
DQ1L
DQ1L
Page 1 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
1A
1A
1A
1A
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
2C
2C
2C
VREF Group
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK1n
CLK1p
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK3p
CLK3n
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
DATA0
INIT_DONE
DEV_OE
DEV_CLRn
PLL_L2_CLKOUT0n
PLL_L2_FB_CLKOUT0p
CLK0n
CLK0p
CLK1n
CLK1p
CLK3p
CLK3n
CLK2p
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
DIFFIO_TX_L9n
DIFFIO_TX_L9p
DIFFIO_RX_L9n
DIFFIO_RX_L9p
DIFFIO_TX_L10n
DIFFIO_TX_L10p
DIFFIO_RX_L10n
DIFFIO_RX_L10p
DIFFIO_TX_L11n
DIFFIO_TX_L11p
DIFFIO_RX_L11n
DIFFIO_RX_L11p
DIFFIO_TX_L12n
DIFFIO_TX_L12p
DIFFIO_RX_L12n
DIFFIO_RX_L12p
DIFFIO_TX_L13n
DIFFIO_TX_L13p
DIFFIO_RX_L13n
DIFFIO_RX_L13p
DIFFIO_TX_L14n
DIFFIO_TX_L14p
DIFFIO_RX_L14n
DIFFIO_RX_L14p
DIFFOUT_L17n
DIFFOUT_L17p
DIFFOUT_L18n
DIFFOUT_L18p
DIFFOUT_L19n
DIFFOUT_L19p
DIFFOUT_L20n
DIFFOUT_L20p
DIFFOUT_L21n
DIFFOUT_L21p
DIFFOUT_L22n
DIFFOUT_L22p
DIFFOUT_L23n
DIFFOUT_L23p
DIFFOUT_L24n
DIFFOUT_L24p
DIFFOUT_L25n
DIFFOUT_L25p
DIFFOUT_L26n
DIFFOUT_L26p
DIFFOUT_L27n
DIFFOUT_L27p
DIFFOUT_L28n
DIFFOUT_L28p
DIFFIO_RX_L15p
Pin List
DIFFOUT_L29p
FF484
G19
H19
F20
G20
H20
J19
F22
F21
J18
J17
K20
K19
H17
J16
J21
J20
K16
L16
G22
G21
L20
L19
J22
K21
K22
L22
M19
M20
M21
F780/H780 H1152 for
for Stratix Stratix III
III only
only
L29
G33
N27
M28
M23
R28
M22
R27
L26
R32
L25
P31
M21
R30
M20
R29
K28
N34
L28
P34
N21
T28
N20
T27
M26
R34
M25
R33
N25
T25
M24
T24
M28
T32
M27
R31
N23
T26
P23
U25
P25
U32
N24
U31
P20
T30
P19
T29
N27
V32
N26
V31
N28
T34
P28
T33
N30
N29
N32
M31
P29
P28
L34
M33
R26
R25
P32
N31
R24
T23
M34
N33
R27
V33
R28
V34
U28
W33
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQSn5L
DQS5L
DQ5L
DQ5L
DQ5L
DQ5L
DQ6L
DQ6L
DQSn6L
DQS6L
DQ6L
DQ6L
DQSn7L
DQS7L
DQ7L
DQ7L
DQ7L
DQ7L
DQ5L
DQ5L
DQ5L
DQ5L/CQn5L
DQ5L
DQ5L
DQSn5L/DQ5L
DQS5L/CQ5L
DQ5L
DQ5L
DQ5L
DQ5L
Page 2 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
VREF Group
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
CLK2n
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_L15n
DIFFIO_TX_L15p
DIFFIO_TX_L15n
DIFFIO_RX_L16p
DIFFIO_RX_L16n
DIFFIO_TX_L16p
DIFFIO_TX_L16n
DIFFIO_RX_L17p
DIFFIO_RX_L17n
DIFFIO_TX_L17p
DIFFIO_TX_L17n
DIFFIO_RX_L18p
DIFFIO_RX_L18n
DIFFIO_TX_L18p
DIFFIO_TX_L18n
DIFFIO_RX_L19p
DIFFIO_RX_L19n
DIFFIO_TX_L19p
DIFFIO_TX_L19n
DIFFIO_RX_L20p
DIFFIO_RX_L20n
DIFFIO_TX_L20p
DIFFIO_TX_L20n
Pin List
Emulated LVDS
Output Channel (2)
DIFFOUT_L29n
DIFFOUT_L30p
DIFFOUT_L30n
DIFFOUT_L31p
DIFFOUT_L31n
DIFFOUT_L32p
DIFFOUT_L32n
DIFFOUT_L33p
DIFFOUT_L33n
DIFFOUT_L34p
DIFFOUT_L34n
DIFFOUT_L35p
DIFFOUT_L35n
DIFFOUT_L36p
DIFFOUT_L36n
DIFFOUT_L37p
DIFFOUT_L37n
DIFFOUT_L38p
DIFFOUT_L38n
DIFFOUT_L39p
DIFFOUT_L39n
DIFFOUT_L40p
DIFFOUT_L40n
FF484
M22
M15
M16
N21
N22
P16
P17
N19
N20
N16
N17
R21
R22
P19
P20
U22
T22
R19
R20
T20
T21
R18
T19
F780/H780
for Stratix
III only
T28
R20
R21
R26
T27
T25
R25
V27
V28
T20
T21
V26
U26
T24
U25
W27
W28
T22
T23
V24
V25
V23
U23
H1152 for
Stratix III
only
W34
W28
V29
AA33
Y34
W26
W27
Y31
Y32
V24
V25
AB33
AA34
W30
W31
AA31
AA32
Y28
Y29
AC34
AB34
Y23
W24
AB31
AB32
AA29
AA30
AD33
AD34
Y25
Y26
AC31
AC32
AA27
AA28
AE33
AE34
AB29
AB30
AG33
AF34
AA24
AA25
AE31
AE32
AC28
AC29
AH33
AG34
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ8L
DQ8L
DQ8L
DQ8L
DQS8L
DQSn8L
DQ9L
DQ9L
DQS9L
DQSn9L
DQ9L
DQ9L
DQ10L
DQ10L
DQ10L
DQ10L
DQS10L
DQSn10L
DQ10L
DQ10L
DQ10L
DQ10L
DQS10L/CQ10L
DQSn10L/DQ10L
DQ10L
DQ10L
DQ10L/CQn10L
DQ10L
DQ10L
DQ10L
Page 3 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
3A
3A
3A
3A
3A
3A
VREF Group
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
nCONFIG
nSTATUS
CONF_DONE
PORSEL
nCE
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
RUP2A
RDN2A
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
DIFFIO_RX_L23p
DIFFIO_RX_L23n
DIFFIO_TX_L23p
DIFFIO_TX_L23n
DIFFIO_RX_L24p
DIFFIO_RX_L24n
DIFFIO_TX_L24p
DIFFIO_TX_L24n
DIFFIO_RX_L25p
DIFFIO_RX_L25n
DIFFIO_TX_L25p
DIFFIO_TX_L25n
DIFFIO_RX_L26p
DIFFIO_RX_L26n
DIFFIO_TX_L26p
DIFFIO_TX_L26n
DIFFIO_RX_L27p
DIFFIO_RX_L27n
DIFFIO_TX_L27p
DIFFIO_TX_L27n
DIFFIO_RX_L28p
DIFFIO_RX_L28n
DIFFIO_TX_L28p
DIFFIO_TX_L28n
DIFFOUT_L45p
DIFFOUT_L45n
DIFFOUT_L46p
DIFFOUT_L46n
DIFFOUT_L47p
DIFFOUT_L47n
DIFFOUT_L48p
DIFFOUT_L48n
DIFFOUT_L49p
DIFFOUT_L49n
DIFFOUT_L50p
DIFFOUT_L50n
DIFFOUT_L51p
DIFFOUT_L51n
DIFFOUT_L52p
DIFFOUT_L52n
DIFFOUT_L53p
DIFFOUT_L53n
DIFFOUT_L54p
DIFFOUT_L54n
DIFFOUT_L55p
DIFFOUT_L55n
DIFFOUT_L56p
DIFFOUT_L56n
nCONFIG
nSTATUS
CONF_DONE
PORSEL
nCE
Pin List
FF484
V21
V22
U15
T15
Y22
W22
U16
T17
W20
W21
U19
U20
AA21
AA22
V19
V20
AB20
AB21
V16
W17
AB18
AB19
AA19
Y19
AB17
W18
V18
Y18
Y17
F780/H780 H1152 for
for Stratix Stratix III
III only
only
AD30
AD31
AF31
AF32
AB24
AB25
AA27
AJ34
Y28
AG32
W22
AG31
W23
AB26
AB27
AB27
AA28
AE29
W24
AE30
W25
AH34
Y25
AK33
Y26
AK34
V20
AD28
V21
AD29
AC28
AJ31
AB28
AJ32
AA25
AF28
AA26
AF29
AB25
AM34
AB26
AL34
AC25
AE27
AC26
AE28
AD27
AH30
AD28
AH31
W20
AD26
W21
AD27
AG28
AL32
AF28
AL33
Y23
AC25
AA24
AC26
AE27
AK31
AE28
AK32
AA23
AG29
AB24
AG30
W19
AE25
AD25
AH28
AE26
AH29
AB23
AF26
Y20
AE26
AF26
AE23
AH27
AP29
AH25
AM28
AG25
AL29
AG27
AM29
AH26
AN28
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ12L
DQ12L
DQS12L
DQSn12L
DQ12L
DQ12L
DQ13L
DQ13L
DQ13L
DQ13L
DQS13L
DQSn13L
DQ14L
DQ14L
DQS14L
DQSn14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQ14L
DQS14L/CQ14L
DQSn14L/DQ14L
DQ14L
DQ14L
DQ14L/CQn14L
DQ14L
DQ14L
DQ14L
Page 4 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
VREF Group
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Pin List
Emulated LVDS
Output Channel (2)
FF484
F780/H780
for Stratix
III only
AE22
AD22
AB20
AB21
AD21
AC21
AD24
AE23
AF24
AE24
AF23
AG24
AH24
AH23
AH20
AH21
AH22
AG22
AC20
AG21
AF21
AE21
AF20
AE20
AD19
AC19
AB19
AA19
AE19
AD18
Y19
AA18
Y18
Y17
H1152 for
Stratix III
only
AK27
AM30
AN27
AP28
AN30
AM31
AH26
AP27
AM26
AL26
AM32
AF24
AG24
AK25
AL27
AH25
AH24
AH27
AL28
AN31
AF23
AJ28
AJ29
AP32
AP30
AP31
AN33
AP33
AK28
AJ26
AJ27
AC22
AD22
AE24
AH23
AJ24
AJ22
AH22
AJ23
AK22
AM24
AL24
AK24
AL25
AM23
AL23
AE22
AE21
AG21
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
Page 5 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
3B
3B
3B
3B
3B
3B
3B
3B
3B
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
4C
4C
4C
4C
4C
4C
4C
4C
VREF Group
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_B11n
DIFFIO_RX_B11p
DIFFIO_RX_B12n
DIFFIO_RX_B12p
DIFFIO_RX_B13n
DIFFIO_RX_B13p
PLL_B1_CLKOUT4
PLL_B1_CLKOUT3
DIFFIO_RX_B14n
DIFFIO_RX_B14p
PLL_B1_CLKOUT0n
PLL_B1_CLKOUT0p
PLL_B1_FBn/CLKOUT2
PLL_B1_FBp/CLKOUT1
CLK5n
CLK5p
CLK4n
CLK4p
CLK6p
CLK6n
CLK7p
CLK7n
DIFFIO_RX_B15n
DIFFIO_RX_B15p
DIFFIO_RX_B16n
DIFFIO_RX_B16p
DIFFIO_RX_B17p
DIFFIO_RX_B17n
DIFFIO_RX_B18p
DIFFIO_RX_B18n
Pin List
Emulated LVDS
Output Channel (2)
FF484
DIFFOUT_B21n
DIFFOUT_B21p
DIFFOUT_B22n
DIFFOUT_B22p
DIFFOUT_B23n
DIFFOUT_B23p
DIFFOUT_B24n
DIFFOUT_B24p
DIFFOUT_B25n
DIFFOUT_B25p
DIFFOUT_B26n
DIFFOUT_B26p
DIFFOUT_B27n
DIFFOUT_B27p
DIFFOUT_B28n
DIFFOUT_B28p
DIFFOUT_B29n
DIFFOUT_B29p
DIFFOUT_B30n
DIFFOUT_B30p
DIFFOUT_B31n
DIFFOUT_B31p
DIFFOUT_B32n
DIFFOUT_B32p
W16
V15
Y14
W14
Y15
W15
AB16
AA16
Y16
AB14
AB15
AA15
T13
R13
W13
V13
Y12
W12
U14
U13
AB12
AA12
AB13
AA13
DIFFOUT_B33p
DIFFOUT_B33n
DIFFOUT_B34p
DIFFOUT_B34n
DIFFOUT_B35p
DIFFOUT_B35n
DIFFOUT_B36p
DIFFOUT_B36n
Y10
AA10
AB10
AB11
W11
Y11
T10
R10
F780/H780 H1152 for
for Stratix Stratix III
III only
only
AF21
AD21
AE20
AP25
AN25
AP26
AP23
AP24
AN24
AF19
AL22
AG19
AM22
AH19
AL21
AG18
AK21
AH17
AJ20
AH18
AJ21
AF17
AP22
AE18
AN22
AE16
AM21
AD16
AP20
AF16
AP21
AE17
AN21
AC17
AE19
AB17
AD19
AC16
AH19
AB16
AG19
AA15
AE18
Y15
AD18
AH16
AK19
AG16
AJ19
AH15
AP19
AG15
AN19
AF15
AP18
AE15
AN18
AL20
AM18
AM19
AL19
AK18
AL18
AF20
AF19
AE14
AN16
AF14
AP16
AG13
AN15
AH14
AP15
AG12
AJ16
AH13
AK16
Y13
AL15
Y14
AM15
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ7B
DQ7B
DQSn7B
DQS7B
DQ7B
DQ7B
DQSn8B
DQS8B
DQ8B
DQ8B
DQ8B
DQ8B
DQ7B
DQ7B
DQ7B
DQ7B/CQn7B
DQ7B
DQ7B
DQSn7B/DQ7B
DQS7B/CQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ9B
DQ9B
Page 6 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4A
VREF Group
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_B19p
DIFFIO_RX_B19n
DIFFIO_RX_B20p
DIFFIO_RX_B20n
DIFFIO_RX_B21p
DIFFIO_RX_B21n
DIFFIO_RX_B22p
DIFFIO_RX_B22n
Emulated LVDS
Output Channel (2)
DIFFOUT_B37p
DIFFOUT_B37n
DIFFOUT_B38p
DIFFOUT_B38n
DIFFOUT_B39p
DIFFOUT_B39n
DIFFOUT_B40p
DIFFOUT_B40n
DIFFOUT_B41p
DIFFOUT_B41n
DIFFOUT_B42p
DIFFOUT_B42n
DIFFOUT_B43p
DIFFOUT_B43n
DIFFOUT_B44p
DIFFOUT_B44n
FF484
U9
V9
R9
T9
AA9
AB9
W8
AB8
W9
Y9
Y7
W7
AA7
AB7
AB6
AA6
F780/H780
for Stratix
III only
AD13
AE13
AA13
AB13
AG10
AH10
AH11
AH12
AF10
AF11
AF12
AC12
AD12
AE12
AC11
AE11
AB11
Pin List
H1152 for
Stratix III
only
AL14
AM14
AK13
AL13
AH15
AJ15
AG15
AK15
AH14
AJ14
AP14
AN13
AN12
AP12
AM12
AP13
AL17
AM17
AE16
AF16
AL16
AM16
AD15
AD16
AN10
AP10
AP9
AP11
AM9
AN9
AE15
AF15
AF13
AF14
AE13
AE14
AK12
AL12
AK10
AM11
AL10
AL11
AM8
AP8
AN7
AP7
AP6
AM7
AM4
DQ Group for
DQS X4 Mode (2)
DQS9B
DQSn9B
DQ9B
DQ9B
DQ10B
DQ10B
DQ10B
DQ10B
DQS10B
DQSn10B
DQ11B
DQ11B
DQS11B
DQSn11B
DQ11B
DQ11B
DQ Group for
DQS X8/X9 Mode (2)
DQ11B
DQ11B
DQ11B
DQ11B
DQS11B/CQ11B
DQSn11B/DQ11B
DQ11B
DQ11B
DQ11B/CQn11B
DQ11B
DQ11B
DQ11B
Page 7 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
5A
5A
5A
5A
5A
VREF Group
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
nIO_PULLUP
nCEO
DCLK
nCSO
ASDO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
FF484
DIFFOUT_R1n
DIFFOUT_R1p
DIFFOUT_R2n
DIFFOUT_R2p
DIFFOUT_R3n
AB4
U5
Y4
Y6
Y3
W4
W5
AA3
AA4
V6
nIO_PULLUP
nCEO
DCLK
nCSO
ASDO
RDN5A
RUP5A
DIFFIO_TX_R1n
DIFFIO_TX_R1p
DIFFIO_RX_R1n
DIFFIO_RX_R1p
DIFFIO_TX_R2n
Pin List
F780/H780
for Stratix
III only
AC10
Y10
Y11
AG9
AH8
AE10
AH9
AE9
AF9
AF8
AE8
AG7
AH7
AG6
AH6
AG4
AH3
AH4
AH5
AG3
AH2
AD9
AC9
AA9
AB9
Y9
AA10
AE6
AF6
AE4
AE7
AE5
AF5
AB8
AC8
AC7
AD7
AB7
AD6
AE3
AB5
AC5
AD4
AA6
AC3
AC4
AF1
AE2
AB3
H1152 for
Stratix III
only
AL5
AC12
AE10
AE11
AM5
AD12
AG9
AF11
AN6
AF10
AH9
AM6
AG12
AJ6
AH8
AJ7
AK6
AL8
AH11
AJ8
AK7
AJ10
AJ11
AN3
AN4
AL7
AK9
AH12
AP3
AP4
AP2
AP5
AJ9
AL9
AJ12
AJ13
AE12
AD13
AL4
AF8
AJ5
AL3
AE9
AH6
AH4
AH5
AK3
AK4
AE7
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ1R
DQ1R
Page 8 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5C
5C
5C
5C
5C
5C
VREF Group
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_TX_R2p
DIFFIO_RX_R2n
DIFFIO_RX_R2p
DIFFIO_TX_R3n
DIFFIO_TX_R3p
DIFFIO_RX_R3n
DIFFIO_RX_R3p
DIFFIO_TX_R4n
DIFFIO_TX_R4p
DIFFIO_RX_R4n
DIFFIO_RX_R4p
DIFFIO_TX_R5n
DIFFIO_TX_R5p
DIFFIO_RX_R5n
DIFFIO_RX_R5p
DIFFIO_TX_R6n
DIFFIO_TX_R6p
DIFFIO_RX_R6n
DIFFIO_RX_R6p
Emulated LVDS
Output Channel (2)
DIFFOUT_R3p
DIFFOUT_R4n
DIFFOUT_R4p
DIFFOUT_R5n
DIFFOUT_R5p
DIFFOUT_R6n
DIFFOUT_R6p
DIFFOUT_R7n
DIFFOUT_R7p
DIFFOUT_R8n
DIFFOUT_R8p
DIFFOUT_R9n
DIFFOUT_R9p
DIFFOUT_R10n
DIFFOUT_R10p
DIFFOUT_R11n
DIFFOUT_R11p
DIFFOUT_R12n
DIFFOUT_R12p
FF484
V7
AB2
AB3
U4
T4
AB1
AA1
V3
V4
W2
W3
U7
U8
Y1
Y2
T7
T8
W1
V1
DIFFIO_TX_R9n
DIFFIO_TX_R9p
DIFFIO_RX_R9n
DIFFIO_RX_R9p
DIFFIO_TX_R10n
DIFFIO_TX_R10p
DIFFOUT_R17n
DIFFOUT_R17p
DIFFOUT_R18n
DIFFOUT_R18p
DIFFOUT_R19n
DIFFOUT_R19p
R6
P7
R3
R4
P3
P4
Pin List
F780/H780
for Stratix
III only
AB4
AG1
AF2
Y6
Y7
AE1
AD1
AA4
Y5
AC1
AC2
Y3
Y4
AB1
AB2
W8
W9
AA1
Y2
W5
W6
Y1
W2
V6
V7
W3
W4
U6
U7
V3
V4
U8
U9
H1152 for
Stratix III
only
AE8
AM1
AM2
AF5
AF6
AJ3
AJ4
AC8
AC9
AL1
AL2
AE5
AE6
AG3
AG4
AB10
AC11
AK1
AJ2
AB9
AA10
AH1
AG1
AC5
AC6
AF1
AF2
AB11
AA12
AE3
AE4
AD3
AD4
AE1
AE2
AC7
AB8
AH2
AF3
AF4
AD6
AD7
AJ1
Y11
W12
Y3
AA4
Y5
Y6
DQ Group for
DQS X4 Mode (2)
DQ1R
DQSn1R
DQS1R
DQ1R
DQ1R
DQSn2R
DQS2R
DQ2R
DQ2R
DQ2R
DQ2R
DQ3R
DQ3R
DQSn3R
DQS3R
DQ3R
DQ3R
DQ Group for
DQS X8/X9 Mode (2)
DQ1R
DQ1R
DQ1R/CQn1R
DQ1R
DQ1R
DQSn1R/DQ1R
DQS1R/CQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn5R
DQS5R
DQ5R
DQ5R
Page 9 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
VREF Group
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK8n
CLK8p
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK10p
CLK10n
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
CLK9n
CLK9p
CLK8n
CLK8p
CLK10p
CLK10n
CLK11p
CLK11n
PLL_R2_FB_CLKOUT0p
PLL_R2_CLKOUT0n
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_R10n
DIFFIO_RX_R10p
DIFFIO_TX_R11n
DIFFIO_TX_R11p
DIFFIO_RX_R11n
DIFFIO_RX_R11p
DIFFIO_TX_R12n
DIFFIO_TX_R12p
DIFFIO_RX_R12n
DIFFIO_RX_R12p
DIFFIO_TX_R13n
DIFFIO_TX_R13p
DIFFIO_RX_R13n
DIFFIO_RX_R13p
DIFFIO_TX_R14n
DIFFIO_TX_R14p
DIFFIO_RX_R14n
DIFFIO_RX_R14p
DIFFIO_RX_R15p
DIFFIO_RX_R15n
DIFFIO_TX_R15p
DIFFIO_TX_R15n
DIFFIO_RX_R16p
DIFFIO_RX_R16n
DIFFIO_TX_R16p
DIFFIO_TX_R16n
DIFFIO_RX_R17p
DIFFIO_RX_R17n
DIFFIO_TX_R17p
Pin List
Emulated LVDS
Output Channel (2)
DIFFOUT_R20n
DIFFOUT_R20p
DIFFOUT_R21n
DIFFOUT_R21p
DIFFOUT_R22n
DIFFOUT_R22p
DIFFOUT_R23n
DIFFOUT_R23p
DIFFOUT_R24n
DIFFOUT_R24p
DIFFOUT_R25n
DIFFOUT_R25p
DIFFOUT_R26n
DIFFOUT_R26p
DIFFOUT_R27n
DIFFOUT_R27p
DIFFOUT_R28n
DIFFOUT_R28p
DIFFOUT_R29p
DIFFOUT_R29n
DIFFOUT_R30p
DIFFOUT_R30n
DIFFOUT_R31p
DIFFOUT_R31n
DIFFOUT_R32p
DIFFOUT_R32n
DIFFOUT_R33p
DIFFOUT_R33n
DIFFOUT_R34p
FF484
U3
T3
P6
N6
U1
U2
N4
N5
T1
T2
M6
M7
P1
P2
M3
M4
N2
N3
N1
M1
F780/H780
for Stratix
III only
W1
V1
T4
U5
U3
U4
T8
T9
T2
T3
T6
R6
R4
T5
R9
R10
U1
U2
T1
R1
L2
L1
K2
K1
L4
L3
H1
J1
K8
K7
K4
K3
H7
P2
P1
M1
N1
P9
P8
N4
P4
N7
N6
P3
N2
N5
H1152 for
Stratix III
only
AB1
AA1
W7
W8
W3
Y4
W10
W11
Y1
Y2
W5
W6
V3
V4
W9
V10
U3
U4
W1
W2
AB5
AB6
AB3
AC4
AA6
AA7
AD1
AC2
Y9
Y10
AA3
AB4
Y7
Y8
AC1
AB2
U2
U1
T2
T1
U11
U10
P2
R1
T7
U6
R4
R3
T9
DQ Group for
DQS X4 Mode (2)
DQ5R
DQ5R
DQ6R
DQ6R
DQSn6R
DQS6R
DQ6R
DQ6R
DQSn7R
DQS7R
DQ7R
DQ7R
DQ7R
DQ7R
DQ Group for
DQS X8/X9 Mode (2)
DQ5R
DQ5R
DQ5R
DQ5R/CQn5R
DQ5R
DQ5R
DQSn5R/DQ5R
DQS5R/CQ5R
DQ5R
DQ5R
DQ5R
DQ5R
DQ8R
DQ8R
DQ8R
DQ8R
DQS8R
DQSn8R
DQ9R
DQ10R
DQ10R
DQ10R
DQ10R
DQS10R/CQ10R
DQSn10R/DQ10R
DQ10R
Page 10 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREF Group
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_TX_R17n
DIFFIO_RX_R18p
DIFFIO_RX_R18n
DIFFIO_TX_R18p
DIFFIO_TX_R18n
DIFFIO_RX_R19p
DIFFIO_RX_R19n
DIFFIO_TX_R19p
DIFFIO_TX_R19n
DIFFIO_RX_R20p
DIFFIO_RX_R20n
DIFFIO_TX_R20p
DIFFIO_TX_R20n
Emulated LVDS
Output Channel (2)
DIFFOUT_R34n
DIFFOUT_R35p
DIFFOUT_R35n
DIFFOUT_R36p
DIFFOUT_R36n
DIFFOUT_R37p
DIFFOUT_R37n
DIFFOUT_R38p
DIFFOUT_R38n
DIFFOUT_R39p
DIFFOUT_R39n
DIFFOUT_R40p
DIFFOUT_R40n
FF484
J7
F1
G1
J4
J3
H3
H2
H5
H4
G4
G3
H6
J6
F780/H780
for Stratix
III only
M4
L2
L1
N9
N8
L3
M3
L5
L4
K2
K1
L6
M6
H2
J1
K7
K6
Pin List
H1152 for
Stratix III
only
T8
N2
P1
T5
T4
P4
P3
R7
R6
M1
N1
P6
P5
N4
N3
R12
T11
L2
L1
R10
R9
M4
M3
P8
P7
K2
K1
N6
N5
H2
J1
P11
P10
K4
K3
M7
M6
G2
H1
L5
L4
J4
J3
L7
L6
H4
H3
F1
G1
DQ Group for
DQS X4 Mode (2)
DQ9R
DQS9R
DQSn9R
DQ9R
DQ9R
DQ10R
DQ10R
DQ10R
DQ10R
DQS10R
DQSn10R
DQ Group for
DQS X8/X9 Mode (2)
DQ10R
DQ10R/CQn10R
DQ10R
DQ10R
DQ10R
Page 11 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
VREF Group
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
RUP6A
RDN6A
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
FF484
DIFFIO_RX_R23p
DIFFIO_RX_R23n
DIFFIO_TX_R23p
DIFFIO_TX_R23n
DIFFIO_RX_R24p
DIFFIO_RX_R24n
DIFFIO_TX_R24p
DIFFIO_TX_R24n
DIFFIO_RX_R25p
DIFFIO_RX_R25n
DIFFIO_TX_R25p
DIFFIO_TX_R25n
DIFFIO_RX_R26p
DIFFIO_RX_R26n
DIFFIO_TX_R26p
DIFFIO_TX_R26n
DIFFIO_RX_R27p
DIFFIO_RX_R27n
DIFFIO_TX_R27p
DIFFIO_TX_R27n
DIFFIO_RX_R28p
DIFFIO_RX_R28n
DIFFIO_TX_R28p
DIFFIO_TX_R28n
DIFFOUT_R45p
DIFFOUT_R45n
DIFFOUT_R46p
DIFFOUT_R46n
DIFFOUT_R47p
DIFFOUT_R47n
DIFFOUT_R48p
DIFFOUT_R48n
DIFFOUT_R49p
DIFFOUT_R49n
DIFFOUT_R50p
DIFFOUT_R50n
DIFFOUT_R51p
DIFFOUT_R51n
DIFFOUT_R52p
DIFFOUT_R52n
DIFFOUT_R53p
DIFFOUT_R53n
DIFFOUT_R54p
DIFFOUT_R54n
DIFFOUT_R55p
DIFFOUT_R55n
DIFFOUT_R56p
DIFFOUT_R56n
E2
E1
F8
G8
D2
D1
F7
G6
B1
C1
F4
F3
A2
B2
E5
E4
D3
E3
B4
C4
A4
A3
B5
C5
Pin List
F780/H780
for Stratix
III only
G2
H1
K5
K4
F1
G1
J4
J3
E2
E1
L9
L8
H4
H3
K9
K8
D2
D1
J6
H5
F4
F3
G4
G3
B1
C1
H6
G5
A2
C3
A4
B4
A3
B2
D7
E7
G8
G9
E8
F8
D6
E5
C5
D5
B5
C6
A5
A6
A8
H1152 for
Stratix III
only
K5
K6
N8
N9
E2
E1
N11
N10
F4
F3
J7
J6
G5
G4
K8
K7
C1
D1
M10
M9
D3
D2
L9
L8
E4
E3
H6
H5
F8
F9
E7
A2
B2
A4
A5
A3
G8
F7
J12
B4
D7
F6
G11
G10
C9
D8
A8
H11
J11
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ12R
DQ12R
DQS12R
DQSn12R
DQ12R
DQ12R
DQ13R
DQ13R
DQ13R
DQ13R
DQS13R
DQSn13R
DQ14R
DQ14R
DQS14R
DQSn14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQ14R
DQS14R/CQ14R
DQSn14R/DQ14R
DQ14R
DQ14R
DQ14R/CQn14R
DQ14R
DQ14R
DQ14R
Page 12 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7C
7C
7C
7C
7C
7C
VREF Group
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
FF484
DIFFIO_RX_T11n
DIFFIO_RX_T11p
DIFFOUT_T21n
DIFFOUT_T21p
DIFFOUT_T22n
DIFFOUT_T22p
DIFFOUT_T23n
DIFFOUT_T23p
D7
D9
C10
D10
D8
C9
Pin List
F780/H780
for Stratix
III only
A9
A7
B7
B8
F9
C8
D8
D9
C9
E10
F10
H10
G10
D10
E11
H11
J10
J11
J12
B10
C10
A10
B11
A11
A12
H1152 for
Stratix III
only
C3
D9
E10
A7
B8
G9
C4
B5
B7
C5
E8
C7
C6
D6
A6
M13
L13
K11
K12
G12
F11
F12
F13
G13
E11
C11
D11
D13
D10
C12
D12
K14
K13
H14
J14
K15
L14
A10
B10
A12
A9
A11
B11
D14
E13
E14
F14
F15
D15
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
DQ7T
DQ7T
DQSn7T
DQS7T
DQ7T
DQ7T
DQ7T
DQ7T
DQ7T
DQ7T/CQn7T
DQ7T
DQ7T
Page 13 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
VREF Group
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
DIFFIO_RX_T12n
DIFFIO_RX_T12p
DIFFIO_RX_T13n
DIFFIO_RX_T13p
DIFFIO_RX_T14n
DIFFIO_RX_T14p
DIFFIO_RX_T15n
DIFFIO_RX_T15p
CLK13n
CLK13p
CLK12n
CLK12p
CLK14p
CLK14n
CLK15p
CLK15n
PLL_T1_FBp/CLKOUT1
PLL_T1_FBn/CLKOUT2
PLL_T1_CLKOUT0p
PLL_T1_CLKOUT0n
DIFFIO_RX_T16n
DIFFIO_RX_T16p
DIFFIO_RX_T17p
DIFFIO_RX_T17n
DIFFIO_RX_T18p
DIFFIO_RX_T18n
DIFFIO_RX_T19p
DIFFIO_RX_T19n
PLL_T1_CLKOUT3
PLL_T1_CLKOUT4
DIFFIO_RX_T20p
DIFFIO_RX_T20n
DIFFIO_RX_T21p
DIFFIO_RX_T21n
DIFFIO_RX_T22p
DIFFIO_RX_T22n
Pin List
Emulated LVDS
Output Channel (2)
DIFFOUT_T24n
DIFFOUT_T24p
DIFFOUT_T25n
DIFFOUT_T25p
DIFFOUT_T26n
DIFFOUT_T26p
DIFFOUT_T27n
DIFFOUT_T27p
DIFFOUT_T28n
DIFFOUT_T28p
DIFFOUT_T29n
DIFFOUT_T29p
DIFFOUT_T30n
DIFFOUT_T30p
DIFFOUT_T31n
DIFFOUT_T31p
DIFFOUT_T32n
DIFFOUT_T32p
FF484
A7
B7
A9
C7
A8
B8
F10
G10
F9
G9
H10
G11
C11
D11
A11
B11
A10
B10
F780/H780
for Stratix
III only
C12
D11
E13
D13
C13
D12
G12
F12
F13
G13
H14
J14
A13
B13
A14
B14
C14
D14
DIFFOUT_T33p
DIFFOUT_T33n
DIFFOUT_T34p
DIFFOUT_T34n
DIFFOUT_T35p
DIFFOUT_T35n
DIFFOUT_T36p
DIFFOUT_T36n
DIFFOUT_T37p
DIFFOUT_T37n
DIFFOUT_T38p
DIFFOUT_T38n
DIFFOUT_T39p
DIFFOUT_T39n
DIFFOUT_T40p
DIFFOUT_T40n
DIFFOUT_T41p
DIFFOUT_T41n
DIFFOUT_T42p
DIFFOUT_T42n
DIFFOUT_T43p
DIFFOUT_T43n
DIFFOUT_T44p
A13
A12
D12
C12
C13
B13
H14
G14
D14
D13
E14
F14
A15
A14
B14
D15
C15
C14
C17
B17
A17
A16
D16
D15
C15
B16
A15
B17
A16
J16
J15
E16
D16
G16
H16
B19
A19
A17
A18
C19
C18
F17
C17
E17
D17
D18
H1152 for
Stratix III
only
A13
B13
A15
C14
A14
B14
C17
C15
C16
D16
D17
E17
J16
J15
A16
B16
A17
B17
L16
K16
G16
H16
K17
L17
E16
F16
B19
A19
B20
A20
D18
C18
K19
J19
D19
C19
L19
L20
G20
F20
E20
H20
G21
F21
A22
A21
B23
A23
B22
DQ Group for
DQS X4 Mode (2)
DQSn8T
DQS8T
DQ8T
DQ8T
DQ8T
DQ8T
DQ9T
DQ9T
DQSn9T
DQS9T
DQ9T
DQ9T
DQ Group for
DQS X8/X9 Mode (2)
DQSn7T/DQ7T
DQS7T/CQ7T
DQ7T
DQ7T
DQ7T
DQ7T
DQ10T
DQ10T
DQ10T
DQ10T
DQS10T
DQSn10T
DQ11T
DQ11T
DQS11T
DQSn11T
DQ11T
DQ11T
DQ11T
DQ11T
DQ11T
DQS11T/CQ11T
DQSn11T/DQ11T
DQ11T
DQ11T
DQ11T/CQn11T
DQ11T
DQ11T
Page 14 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
8C
8C
8C
8C
8C
8C
8C
8C
8C
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
VREF Group
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
DIFFOUT_T44n
FF484
C16
F780/H780
for Stratix
III only
F18
G18
F19
J18
J19
B20
A21
A20
D19
D20
C20
D21
C21
B22
A22
A23
B23
Pin List
H1152 for
Stratix III
only
C23
F19
E19
C20
D20
D21
C21
D22
E22
B25
A25
A24
A26
C26
B26
K20
J20
J22
J21
K21
K22
D25
D24
C24
E25
E23
D23
A27
C27
B28
A28
C28
A29
F22
F23
D26
F26
A30
A33
A31
A32
G23
E26
D28
B31
B32
F24
D27
E28
DQ Group for
DQS X4 Mode (2)
DQ11T
DQ Group for
DQS X8/X9 Mode (2)
DQ11T
Page 15 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
VREF Group
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
Pin Name
/Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
FF484
L14
AB5
M11
E18
AB22
AA20
AA17
AA14
AA11
AA8
AA5
AA2
Y21
V17
V14
V11
V8
V5
V2
U21
U18
R14
R11
R8
R5
Pin List
F780/H780
for Stratix
III only
B25
A26
A24
A25
B26
A27
F20
E20
H20
G20
H19
J20
D23
C23
D22
D25
D24
C24
F21
G21
F22
E22
E23
G22
M17
AF3
R14
K11
B24
AG2
AG5
AG8
AG11
AG14
AG17
AG20
AG23
AG26
AF27
AD2
AD5
AD8
AD11
AD14
AD17
AD20
AD23
AC24
AC27
H1152 for
Stratix III
only
E29
H23
G24
F25
F27
F28
F29
G27
B29
G26
J25
L23
C29
J24
H26
M23
C30
K24
K25
C31
D30
L22
K23
D31
V2
AF9
V17
E21
N14
AN5
AN8
AN11
AN14
AN17
AN20
AN23
AN26
AN29
AN32
AM33
AK2
AK5
AK8
AK11
AK14
AK17
AK20
AK23
AK26
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
Page 16 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Pin List
Emulated LVDS
Output Channel (2)
FF484
R2
P21
P18
P15
P13
P11
P9
N14
N12
N10
M13
M9
M8
M5
M2
L21
L18
L15
L10
K13
K11
K9
J14
J12
J10
J8
J5
J2
H21
H18
H15
H12
H9
F5
F2
E21
E15
E12
E9
E6
C2
B21
B18
B15
B12
B9
B6
B3
A1
F780/H780
for Stratix
III only
AA2
AA5
AA8
AA11
AA14
AA17
AA20
Y12
Y16
Y21
Y24
Y27
W12
W14
W16
W18
V2
V5
V8
V11
V13
V15
V17
V19
U10
U12
U14
U16
U18
U21
U24
U27
T11
T13
T15
T17
T19
R2
R5
R8
R12
R16
R18
P11
P13
P17
P21
P24
P27
H1152 for
Stratix III
only
AK29
AJ30
AJ33
AG2
AG5
AG8
AG11
AG14
AG17
AG20
AG23
AG26
AF27
AF30
AF33
AD2
AD5
AD8
AD11
AD14
AD17
AD20
AD23
AC14
AC16
AC18
AC20
AC24
AC27
AC30
AC33
AB13
AB15
AB17
AB19
AB21
AB23
AA2
AA5
AA8
AA11
AA14
AA16
AA18
AA20
AA22
Y13
Y15
Y17
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
Page 17 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Pin List
Emulated LVDS
Output Channel (2)
FF484
F780/H780
for Stratix
III only
E15
N10
N12
N14
N16
N18
M2
M5
M8
M11
M13
M15
M19
L10
L12
L14
L16
L18
L21
L24
L27
K13
K15
K17
K19
J2
J5
J8
J13
J17
H9
H12
H15
H18
H21
H24
H27
F2
F5
E6
E9
E12
E18
E21
E24
E27
C2
B3
B6
H1152 for
Stratix III
only
N16
N18
N20
N22
M2
M5
M8
M11
M15
M17
M19
M21
L12
L15
L18
L21
L24
L27
L30
L33
J2
J5
J8
H9
H12
H15
H18
H21
H24
H27
H30
H33
F2
F5
E6
E9
E12
E15
E18
E24
E27
E30
E33
C2
B3
B6
B9
B12
B15
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
Page 18 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Pin List
Emulated LVDS
Output Channel (2)
FF484
F780/H780
for Stratix
III only
B9
B12
B15
B18
B21
B27
H1152 for
Stratix III
only
B18
B21
B24
B27
B30
B33
P27
P30
P33
N12
AN2
P19
P21
P24
P17
R16
R18
R20
R22
P13
P15
R11
R14
R5
R8
T13
T15
T17
T19
T21
R2
U33
U27
U30
U22
U23
U24
U12
U14
U16
U20
V8
V11
V12
V13
V15
V19
V21
V23
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
Page 19 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
VCCL
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
FF484
L11
K14
P12
N13
N11
N9
M12
M10
L13
K12
K10
J13
J11
Pin List
F780/H780 H1152 for
for Stratix Stratix III
III only
only
W18
W20
W22
V5
Y33
W14
W16
Y19
Y21
Y24
Y27
Y30
R15
U17
L17
T14
V14
AB22
V18
AA13
U11
AA15
U13
AA17
U15
AA19
U17
AA21
T12
Y14
T14
Y16
T16
Y18
R13
Y20
R17
W15
M16
T16
P12
T18
P14
T20
P16
R15
P18
R17
N13
R19
N15
R21
N17
P14
M12
P16
M14
P18
L11
P20
P22
N13
N21
U21
V20
U15
U19
V16
V18
AB14
W17
W19
W21
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
Page 20 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
VCCL
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCPT
VCCPT
VCCPT
VCCPT
DNU
VCCPGM
VCCPGM
TEMPDIODEn
TEMPDIODEp
VCC_CLKIN3C
VCC_CLKIN4C
VCC_CLKIN7C
VCC_CLKIN8C
VCCA_PLL_B1
VCCA_PLL_L2
VCCA_PLL_R2
VCCA_PLL_T1
VCCA_PLL_L3
VCCA_PLL_B2
VCCA_PLL_R3
VCCA_PLL_T2
VCCD_PLL_B1
VCCD_PLL_L2
VCCD_PLL_R2
VCCD_PLL_T1
VCCD_PLL_L3
VCCD_PLL_B2
VCCD_PLL_R3
VCCD_PLL_T2
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1C
VCCIO1C
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
FF484
J9
P14
M14
L9
F17
U17
U6
F6
L12
T16
T6
A6
A5
T12
U10
E11
F13
U11
M18
L5
F12
U12
M17
L6
G12
C18
F19
H22
K17
Pin List
F780/H780 H1152 for
for Stratix Stratix III
III only
only
V14
T18
AB20
V12
AB16
V16
AB18
R11
Y22
M18
T22
N11
R13
L13
N15
L15
N17
V22
U13
N19
W13
G23
J27
AC23
AG27
AB6
AG7
G6
H8
P15
U18
AA21
AD24
Y8
AD10
D4
D4
D3
E5
AB14
AG18
AC13
AE17
F14
H17
F16
K18
AC14
AH18
R22
U28
R7
U7
F15
G18
V28
AH17
V7
G17
AB15
AF18
P22
U26
P7
U9
G15
J18
V26
AF17
V9
J17
E26
H29
H23
L26
H26
G32
B34
N28
P26
M32
R23
V30
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
Page 21 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
VREF Group
Pin Name
/Function
VCCIO1C
VCCIO1C
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2C
VCCIO2C
VCCIO2C
VCCIO2C
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3B
VCCIO3B
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4B
VCCIO4B
VCCIO4C
VCCIO4C
VCCIO4C
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5C
VCCIO5C
VCCIO5C
VCCIO5C
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6C
VCCIO6C
VCCIO6C
VCCIO6C
VCCIO7A
VCCIO7A
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
FF484
R16
Y20
P22
R17
T14
Y13
W10
Y8
R7
Y5
N7
R1
D5
C3
G2
K6
Pin List
F780/H780 H1152 for
for Stratix Stratix III
III only
only
U34
T31
W26
AH32
AD26
AB28
AA22
AG28
AD25
AN34
T26
W25
V22
AD32
W29
W32
AC22
AF25
AF22
AM27
AF25
AL30
AC18
AJ25
AF22
AM25
AF18
AM20
AC15
AH21
AJ18
AC6
AH10
AF4
AF12
AF7
AM3
AD10
AL6
AH13
AM10
AB12
AG16
AF13
AP17
AM13
AA7
AH3
AD3
AD9
AA3
AG6
AB7
AN1
P6
AC3
R3
W4
V1
U5
E3
H7
K3
L10
H7
G3
B1
N7
L7
T10
N3
T3
T6
L3
C7
D5
F7
C8
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
Page 22 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
1A
1C
2A
2C
3A
3B
3C
4A
4B
4C
5A
5C
6A
VREF Group
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3BN0
VREFB3CN0
VREFB4AN0
VREFB4BN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
Pin Name
/Function
VCCIO7A
VCCIO7A
VCCIO7B
VCCIO7B
VCCIO7C
VCCIO7C
VCCIO7C
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8B
VCCIO8B
VCCIO8C
VCCIO8C
VCCIO8C
VCCPD1A
VCCPD1C
VCCPD2A
VCCPD2C
VCCPD3A
VCCPD3B
VCCPD3C
VCCPD4A
VCCPD4B
VCCPD4C
VCCPD5A
VCCPD5C
VCCPD6A
VCCPD6C
VCCPD7A
VCCPD7B
VCCPD7C
VCCPD8A
VCCPD8B
VCCPD8C
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3BN0
VREFB3CN0
VREFB4AN0
VREFB4BN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Optional
Function(s)
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
FF484
F780/H780
for Stratix
III only
F11
C4
E8
C8
C11
G14
C25
F23
E19
C22
B16
G13
C16
G17
J15
K15
R15
N15
L19
N19
U19
R19
W17
R12
W15
W11
P10
P8
N8
H8
L8
W13
V10
T10
M10
P10
K12
H11
K14
K18
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
H13
G18
K18
T18
N18
K16
K22
N22
Y22
U22
AB18
VREFB3CN0
V12
AA16
AB10
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
V10
T5
P5
G5
AA12
W7
T7
J7
Pin List
H1152 for
Stratix III
only
F10
J10
C10
J13
C13
G14
F17
C32
D29
G25
J23
C25
G22
C22
H19
A18
N23
R23
AA23
W23
AC23
AC21
AC19
AC13
AC15
AC17
AB12
Y12
P12
T12
M12
M14
M16
M22
M20
M18
J26
P26
AA26
V27
AG25
AG22
AH20
AG10
AG13
AH16
AF7
AA9
P9
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
Page 23 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Bank
Number
6C
7A
7B
7C
8A
8B
8C
VREF Group
VREFB6CN0
VREFB7AN0
VREFB7BN0
VREFB7CN0
VREFB8AN0
VREFB8BN0
VREFB8CN0
Pin Name
/Function
VREFB6CN0
VREFB7AN0
VREFB7BN0
VREFB7CN0
VREFB8AN0
VREFB8BN0
VREFB8CN0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC (3)
NC (3)
NC (3)
NC (4)
NC (5)
NC (5)
NC (5)
NC (5)
Optional
Function(s)
VREFB6CN0
Configuration Function for
Stratix III Only (1)
Dedicated Tx_Rx
Channel (2)
Emulated LVDS
Output Channel (2)
FF484
K5
F780/H780
for Stratix
III only
M7
G11
VREFB7CN0
E10
H13
G19
VREFB8CN0
E13
H17
AE25
U20
M9
L20
K10
J21
E25
AB22
W10
E4
V9
G7
J9
H8
F6
R24
AD15
P5
E14
E16
AA18
W6
D6
W19
G7
C6
E7
D4
L17
T11
L7
F11
MSEL2
MSEL1
MSEL0
H1152 for
Stratix III
only
U8
H10
H13
G15
H25
H22
G19
DQ Group for
DQS X4 Mode (2)
DQ Group for
DQS X8/X9 Mode (2)
AK30
K26
L25
L11
M25
D32
AL31
AH7
G7
AC10
K9
J9
K10
G6
U29
AJ17
V6
F18
Notes:
®
(1) These pins should be connected on the board to properly configure the FPGA prototype. See Stratix
III device pin table for details.
(2) The individual index number of the pin in this column may not be the same as its companion Stratix III device, but the functionality of the pin is fully migratable.
(3) These NO CONNECT (NC) pins are MSEL configuration input pins in the Stratix III device and should be connected on the board to configure the FPGA prototype.
(4) This NC pin is a VCCBAT pin in the Stratix III device and should be connected for the FPGA prototype.
(5) This NC pin is a VCCPT pin in the Stratix III device and should be connected for the FPGA prototype.
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Pin List
Page 24 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Pin Name
Pin Type (1st, 2nd, &
3rd Function)
VCCL
VCC
RUP[1..8]A
Power
Power
I/O, Input
RDN[1..8]A
I/O, Input
Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected
to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin.
VCCIO[1..8][A,B,C]
Power
These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS,
LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V), HSTL(12, 15, 18), SSTL(15, 18, 2), 3.0-V PCI/PCI-X I/O, and 3.0 V LVTTL I/O standards. VCCIO also supplies power to
the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V), 3.0-V PCI/PCI-X and 3.0 V LVTTL I/O standards.
VREF[1..8][A,B,C]
Power
Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, these pins are used as the voltage-referenced pins for the bank.
VCCA_PLL[L[1:4],R[1:4],T[1:2],B[1:2]]
Power
Analog power for PLLs[L[1:4],R[1:4],T[1:2],B[1:2]]. You must power up these pins even if the PLL is not used. You are advised to keep this pin isolated from other
VCC for better jitter performance.
VCCD_PLL[L[1:4],R[1:4],T[1:2],B[1:2]]
Power
Digital power for PLLs[L[1:4],R[1:4],T[1:2],B[1:2]]. You must power up these pins even if the PLL is not used.
VCCPT
VCCPGM
VCCPD[1..8][A,B,C]
Power
Power
Power
Power supply for the programmable power technology.
Power supply for configuration pins. Can be connected to 1.8 V, 2.5 V or 3.0 V depending on the particular design.
Dedicated power pins. This supply is used to power the I/O pre-drivers. This can be connected to 3.0 V or 2.5 V. VCCPD for 3.0-V I/O standard is 3.0 V, and VCCPD
for 2.5-V/1.8-V/1.2-V I/O standards is 2.5 V.
VCC_CLKIN[3,4,7,8]
GND
DNU
NC
Power
Ground
Do Not Use
No Connect
nIO_PULLUP
Input
TEMPDIODEp
TEMPDIODEn
nCE
Input
Input
Input
Differential clock input power supply for top and bottom I/O banks.
Device ground pins.
Do not connect to power or ground or any other signal; must be left floating.
Do not drive signals into these pins.
Dedicated Configuration/JTAG Pins
Dedicated input that chooses whether the internal pull-up resistors on the user I/O pins are on or off during power up. A logic high (0.9V) turns off the weak pull-ups,
while a logic low turns them on.
Pin used in conjunction with the temperature-sensing diode (bias-high input) inside the HardCopy III device.
Pin used in conjunction with the temperature-sensing diode (bias-low input) inside the HardCopy III device.
Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled.
nCONFIG
Input
Dedicated power up block control input. Pulling this pin low during user-mode will cause the HardCopy III to enter a reset state and tri-state all I/O pins. Returning this
pin to a logic high level will initiate the power up and initialization sequence. It is not available as a user I/O pin.
CONF_DONE
Bidirectional
(open-drain)
Output
Bidirectional
(open-drain)
This is a dedicated power up block status pin. As a status output, the CONF_DONE pin drives low before and during initialization. Driven this pin high indicates that
the device is entering user mode.
Output that drives low when device initialization is complete.
This is a dedicated power up block status pin. The HardCopy III drives nSTATUS low indicates that the device is being initialized. As a status output, the nSTATUS is
pulled low if an error occurs during initialization. As a status input, this pin delays the completion of the Initialization phase when nSTATUS is driven low by an external
source during initialization. It is not available as a user I/O pin.
PORSEL
Input
TCK
TMS
TDI
TDO
TRST
Input
Input
Input
Output
Input
Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high (1.5 V, 1.8 V, 2.5 V,3.0 V) selects a POR time of 12 ms and a logic low selects
POR time of 100 ms.
Dedicated JTAG input pin. Connect TCK to GND if the JTAG circuitry is not used.
Dedicated JTAG input pin. Connect TMS to VCCPD if the JTAG circuitry is not used.
Dedicated JTAG input pin. Connect TDI to VCCPD if the JTAG circuitry is not used.
Dedicated JTAG output pin.
Dedicated active-low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit.
nCEO
nSTATUS
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Pin Description
Supply and Reference Pins
VCCL supplies power to the core voltage power supply pins.
VCC supplies power to the periphery circuitry.
Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected
to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin.
Pin Definitions
Page 25 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Pin Name
Pin Type (1st, 2nd, &
3rd Function)
Pin Description
CLK[1,3,8,10]p
Clock, Input
Clock and PLL Pins
Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins.
CLK[1,3,8,10]n
CLK[0,2,4,5,6,7,9,11..15]p
Clock, Input
I/O, Clock
Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins.
These pins can be used as I/O pins or clock input pins.
CLK[0,2,4,5,6,7,9,11..15]n
PLL_[L1,L4,R1,R4]_CLKp
PLL_[L1,L4,R1,R4]_CLKn
PLL_[L2,L3,R2,R3]_CLKOUT0n
I/O, Clock
Clock, Input
Clock, Input
I/O, Clock
PLL_[L2,L3,R2,R3]_FB_CLKOUT0p
I/O, Clock
These pins can be used as I/O pins or negative clock input pins for differential clock inputs.
Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively.
Dedicated negative clock input pins for dfferential clock input to PLL L1, L4, R1, and R4 respectively.
Each left and right PLL supports 2 clock I/O pins, configured either as 2 single-ended I/O or one differential I/O pair. When using both pins as single-ended I/Os,
PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin.
PLL_[T1,T2,B1,B2]_FBp/CLKOUT1
PLL_[T1,T2,B1,B2]_FBn/CLKOUT2
PLL_[T1,T2,B1,B2]_CLKOUT[3,4]
PLL_[T1,T2,B1,B2]_CLKOUT0[p,n]
I/O, Clock
I/O, Clock
I/O, Clock
I/O, Clock
nCSO
ASDO
DCLK
Output
Output
Input (PS, FPP)
Output (AS)
DIFFIO_RX[##]p/n
I/O, RX channel
DIFFIO_TX[##]p/n
I/O, TX channel
DIFFOUT_[##]p/n
I/O, TX channel
DQS[1..44][T,B], DQS[1..40][L,R]
I/O,DQS
DQSn[1..44][T,B], DQSn[1..40][L,R]
DQ[1..44][T,B],DQ[1..40][L,R]
I/O,DQSn
I/O,DQ
Dual-purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin.
These pins can be used as I/O pins or two single-ended clock ouput pins.
I/O pins that be used as two single-ended clock output pins or one differential clock output pair.
Optional/Dual-Purpose Configuration Pins
Dedicated control signal from Stratix III devices, but kept in HardCopy III for compatibility reasons.
Dedicated control signal from Stratix III devices, but kept in HardCopy III for compatibility reasons.
Dedicated configuration clock pin on Stratix III devices, but kept in HardCopy III for compatibility reasons. It's not required to clock this pin for HardCopy III.
Differential I/O Pins
These are true LVDS receiver channels on side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix
carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.
These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the
negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.
These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os,
including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers.Pins with a "p" suffix carry the positive signal for the differential
channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.
External Memory Interface Pins
Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase-shift circuitry. The shifted DQS signal can also drive to
internal logic.
Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase-shift circuitry.
Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making
pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS
columns in the pin list.
CQ[1..44][T,B], CQ[1..40][L,R]
DQS
Optional data strobe signal for use in QDR II SRAM. These are the pins for echo clocks.
CQn[1..44][T,B], CQn[1..40][L,R]
DQS
Optional complementary data strobe signal for use in QDR II SRAM. These are the pins for echo clocks.
Notes:
(1) These pin definitions are prepared based on the device with the largest density, HC335. Refer to the pin list for the availability of pins in each density.
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Pin Definitions
Page 26 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
7C
6C
6A
VREFB7CN0
1A
PLL_T1
1C
5C
5A
2C
PLL_R2
2A
VREFB2AN0 VREFB2CN0
PLL_L2
3C
VREFB3CN0
PLL_B1
VREFB5AN0 VREFB5CN0
VREFB1CN0 VREFB1AN0
VREFB8CN0
VREFB6CN0 VREFB6AN0
8C
4C
VREFB4CN0
Notes:
1. This is a top view of the silicon die. For flip chip packages, the die is mounted upside down in the package; therefore, to obtain the top package view, flip this diagram on its
vertical axis.
2. This is a pictorial representation only to get an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations.
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Bank & PLL Diagram
Page 27 of 28
Pin Information for HardCopy® III HC325FF484
Version 1.0
Version Number
1.0
Date
10/28/2009
PT-HC325FF484-1.0
Copyright © 2009 Altera Corp.
Changes Made
Initial release.
Revision History
Page 28 of 28