Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 1A 1A VREFB1AN0 VREFB1AN0 1A 1A VREFB1AN0 VREFB1AN0 1A 1A 1A 1A VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 1A VREFB1AN0 1A 1A VREFB1AN0 VREFB1AN0 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function TDI TMS TRST TCK TDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC IO IO IO IO IO IO IO IO IO IO IO NC NC IO IO NC IO IO NC IO IO IO IO NC IO NC IO IO Optional Function(s) PLL_L1_CLKOUT0n PLL_L1_FB_CLKOUT0p RDN1A RUP1A Configuration Function TDI TMS TRST TCK TDO Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFOUT_L1n DIFFOUT_L1p DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFIO_RX_L3n DIFFIO_RX_L3p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFOUT_L6n DIFFOUT_L6p DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFIO_TX_L9n DIFFIO_TX_L9p DIFFOUT_L17n DIFFOUT_L17p DIFFIO_RX_L9p DIFFIO_TX_L10n DIFFOUT_L18p DIFFOUT_L19n DIFFIO_RX_L10n DIFFIO_RX_L10p DIFFIO_TX_L11n DIFFIO_TX_L11p DIFFOUT_L20n DIFFOUT_L20p DIFFOUT_L21n DIFFOUT_L21p DIFFIO_RX_L11p DIFFOUT_L22p DIFFIO_TX_L12p DIFFIO_RX_L12n DIFFOUT_L23p DIFFOUT_L24n Pin List F1932 A36 B36 F36 G35 E36 G34 H34 E37 F37 M33 N33 J34 K34 R31 T31 J35 K35 P31 R30 H36 J36 M35 N35 E38 F38 L36 M36 G37 H37 T30 U30 J37 K37 W31 W30 H40 J40 L35 L34 F40 F39 N34 P34 H38 J38 V31 V30 G40 G39 R33 P32 J39 Dynamic OCT Support No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQSn2L DQS2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ5L DQ5L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ5L DQ5L DQ3L DQ3L DQS6L DQ6L DQS3L/CQ3L DQ3L DQ6L DQ6L DQ7L DQ7L DQ3L DQ3L DQS7L DQ7L Page 1 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 1A VREF VREFB1AN0 1C 1C 1C 1C 1C 1C VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 1C VREFB1CN0 1C VREFB1CN0 1C VREFB1CN0 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. Pin Name/Function IO NC NC IO IO IO IO IO IO NC NC NC IO NC NC NC NC NC NC IO NC IO NC NC IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK1n CLK1p CLK3p CLK3n IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_L12p Emulated LVDS Output Channel DIFFOUT_L24p DIFFIO_RX_L19n DIFFIO_RX_L19p DIFFIO_TX_L20n DIFFIO_TX_L20p DIFFIO_RX_L20n DIFFIO_RX_L20p DIFFOUT_L38n DIFFOUT_L38p DIFFOUT_L39n DIFFOUT_L39p DIFFOUT_L40n DIFFOUT_L40p DIFFIO_RX_L21p DIFFOUT_L42p DIFFIO_RX_L23n DIFFOUT_L46n DIFFIO_RX_L24p DIFFOUT_L48p DIFFIO_TX_L25p DIFFIO_RX_L25n DIFFOUT_L49p DIFFOUT_L50n DIFFIO_TX_L26n DIFFOUT_L51n DIFFIO_RX_L26p DIFFIO_TX_L27n DIFFIO_TX_L27p DIFFIO_RX_L27n DIFFIO_RX_L27p DIFFIO_TX_L28n DIFFIO_TX_L28p DIFFOUT_L52p DIFFOUT_L53n DIFFOUT_L53p DIFFOUT_L54n DIFFOUT_L54p DIFFOUT_L55n DIFFOUT_L55p DIFFIO_RX_L30p DIFFIO_RX_L30n DIFFIO_RX_L31p DIFFIO_RX_L31n DIFFIO_RX_L32p DIFFIO_TX_L32n DIFFIO_RX_L33n DIFFIO_RX_L34p DIFFIO_RX_L35p DIFFOUT_L59p DIFFOUT_L59n DIFFOUT_L61p DIFFOUT_L61n DIFFOUT_L63p DIFFOUT_L64n DIFFOUT_L65n DIFFOUT_L67p DIFFOUT_L69p CLKUSR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 INIT_DONE CRC_ERROR DEV_OE DEV_CLRn PLL_L2_CLKOUT0n PLL_L2_FB_CLKOUT0p CLK1n CLK1p CLK3p CLK3n Pin List F1932 K39 P36 P35 M38 M37 U32 V32 L39 L38 T33 U33 M40 M39 V34 W33 K40 L40 U36 V35 R38 R37 V37 V36 N40 N39 AA33 Y32 P38 P37 U38 U37 R40 P39 Y31 AA31 R39 T39 AA30 AB30 U39 V39 AD39 AC39 AA38 Y38 AB39 AA39 Y39 AF38 W38 AE39 AD38 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 DQSn12L DQS12L DQ12L DQ12L DQSn13L DQS13L DQ12L DQ12L/CQn12L DQ12L DQ12L DQSn12L/DQ12L DQS12L/CQ12L DQ12L DQ12L DQ12L DQ12L DQ12L DQ12L/CQn12L DQ13L DQ12L DQ12L DQSn15L DQSn13L/DQ13L DQ12L DQ15L DQ13L DQ12L DQ16L DQSn16L DQ14L DQ14L DQ16L DQ14L DQS17L DQ17L DQ17L DQ17L DQ17L DQS14L/CQ14L DQ14L DQ14L DQ14L DQ14L DQ18L DQ18L DQS18L DQSn18L DQS19L DQ19L DQ20L DQS20L DQS21L DQ21L DQ21L DQS21L/CQ21L DQSn21L/DQ21L DQ21L/CQn21L DQ21L DQ22L DQS22L/CQ22L DQ22L/CQn22L DQ23L DQ23L DQS23L/CQ23L Page 2 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2B 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2BN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_L35n DIFFIO_TX_L35p DIFFIO_RX_L36p DIFFIO_RX_L37p DIFFIO_RX_L37n DIFFIO_TX_L37p DIFFIO_TX_L37n DIFFIO_RX_L38n DIFFIO_TX_L38p DIFFIO_TX_L38n DIFFIO_RX_L40p DIFFIO_RX_L41p DIFFIO_RX_L42p DIFFIO_RX_L42n DIFFIO_TX_L42p DIFFIO_RX_L43p DIFFIO_RX_L43n DIFFIO_TX_L43p DIFFIO_TX_L43n DIFFIO_RX_L44p DIFFIO_RX_L44n DIFFIO_TX_L44p DIFFIO_TX_L44n DIFFIO_RX_L45p DIFFIO_RX_L46p DIFFIO_RX_L46n DIFFIO_TX_L46p DIFFIO_TX_L46n DIFFIO_RX_L47p DIFFIO_RX_L47n DIFFIO_TX_L47p DIFFIO_TX_L47n DIFFIO_TX_L48p DIFFIO_TX_L48n DIFFIO_RX_L49p DIFFIO_RX_L49n DIFFIO_TX_L49p DIFFIO_TX_L49n DIFFIO_RX_L50p DIFFIO_RX_L50n DIFFIO_TX_L50p DIFFIO_TX_L50n DIFFIO_RX_L51p DIFFIO_RX_L51n DIFFIO_TX_L51p DIFFIO_TX_L51n DIFFIO_RX_L52p DIFFIO_RX_L52n DIFFIO_TX_L52p DIFFIO_TX_L52n DIFFIO_RX_L53p DIFFIO_RX_L53n Pin List Emulated LVDS Output Channel DIFFOUT_L69n DIFFOUT_L70p DIFFOUT_L71p DIFFOUT_L73p DIFFOUT_L73n DIFFOUT_L74p DIFFOUT_L74n DIFFOUT_L75n DIFFOUT_L76p DIFFOUT_L76n DIFFOUT_L79p DIFFOUT_L81p DIFFOUT_L83p DIFFOUT_L83n DIFFOUT_L84p DIFFOUT_L85p DIFFOUT_L85n DIFFOUT_L86p DIFFOUT_L86n DIFFOUT_L87p DIFFOUT_L87n DIFFOUT_L88p DIFFOUT_L88n DIFFOUT_L89p DIFFOUT_L91p DIFFOUT_L91n DIFFOUT_L92p DIFFOUT_L92n DIFFOUT_L93p DIFFOUT_L93n DIFFOUT_L94p DIFFOUT_L94n DIFFOUT_L96p DIFFOUT_L96n DIFFOUT_L97p DIFFOUT_L97n DIFFOUT_L98p DIFFOUT_L98n DIFFOUT_L99p DIFFOUT_L99n DIFFOUT_L100p DIFFOUT_L100n DIFFOUT_L101p DIFFOUT_L101n DIFFOUT_L102p DIFFOUT_L102n DIFFOUT_L103p DIFFOUT_L103n DIFFOUT_L104p DIFFOUT_L104n DIFFOUT_L105p DIFFOUT_L105n F1932 AC38 AF32 AH39 AG39 AF39 AD29 AD30 AG38 AE30 AE31 AJ39 AL39 AM38 AM39 AL35 AK38 AK39 AH31 AG32 AL36 AM37 AF30 AG31 AN39 AR39 AP39 AN35 AM35 AN37 AN38 AP35 AP36 AM33 AL34 AU39 AT39 AN33 AN34 AR37 AP37 AJ31 AJ32 AT37 AT38 AR34 AP34 AU36 AU37 AK31 AK32 AW36 AW37 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQSn21L DQ21L DQ22L DQS22L DQSn22L DQ23L DQ23L DQSn23L DQ23L DQ23L DQS for X8/X9 for F1932 DQ22L DQ22L DQ23L DQS23L/CQ23L DQSn23L/DQ23L DQ23L DQ23L DQ23L DQ23L DQ23L DQS25L DQ26L DQ26L DQ26L DQS26L DQSn26L DQ27L DQ27L DQS27L DQSn27L DQ27L DQ27L DQ27L DQ27L DQ27L DQS27L/CQ27L DQSn27L/DQ27L DQ27L DQ27L DQ27L/CQn27L DQ27L DQ27L DQ27L DQS28L DQSn28L DQ28L DQ28L DQ29L DQ29L DQ29L DQ29L DQ30L DQ30L DQS30L DQSn30L DQ30L DQ30L DQ31L DQ31L DQ31L DQ31L DQS31L DQSn31L DQ32L DQ32L DQS32L DQSn32L DQ32L DQ32L DQ33L DQ33L DQ32L DQ32L DQ32L DQ32L DQ32L DQ32L DQ32L/CQn32L DQ32L DQ32L DQ32L DQ33L DQ33L DQ33L DQ33L DQS33L/CQ33L DQSn33L/DQ33L DQ33L DQ33L DQ33L/CQn33L DQ33L DQ33L DQ33L DQ34L DQ34L DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 DQSn23L/DQ23L DQ23L DQ23L DQ23L/CQn23L DQ23L DQ23L DQ23L DQ23L DQ23L DQ23L DQ34L DQ34L DQ34L DQ34L DQ34L DQ34L DQ34L DQ34L DQS34L/CQ34L DQSn34L/DQ34L DQ34L DQ34L DQ34L DQ34L Page 3 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO PLL_L4_CLKp PLL_L4_CLKn nCONFIG nSTATUS CONF_DONE PORSEL nCE IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function RUP2A RDN2A PLL_L4_FB_CLKOUT0p PLL_L4_CLKOUT0n PLL_L4_CLKp PLL_L4_CLKn Dedicated Tx/Rx Channel DIFFIO_TX_L53p DIFFIO_TX_L53n DIFFIO_TX_L54p DIFFIO_TX_L54n DIFFIO_RX_L55p DIFFIO_RX_L55n DIFFIO_TX_L55p DIFFIO_TX_L55n Emulated LVDS Output Channel DIFFOUT_L106p DIFFOUT_L106n DIFFOUT_L108p DIFFOUT_L108n DIFFOUT_L109p DIFFOUT_L109n DIFFOUT_L110p DIFFOUT_L110n DIFFIO_TX_L56p DIFFIO_TX_L56n DIFFOUT_L112p DIFFOUT_L112n nCONFIG nSTATUS CONF_DONE nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFIO_RX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_RX_B8n DIFFIO_RX_B8p Pin List DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n F1932 AR35 AT36 AU34 AT34 AV37 AV38 AV35 AU35 AY37 AY38 AJ30 AH30 AY39 AY40 BA36 AY36 AW38 AY35 AW35 BB35 BC35 BD35 BC34 BD34 BD33 BD32 BC32 BB32 BB31 BD31 BC31 AW34 BA33 BA34 AY34 AW33 BB33 BA31 AY31 BA32 AY32 AW31 AV31 AT33 AT32 AV34 AV33 AU32 AV32 AR32 AR31 AT31 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQ33L DQ33L DQ34L DQ34L DQS34L DQSn34L DQ34L DQ34L DQS for X8/X9 for F1932 DQ34L DQ34L DQ34L DQ34L DQ34L/CQn34L DQ34L DQ34L DQ34L DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 DQ34L DQ34L DQ34L DQ34L DQ34L DQ34L DQ34L DQ34L DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQSn6B DQS6B DQ6B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B Page 4 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_RX_B12n DIFFIO_RX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p DIFFIO_RX_B14n DIFFIO_RX_B14p DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_RX_B16n DIFFIO_RX_B16p DIFFIO_RX_B17n DIFFIO_RX_B17p DIFFIO_RX_B18n DIFFIO_RX_B18p DIFFIO_RX_B19n DIFFIO_RX_B19p DIFFIO_RX_B20n DIFFIO_RX_B20p DIFFIO_RX_B21n DIFFIO_RX_B21p Pin List Emulated LVDS Output Channel DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33n DIFFOUT_B33p DIFFOUT_B34n DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B35p DIFFOUT_B36n DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B37p DIFFOUT_B38n DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B39p DIFFOUT_B40n DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B41p DIFFOUT_B42n DIFFOUT_B42p DIFFOUT_B43n F1932 AU31 AT30 AR30 AM30 AM31 AN31 AN30 AL32 AN29 AM29 AL29 AK29 AK30 AL28 AK28 BD30 BD29 BC29 BB30 BD28 BC28 BD27 BD26 BC26 BB26 BD25 BC25 AY29 AY28 BA30 BA29 AW29 AW30 BB28 BA28 AY26 AW26 BA27 BA26 AT29 AR29 AV29 AU29 AU28 AV28 AW28 AV27 AU27 AT26 AV26 AU26 AN28 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQ6B DQ6B DQ6B DQ7B DQ7B DQSn7B DQS7B DQ7B DQ7B DQSn8B DQS8B DQ8B DQ8B DQ8B DQ8B DQ9B DQ9B DQSn9B DQS9B DQ9B DQ9B DQSn10B DQS10B DQ10B DQ10B DQ10B DQ10B DQ11B DQ11B DQSn11B DQS11B DQ11B DQ11B DQSn12B DQS12B DQ12B DQ12B DQ12B DQ12B DQ13B DQ13B DQSn13B DQS13B DQ13B DQ13B DQSn14B DQS14B DQ14B DQ14B DQ14B DQ14B DQ15B DQS for X8/X9 for F1932 DQ3B DQ3B DQ3B DQ4B DQ4B DQ4B DQ4B/CQn4B DQ4B DQ4B DQSn4B/DQ4B DQS4B/CQ4B DQ4B DQ4B DQ4B DQ4B DQ9B DQ9B DQ9B DQ9B/CQn9B DQ9B DQ9B DQSn9B/DQ9B DQS9B/CQ9B DQ9B DQ9B DQ9B DQ9B DQ10B DQ10B DQ10B DQ10B/CQn10B DQ10B DQ10B DQSn10B/DQ10B DQS10B/CQ10B DQ10B DQ10B DQ10B DQ10B DQ11B DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQSn11B/DQ11B DQS11B/CQ11B DQ11B DQ11B DQ11B DQ11B DQ12B DQS for X16/ X18 for F1932 DQ2B DQ2B DQ2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B/CQn9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQSn9B/DQ9B DQS9B/CQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B/CQn10B DQ10B DQ10B DQ10B DQ10B DQ10B DQS for X32/ X36 for F1932 DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B/CQn9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQSn9B/DQ9B DQS9B/CQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B Page 5 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 4C 4C 4C 4C 4C 4C 4C 4C 4C PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B22n DIFFIO_RX_B22p DIFFIO_RX_B23n DIFFIO_RX_B23p DIFFIO_RX_B24n DIFFIO_RX_B24p RDN3C RUP3C DIFFIO_RX_B25n DIFFIO_RX_B25p DIFFIO_RX_B26n DIFFIO_RX_B26p DIFFIO_RX_B27n DIFFIO_RX_B27p DIFFIO_RX_B28n DIFFIO_RX_B28p DIFFIO_RX_B29n DIFFIO_RX_B29p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 DIFFIO_RX_B30n DIFFIO_RX_B30p PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p CLK6p CLK6n CLK7p CLK7n PLL_B2_FBp/CLKOUT1 PLL_B2_FBn/CLKOUT2 PLL_B2_CLKOUT0p PLL_B2_CLKOUT0n DIFFIO_RX_B31n DIFFIO_RX_B31p DIFFIO_RX_B32n DIFFIO_RX_B32p DIFFIO_RX_B33p DIFFIO_RX_B33n DIFFIO_RX_B34p DIFFIO_RX_B34n DIFFIO_RX_B35p Pin List Emulated LVDS Output Channel DIFFOUT_B43p DIFFOUT_B44n DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B45p DIFFOUT_B46n DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B47p DIFFOUT_B48n DIFFOUT_B48p DIFFOUT_B49n DIFFOUT_B49p DIFFOUT_B50n DIFFOUT_B50p DIFFOUT_B51n DIFFOUT_B51p DIFFOUT_B52n DIFFOUT_B52p DIFFOUT_B53n DIFFOUT_B53p DIFFOUT_B54n DIFFOUT_B54p DIFFOUT_B55n DIFFOUT_B55p DIFFOUT_B56n DIFFOUT_B56p DIFFOUT_B57n DIFFOUT_B57p DIFFOUT_B58n DIFFOUT_B58p DIFFOUT_B59n DIFFOUT_B59p DIFFOUT_B60n DIFFOUT_B60p DIFFOUT_B61n DIFFOUT_B61p DIFFOUT_B62n DIFFOUT_B62p DIFFOUT_B63n DIFFOUT_B63p DIFFOUT_B64n DIFFOUT_B64p DIFFOUT_B65p DIFFOUT_B65n DIFFOUT_B66p DIFFOUT_B66n DIFFOUT_B67p DIFFOUT_B67n DIFFOUT_B68p DIFFOUT_B68n DIFFOUT_B69p F1932 AR27 AR28 AP28 AM28 AR26 AK27 AK26 AM27 AL26 AN26 AM26 BB25 AW25 BA25 AY25 BA24 AW24 BD24 BD23 BA23 AY23 BC23 BB23 AW23 AV23 AV25 AV24 AT23 AU23 AR25 AP25 AM25 AN24 AT25 AT24 AM24 AL23 AN23 AM23 AK23 AJ24 AL25 AK24 AK21 AL22 AJ22 AK22 AM21 AM22 AU22 AV22 AT20 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQ15B DQSn15B DQS15B DQ15B DQ15B DQSn16B DQS16B DQ16B DQ16B DQ16B DQ16B DQ17B DQ17B DQSn17B DQS17B DQ17B DQ17B DQSn18B DQS18B DQ18B DQ18B DQ18B DQ18B DQ19B DQ19B DQSn19B DQS19B DQ19B DQ19B DQS for X8/X9 for F1932 DQ12B DQ12B DQ12B/CQn12B DQ12B DQ12B DQSn12B/DQ12B DQS12B/CQ12B DQ12B DQ12B DQ12B DQ12B DQ17B DQ17B DQ17B DQ17B/CQn17B DQ17B DQ17B DQSn17B/DQ17B DQS17B/CQ17B DQ17B DQ17B DQ17B DQ17B DQS for X16/ X18 for F1932 DQ10B DQSn10B/DQ10B DQS10B/CQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQS for X32/ X36 for F1932 DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B Page 6 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B35n PLL_B2_CLKOUT3 PLL_B2_CLKOUT4 DIFFIO_RX_B36p DIFFIO_RX_B36n DIFFIO_RX_B37p DIFFIO_RX_B37n DIFFIO_RX_B38p DIFFIO_RX_B38n DIFFIO_RX_B39p DIFFIO_RX_B39n DIFFIO_RX_B40p DIFFIO_RX_B40n DIFFIO_RX_B41p DIFFIO_RX_B41n DIFFIO_RX_B42p DIFFIO_RX_B42n DIFFIO_RX_B43p DIFFIO_RX_B43n DIFFIO_RX_B44p DIFFIO_RX_B44n DIFFIO_RX_B45p DIFFIO_RX_B45n DIFFIO_RX_B46p DIFFIO_RX_B46n DIFFIO_RX_B47p DIFFIO_RX_B47n DIFFIO_RX_B48p Pin List Emulated LVDS Output Channel DIFFOUT_B69n DIFFOUT_B70p DIFFOUT_B70n DIFFOUT_B71p DIFFOUT_B71n DIFFOUT_B72p DIFFOUT_B72n DIFFOUT_B73p DIFFOUT_B73n DIFFOUT_B74p DIFFOUT_B74n DIFFOUT_B75p DIFFOUT_B75n DIFFOUT_B76p DIFFOUT_B76n DIFFOUT_B77p DIFFOUT_B77n DIFFOUT_B78p DIFFOUT_B78n DIFFOUT_B79p DIFFOUT_B79n DIFFOUT_B80p DIFFOUT_B80n DIFFOUT_B81p DIFFOUT_B81n DIFFOUT_B82p DIFFOUT_B82n DIFFOUT_B83p DIFFOUT_B83n DIFFOUT_B84p DIFFOUT_B84n DIFFOUT_B85p DIFFOUT_B85n DIFFOUT_B86p DIFFOUT_B86n DIFFOUT_B87p DIFFOUT_B87n DIFFOUT_B88p DIFFOUT_B88n DIFFOUT_B89p DIFFOUT_B89n DIFFOUT_B90p DIFFOUT_B90n DIFFOUT_B91p DIFFOUT_B91n DIFFOUT_B92p DIFFOUT_B92n DIFFOUT_B93p DIFFOUT_B93n DIFFOUT_B94p DIFFOUT_B94n DIFFOUT_B95p F1932 AU20 AT21 AR20 AN20 AP20 BA22 BB22 BD21 BD22 BB21 BC22 BC20 BD20 BA20 BB20 BC19 BD19 AY22 AW22 AW20 AY20 AV20 AW21 AN19 AP19 AM18 AN18 AN17 AP17 AK20 AL20 AM19 AM20 AL19 AJ20 AV18 AV19 AT19 AU19 AR19 AT18 AT17 AU17 AU16 AV16 AR16 AT16 BA18 BA19 AW19 AY19 AW17 Dynamic OCT Support No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 DQ20B DQ20B DQS20B DQSn20B DQ20B DQ20B DQ21B DQ21B DQ21B DQ21B DQS21B DQSn21B DQ22B DQ22B DQS22B DQSn22B DQ22B DQ22B DQ23B DQ23B DQ23B DQ23B DQS23B DQSn23B DQ24B DQ24B DQS24B DQSn24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B DQSn25B DQ26B DQ26B DQS26B DQSn26B DQ26B DQ26B DQ27B DQ27B DQ27B DQ27B DQS27B DQ22B DQ22B DQ22B DQ22B DQS22B/CQ22B DQSn22B/DQ22B DQ22B DQ22B DQ22B/CQn22B DQ22B DQ22B DQ22B DQ27B DQ27B DQ27B DQ27B DQS27B/CQ27B DQSn27B/DQ27B DQ27B DQ27B DQ27B/CQn27B DQ27B DQ27B DQ27B DQ28B DQ28B DQ28B DQ28B DQS28B/CQ28B DQSn28B/DQ28B DQ28B DQ28B DQ28B/CQn28B DQ28B DQ28B DQ28B DQ29B DQ29B DQ29B DQ29B DQS29B/CQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQS29B/CQ29B DQSn29B/DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B/CQn29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQS30B/CQ30B DQSn30B/DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B/CQn30B Page 7 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B48n DIFFIO_RX_B49p DIFFIO_RX_B49n DIFFIO_RX_B50p DIFFIO_RX_B50n DIFFIO_RX_B51p DIFFIO_RX_B51n DIFFIO_RX_B52p DIFFIO_RX_B52n DIFFIO_RX_B53p DIFFIO_RX_B53n DIFFIO_RX_B54p DIFFIO_RX_B54n DIFFIO_RX_B55p DIFFIO_RX_B55n DIFFIO_RX_B56p DIFFIO_RX_B56n DIFFIO_RX_B57p DIFFIO_RX_B57n DIFFIO_RX_B58p DIFFIO_RX_B58n DIFFIO_RX_B59p DIFFIO_RX_B59n DIFFIO_RX_B60p DIFFIO_RX_B60n DIFFIO_RX_B61p Pin List Emulated LVDS Output Channel DIFFOUT_B95n DIFFOUT_B96p DIFFOUT_B96n DIFFOUT_B97p DIFFOUT_B97n DIFFOUT_B98p DIFFOUT_B98n DIFFOUT_B99p DIFFOUT_B99n DIFFOUT_B100p DIFFOUT_B100n DIFFOUT_B101p DIFFOUT_B101n DIFFOUT_B102p DIFFOUT_B102n DIFFOUT_B103p DIFFOUT_B103n DIFFOUT_B104p DIFFOUT_B104n DIFFOUT_B105p DIFFOUT_B105n DIFFOUT_B106p DIFFOUT_B106n DIFFOUT_B107p DIFFOUT_B107n DIFFOUT_B108p DIFFOUT_B108n DIFFOUT_B109p DIFFOUT_B109n DIFFOUT_B110p DIFFOUT_B110n DIFFOUT_B111p DIFFOUT_B111n DIFFOUT_B112p DIFFOUT_B112n DIFFOUT_B113p DIFFOUT_B113n DIFFOUT_B114p DIFFOUT_B114n DIFFOUT_B115p DIFFOUT_B115n DIFFOUT_B116p DIFFOUT_B116n DIFFOUT_B117p DIFFOUT_B117n DIFFOUT_B118p DIFFOUT_B118n DIFFOUT_B119p DIFFOUT_B119n DIFFOUT_B120p DIFFOUT_B120n DIFFOUT_B121p F1932 AW18 BA15 BA16 AY16 AY17 AW15 AW16 BB18 BC17 BB17 BA17 BD17 BD18 BB15 BC16 BD15 BD16 BC14 BD14 AJ18 AK18 AM16 AM17 AK17 AL17 AK16 AJ16 AM14 AM15 AL14 AK15 AU14 AV15 AT14 AU13 AT12 AT13 AR14 AR13 AP16 AR15 AN15 AN14 AY14 BA14 AV14 AW14 AY13 BA13 AV13 BA12 AW12 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQSn27B DQ28B DQ28B DQS28B DQSn28B DQ28B DQ28B DQ29B DQ29B DQ29B DQ29B DQS29B DQSn29B DQ30B DQ30B DQS30B DQSn30B DQ30B DQ30B DQ31B DQ31B DQ31B DQ31B DQS31B DQSn31B DQ32B DQ32B DQS32B DQSn32B DQ32B DQ32B DQ33B DQ33B DQ33B DQ33B DQS33B DQSn33B DQ34B DQ34B DQS34B DQSn34B DQ34B DQ34B DQ35B DQ35B DQ35B DQ35B DQS35B DQSn35B DQ36B DQ36B DQS36B DQS for X8/X9 for F1932 DQSn29B/DQ29B DQ29B DQ29B DQ29B/CQn29B DQ29B DQ29B DQ29B DQ30B DQ30B DQ30B DQ30B DQS30B/CQ30B DQSn30B/DQ30B DQ30B DQ30B DQ30B/CQn30B DQ30B DQ30B DQ30B DQ35B DQ35B DQ35B DQ35B DQS35B/CQ35B DQSn35B/DQ35B DQ35B DQ35B DQ35B/CQn35B DQ35B DQ35B DQ35B DQ36B DQ36B DQ36B DQ36B DQS36B/CQ36B DQSn36B/DQ36B DQ36B DQ36B DQ36B/CQn36B DQ36B DQ36B DQ36B DQ37B DQ37B DQ37B DQ37B DQS37B/CQ37B DQSn37B/DQ37B DQ37B DQ37B DQ37B/CQn37B DQS for X16/ X18 for F1932 DQ30B DQ30B DQ30B DQS30B/CQ30B DQSn30B/DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B/CQn30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQS37B/CQ37B DQSn37B/DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B/CQn37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQS38B/CQ38B DQS for X32/ X36 for F1932 DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQS38B/CQ38B DQSn38B/DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B/CQn38B DQ38B DQ38B DQ38B DQ38B Page 8 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nIO_PULLUP nCEO DCLK nCSO ASDO PLL_R4_CLKn PLL_R4_CLKp IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B61n DIFFIO_RX_B62p DIFFIO_RX_B62n DIFFIO_RX_B63p DIFFIO_RX_B63n RUP4A RDN4A DIFFIO_RX_B64p DIFFIO_RX_B64n Emulated LVDS Output Channel DIFFOUT_B121n DIFFOUT_B122p DIFFOUT_B122n DIFFOUT_B123p DIFFOUT_B123n DIFFOUT_B124p DIFFOUT_B124n DIFFOUT_B125p DIFFOUT_B125n DIFFOUT_B126p DIFFOUT_B126n DIFFOUT_B127p DIFFOUT_B127n DIFFOUT_B128p DIFFOUT_B128n nIO_PULLUP nCEO DCLK nCSO ASDO PLL_R4_CLKn PLL_R4_CLKp PLL_R4_CLKOUT0n PLL_R4_FB_CLKOUT0p RDN5A RUP5A DIFFIO_TX_R1n DIFFIO_TX_R1p DIFFOUT_R1n DIFFOUT_R1p DIFFIO_TX_R2n DIFFIO_TX_R2p DIFFIO_RX_R2n DIFFIO_RX_R2p DIFFIO_TX_R3n DIFFIO_TX_R3p DIFFIO_RX_R3n DIFFIO_RX_R3p DIFFIO_TX_R4n DIFFIO_TX_R4p DIFFIO_RX_R4n DIFFIO_RX_R4p DIFFIO_TX_R5n DIFFIO_TX_R5p DIFFIO_RX_R5n DIFFIO_RX_R5p DIFFIO_TX_R6n DIFFIO_TX_R6p DIFFIO_RX_R6n DIFFIO_RX_R6p DIFFIO_TX_R7n DIFFIO_TX_R7p DIFFIO_RX_R7p DIFFIO_TX_R8n DIFFIO_TX_R8p DIFFIO_RX_R8n DIFFOUT_R3n DIFFOUT_R3p DIFFOUT_R4n DIFFOUT_R4p DIFFOUT_R5n DIFFOUT_R5p DIFFOUT_R6n DIFFOUT_R6p DIFFOUT_R7n DIFFOUT_R7p DIFFOUT_R8n DIFFOUT_R8p DIFFOUT_R9n DIFFOUT_R9p DIFFOUT_R10n DIFFOUT_R10p DIFFOUT_R11n DIFFOUT_R11p DIFFOUT_R12n DIFFOUT_R12p DIFFOUT_R13n DIFFOUT_R13p DIFFOUT_R14p DIFFOUT_R15n DIFFOUT_R15p DIFFOUT_R16n Pin List F1932 AY11 AV12 BA11 BB14 BC13 BB12 BB13 BD12 BD13 BD10 BD11 BC10 BC11 BA10 BB10 AV11 AW7 AY9 BA9 AW10 AY5 AY6 AR10 AP10 AY7 AY8 AR8 AP9 AV7 AV8 AK14 AJ14 AV10 AU10 AU11 AT11 AW8 AW9 AN11 AM11 AU8 AU9 AN12 AM12 AR7 AT8 AH14 AG15 AV6 AR11 AP11 AT6 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQSn36B DQ36B DQ36B DQ37B DQ37B DQ37B DQ37B DQS37B DQSn37B DQ38B DQ38B DQS38B DQSn38B DQ38B DQ38B DQS for X8/X9 for F1932 DQ37B DQ37B DQ37B DQ38B DQ38B DQ38B DQ38B DQS38B/CQ38B DQSn38B/DQ38B DQ38B DQ38B DQ38B/CQn38B DQ38B DQ38B DQ38B DQS for X16/ X18 for F1932 DQSn38B/DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B/CQn38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ1R DQ1R DQSn1R DQS1R DQ1R DQ1R DQSn2R DQS2R DQ2R DQ2R DQ2R DQ2R DQ3R DQ3R DQSn3R DQS3R DQ3R DQ3R DQSn4R DQS4R DQ4R DQ4R DQ4R DQ5R DQ5R DQSn5R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R/CQn2R DQ2R DQ2R DQSn2R/DQ2R DQS2R/CQ2R DQ2R DQ2R DQ2R DQ3R DQ3R DQ3R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQS for X32/ X36 for F1932 DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B Page 9 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 6C 6C 6C 6C 6C VREF VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 6C 6C 6C VREFB6CN0 VREFB6CN0 VREFB6CN0 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK8n CLK8p CLK10p CLK10n IO IO IO NC IO IO IO Optional Function(s) CLK9p CLK8n CLK8p CLK10p CLK10n CLK11p PLL_R2_FB_CLKOUT0p PLL_R2_CLKOUT0n Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_R8p DIFFIO_TX_R9p DIFFIO_TX_R10n DIFFIO_TX_R10p DIFFIO_RX_R10p DIFFIO_TX_R11n DIFFIO_TX_R11p DIFFIO_RX_R11n DIFFIO_RX_R11p DIFFIO_TX_R12n DIFFIO_TX_R12p DIFFIO_RX_R12p DIFFIO_TX_R13n DIFFIO_TX_R13p DIFFIO_TX_R14n DIFFIO_TX_R14p DIFFIO_RX_R14p DIFFIO_TX_R15p DIFFIO_RX_R15n DIFFIO_RX_R15p DIFFIO_TX_R16p DIFFIO_RX_R16n DIFFIO_RX_R16p DIFFIO_RX_R17n DIFFIO_RX_R19n DIFFIO_RX_R19p DIFFIO_TX_R20n DIFFIO_TX_R20p DIFFIO_RX_R20p DIFFIO_RX_R21p DIFFIO_TX_R22n DIFFIO_TX_R22p DIFFIO_RX_R22n DIFFIO_RX_R22p DIFFIO_RX_R23n DIFFIO_RX_R24n DIFFIO_RX_R24p DIFFIO_RX_R25n DIFFIO_TX_R26n DIFFIO_RX_R26p DIFFIO_RX_R28p Emulated LVDS Output Channel DIFFOUT_R16p DIFFOUT_R17p DIFFOUT_R19n DIFFOUT_R19p DIFFOUT_R20p DIFFOUT_R21n DIFFOUT_R21p DIFFOUT_R22n DIFFOUT_R22p DIFFOUT_R23n DIFFOUT_R23p DIFFOUT_R24p DIFFOUT_R25n DIFFOUT_R25p DIFFOUT_R27n DIFFOUT_R27p DIFFOUT_R28p DIFFOUT_R29p DIFFOUT_R30n DIFFOUT_R30p DIFFOUT_R31p DIFFOUT_R32n DIFFOUT_R32p DIFFOUT_R34n DIFFOUT_R38n DIFFOUT_R38p DIFFOUT_R39n DIFFOUT_R39p DIFFOUT_R40p DIFFOUT_R42p DIFFOUT_R43n DIFFOUT_R43p DIFFOUT_R44n DIFFOUT_R44p DIFFOUT_R46n DIFFOUT_R48n DIFFOUT_R48p DIFFOUT_R50n DIFFOUT_R51n DIFFOUT_R52p DIFFOUT_R56p DIFFIO_RX_R29p DIFFIO_TX_R29p DIFFIO_TX_R29n DIFFOUT_R57p DIFFOUT_R58p DIFFOUT_R58n DIFFIO_RX_R30n DIFFIO_RX_R31p DIFFIO_TX_R31p DIFFOUT_R59n DIFFOUT_R61p DIFFOUT_R62p Pin List F1932 AT7 AL13 AT9 AT10 AR6 AN8 AN9 AP6 AN7 AL10 AL11 AN6 AF15 AE16 AG13 AG14 AL6 AJ13 AL8 AL9 AF13 AM6 AM7 AK7 AK6 AJ7 AD15 AC15 AH6 AJ6 AE14 AD14 AG6 AF6 AG7 AA6 Y6 AD7 AA7 AE6 AB6 AC6 AD6 W6 V6 V7 Y14 AA14 U8 U7 U6 Y15 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Yes Yes Yes Yes DQS for X4 for F1932 DQS5R DQ5R DQ6R DQ6R DQ6R DQ7R DQ7R DQSn7R DQS7R DQ7R DQ7R DQS for X8/X9 for F1932 DQ3R/CQn3R DQ3R DQ3R DQ3R DQ3R DQ8R DQ8R DQ8R DQ8R DQS9R DQ9R DQ9R DQ9R DQ10R DQSn10R DQS10R DQ8R DQ8R DQ8R DQ8R DQS8R/CQ8R DQ8R DQ8R DQ8R DQSn12R DQS12R DQ12R DQ12R DQS13R DQ13R DQ14R DQ14R DQSn14R DQS14R DQSn15R DQ15R DQ15R DQSn16R DQ16R DQS17R DQ12R DQ12R/CQn12R DQ12R DQ12R DQS12R/CQ12R DQ12R DQ13R DQ13R DQ13R DQ13R/CQn13R DQSn13R/DQ13R DQ13R DQ13R DQ14R DQ14R DQS14R/CQ14R DQ18R DQS18R DQ19R DQ21R DQS21R/CQ21R DQ21R DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 DQ12R DQ12R DQ12R DQ12R DQ12R/CQn12R DQ12R DQ12R DQ12R DQSn12R/DQ12R DQS12R/CQ12R DQ12R DQ12R DQ12R Page 10 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 6C 6C 6C VREF VREFB6CN0 VREFB6CN0 VREFB6CN0 6C VREFB6CN0 6C 6C VREFB6CN0 VREFB6CN0 6C VREFB6CN0 6C 6C 6C 6C 6C 6C 6C 6A VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6AN0 6A 6A 6A 6A 6A 6A 6A 6A VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 6A 6A 6A 6A 6A VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 6A VREFB6AN0 6A 6A 6A VREFB6AN0 VREFB6AN0 VREFB6AN0 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO NC NC IO NC NC NC IO IO NC NC IO NC NC NC NC NC NC NC IO IO IO IO IO IO IO IO NC IO IO IO IO IO IO IO IO NC NC IO IO IO IO IO NC IO NC IO IO IO NC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_TX_R31n DIFFIO_RX_R32p DIFFIO_RX_R32n Emulated LVDS Output Channel DIFFOUT_R62n DIFFOUT_R63p DIFFOUT_R63n DIFFIO_RX_R33p DIFFOUT_R65p DIFFIO_RX_R34p DIFFIO_RX_R34n DIFFOUT_R67p DIFFOUT_R67n DIFFIO_RX_R35p DIFFOUT_R69p DIFFIO_RX_R37p DIFFIO_RX_R37n DIFFIO_TX_R37p DIFFIO_TX_R37n DIFFIO_RX_R38p DIFFIO_TX_R38p DIFFIO_TX_R38n DIFFIO_RX_R45p DIFFOUT_R73p DIFFOUT_R73n DIFFOUT_R74p DIFFOUT_R74n DIFFOUT_R75p DIFFOUT_R76p DIFFOUT_R76n DIFFOUT_R89p DIFFIO_TX_R45p DIFFIO_TX_R45n DIFFIO_RX_R46p DIFFIO_RX_R46n DIFFIO_TX_R46p DIFFIO_TX_R46n DIFFIO_RX_R47p DIFFIO_RX_R47n DIFFOUT_R90p DIFFOUT_R90n DIFFOUT_R91p DIFFOUT_R91n DIFFOUT_R92p DIFFOUT_R92n DIFFOUT_R93p DIFFOUT_R93n DIFFIO_RX_R48p DIFFIO_RX_R48n DIFFIO_TX_R48p DIFFIO_TX_R48n DIFFIO_RX_R49p DIFFOUT_R95p DIFFOUT_R95n DIFFOUT_R96p DIFFOUT_R96n DIFFOUT_R97p DIFFIO_TX_R49p DIFFOUT_R98p DIFFIO_RX_R50p DIFFIO_RX_R50n DIFFIO_TX_R50p DIFFOUT_R99p DIFFOUT_R99n DIFFOUT_R100p Pin List F1932 AA15 N6 P6 Y12 AA12 T6 R5 V10 V9 P7 R6 W12 V11 L6 L5 U12 V12 M5 N5 P8 R8 L7 M6 W14 V13 K6 M8 N8 J6 J5 U14 U13 J8 J7 V15 V14 L9 K8 P10 P9 H8 H7 M12 M11 H6 H5 R13 R12 F8 F7 N12 P11 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQ19R DQS19R DQSn19R DQS for X8/X9 for F1932 DQ21R DQ21R/CQn21R DQ21R DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 DQ20R DQ22R DQ23R DQS20R DQSn20R DQS22R/CQ22R DQSn22R/DQ22R DQ23R DQ23R DQS21R DQ22R/CQn22R DQS23R/CQ23R DQS22R DQSn22R DQ23R DQ23R DQS23R DQ23R DQ23R DQS23R/CQ23R DQSn23R/DQ23R DQ23R DQ23R DQ23R/CQn23R DQ23R DQ23R DQ23R/CQn23R DQ23R DQ23R DQ23R DQ23R DQ23R DQ23R DQ28R DQ28R DQS28R DQSn28R DQ28R DQ28R DQ29R DQ29R DQ32R DQ32R DQS29R DQSn29R DQ30R DQ30R DQS30R DQS32R/CQ32R DQSn32R/DQ32R DQ32R DQ32R DQ32R/CQn32R DQ30R DQ32R DQ31R DQ31R DQ31R DQ33R DQ33R DQ33R DQ34R DQ34R DQ34R Page 11 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 6A VREF VREFB6AN0 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 Pin Name/Function IO NC IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL2 MSEL1 MSEL0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function RUP6A RDN6A PLL_R1_FB_CLKOUT0p PLL_R1_CLKOUT0n Dedicated Tx/Rx Channel DIFFIO_RX_R51p Emulated LVDS Output Channel DIFFOUT_R101p DIFFIO_TX_R51p DIFFIO_TX_R51n DIFFIO_RX_R52p DIFFIO_RX_R52n DIFFIO_TX_R52p DIFFIO_TX_R52n DIFFIO_RX_R53p DIFFIO_RX_R53n DIFFIO_TX_R53p DIFFIO_TX_R53n DIFFIO_RX_R54p DIFFIO_RX_R54n DIFFIO_TX_R54p DIFFIO_TX_R54n DIFFIO_TX_R55p DIFFIO_TX_R55n DIFFIO_RX_R56p DIFFOUT_R102p DIFFOUT_R102n DIFFOUT_R103p DIFFOUT_R103n DIFFOUT_R104p DIFFOUT_R104n DIFFOUT_R105p DIFFOUT_R105n DIFFOUT_R106p DIFFOUT_R106n DIFFOUT_R107p DIFFOUT_R107n DIFFOUT_R108p DIFFOUT_R108n DIFFOUT_R110p DIFFOUT_R110n DIFFOUT_R111p DIFFIO_TX_R56p DIFFIO_TX_R56n DIFFOUT_R112p DIFFOUT_R112n MSEL2 MSEL1 MSEL0 RDN7A RUP7A DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n DIFFIO_RX_T3p DIFFIO_RX_T4n DIFFIO_RX_T4p DIFFIO_RX_T5n DIFFIO_RX_T5p DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n Pin List DIFFOUT_T1n DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p DIFFOUT_T8n DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n F1932 G6 G5 M10 N10 H9 J9 L10 M9 G10 H10 R14 P13 F9 G8 T15 U15 H11 J11 F6 F5 K11 L11 F10 E9 A9 B10 C10 A11 A12 C12 B11 A13 B13 B14 C13 C14 D14 E11 F11 D10 D11 D12 F12 E14 F14 F13 E13 G14 G15 L14 K13 J12 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQS31R DQS for X8/X9 for F1932 DQS33R/CQ33R DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 DQ34R DQ32R DQ32R DQS32R DQSn32R DQ32R DQ32R DQ33R DQ33R DQ33R DQ33R DQS33R DQSn33R DQ34R DQ34R DQ34R DQ34R DQ33R DQ33R DQ33R/CQn33R DQ33R DQ33R DQ33R DQ34R DQ34R DQ34R DQ34R DQS34R/CQ34R DQSn34R/DQ34R DQ34R DQ34R DQ34R DQ34R DQ34R DQ34R DQS34R/CQ34R DQSn34R/DQ34R DQ34R DQ34R DQ34R DQ34R DQ34R DQ34R DQ34R/CQn34R DQ34R DQ34R DQ34R DQ34R DQ34R DQ1T DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQSn3T DQS3T DQ3T DQ3T DQSn4T DQS4T DQ4T DQ4T DQ4T DQ4T DQ5T DQ5T DQSn5T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T Page 12 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T7p DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFIO_RX_T9n DIFFIO_RX_T9p DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T11n DIFFIO_RX_T11p DIFFIO_RX_T12n DIFFIO_RX_T12p DIFFIO_RX_T13n DIFFIO_RX_T13p DIFFIO_RX_T14n DIFFIO_RX_T14p DIFFIO_RX_T15n DIFFIO_RX_T15p DIFFIO_RX_T16n DIFFIO_RX_T16p DIFFIO_RX_T17n DIFFIO_RX_T17p DIFFIO_RX_T18n DIFFIO_RX_T18p DIFFIO_RX_T19n DIFFIO_RX_T19p DIFFIO_RX_T20n Pin List Emulated LVDS Output Channel DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T21n DIFFOUT_T21p DIFFOUT_T22n DIFFOUT_T22p DIFFOUT_T23n DIFFOUT_T23p DIFFOUT_T24n DIFFOUT_T24p DIFFOUT_T25n DIFFOUT_T25p DIFFOUT_T26n DIFFOUT_T26p DIFFOUT_T27n DIFFOUT_T27p DIFFOUT_T28n DIFFOUT_T28p DIFFOUT_T29n DIFFOUT_T29p DIFFOUT_T30n DIFFOUT_T30p DIFFOUT_T31n DIFFOUT_T31p DIFFOUT_T32n DIFFOUT_T32p DIFFOUT_T33n DIFFOUT_T33p DIFFOUT_T34n DIFFOUT_T34p DIFFOUT_T35n DIFFOUT_T35p DIFFOUT_T36n DIFFOUT_T36p DIFFOUT_T37n DIFFOUT_T37p DIFFOUT_T38n DIFFOUT_T38p DIFFOUT_T39n DIFFOUT_T39p DIFFOUT_T40n F1932 J13 H13 G12 J15 K15 H14 J14 L16 M16 N16 N15 M14 N14 R15 P14 P16 R16 N17 P17 R17 T17 A15 A14 A16 B16 A17 B17 A18 A19 B19 A20 C18 C19 F16 F15 C15 D15 D16 E16 D17 E17 D18 C17 D19 E19 H17 H16 J16 K16 F17 G17 G18 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQS5T DQ5T DQ5T DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQ7T DQ7T DQSn7T DQS7T DQ7T DQ7T DQSn8T DQS8T DQ8T DQ8T DQ8T DQ8T DQ9T DQ9T DQSn9T DQS9T DQ9T DQ9T DQSn10T DQS10T DQ10T DQ10T DQ10T DQ10T DQ11T DQ11T DQSn11T DQS11T DQ11T DQ11T DQSn12T DQS12T DQ12T DQ12T DQ12T DQ12T DQ13T DQ13T DQSn13T DQS13T DQ13T DQ13T DQSn14T DQS for X8/X9 for F1932 DQ3T/CQn3T DQ3T DQ3T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQ4T DQ4T DQ4T DQ4T/CQn4T DQ4T DQ4T DQSn4T/DQ4T DQS4T/CQ4T DQ4T DQ4T DQ4T DQ4T DQ9T DQ9T DQ9T DQ9T/CQn9T DQ9T DQ9T DQSn9T/DQ9T DQS9T/CQ9T DQ9T DQ9T DQ9T DQ9T DQ10T DQ10T DQ10T DQ10T/CQn10T DQ10T DQ10T DQSn10T/DQ10T DQS10T/CQ10T DQ10T DQ10T DQ10T DQ10T DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQSn11T/DQ11T DQS for X16/ X18 for F1932 DQ2T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T/CQn9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQSn9T/DQ9T DQS9T/CQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQS for X32/ X36 for F1932 DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T/CQn9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQSn9T/DQ9T DQS9T/CQ9T DQ9T DQ9T DQ9T Page 13 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 8C 8C 8C PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T20p DIFFIO_RX_T21n DIFFIO_RX_T21p DIFFIO_RX_T22n DIFFIO_RX_T22p DIFFIO_RX_T23n DIFFIO_RX_T23p DIFFIO_RX_T24n DIFFIO_RX_T24p DIFFIO_RX_T25n DIFFIO_RX_T25p DIFFIO_RX_T26n DIFFIO_RX_T26p DIFFIO_RX_T27n DIFFIO_RX_T27p DIFFIO_RX_T28n DIFFIO_RX_T28p DIFFIO_RX_T29n DIFFIO_RX_T29p PLL_T2_CLKOUT4 PLL_T2_CLKOUT3 DIFFIO_RX_T30n DIFFIO_RX_T30p PLL_T2_CLKOUT0n PLL_T2_CLKOUT0p PLL_T2_FBn/CLKOUT2 PLL_T2_FBp/CLKOUT1 CLK13n CLK13p CLK12n CLK12p CLK14p CLK14n CLK15p DIFFIO_RX_T31n DIFFIO_RX_T31p DIFFIO_RX_T32n DIFFIO_RX_T32p DIFFIO_RX_T33p DIFFIO_RX_T33n Pin List Emulated LVDS Output Channel DIFFOUT_T40p DIFFOUT_T41n DIFFOUT_T41p DIFFOUT_T42n DIFFOUT_T42p DIFFOUT_T43n DIFFOUT_T43p DIFFOUT_T44n DIFFOUT_T44p DIFFOUT_T45n DIFFOUT_T45p DIFFOUT_T46n DIFFOUT_T46p DIFFOUT_T47n DIFFOUT_T47p DIFFOUT_T48n DIFFOUT_T48p DIFFOUT_T49n DIFFOUT_T49p DIFFOUT_T50n DIFFOUT_T50p DIFFOUT_T51n DIFFOUT_T51p DIFFOUT_T52n DIFFOUT_T52p DIFFOUT_T53n DIFFOUT_T53p DIFFOUT_T54n DIFFOUT_T54p DIFFOUT_T55n DIFFOUT_T55p DIFFOUT_T56n DIFFOUT_T56p DIFFOUT_T57n DIFFOUT_T57p DIFFOUT_T58n DIFFOUT_T58p DIFFOUT_T59n DIFFOUT_T59p DIFFOUT_T60n DIFFOUT_T60p DIFFOUT_T61n DIFFOUT_T61p DIFFOUT_T62n DIFFOUT_T62p DIFFOUT_T63n DIFFOUT_T63p DIFFOUT_T64n DIFFOUT_T64p DIFFOUT_T65p DIFFOUT_T65n DIFFOUT_T66p F1932 H19 J19 J18 F19 G19 K18 M17 K17 L17 K19 N18 M19 N19 R19 T19 P19 R18 B22 A21 B20 C20 D22 C22 D20 D21 F22 E22 E20 F21 G21 F20 G20 H20 H22 J22 R21 T21 P20 N20 P22 R22 N22 N21 K20 L20 M21 M22 J20 J21 R23 P23 N24 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS14T DQ14T DQ14T DQ14T DQ14T DQ15T DQ15T DQSn15T DQS15T DQ15T DQ15T DQSn16T DQS16T DQ16T DQ16T DQ16T DQ16T DQ17T DQ17T DQSn17T DQS17T DQ17T DQ17T DQSn18T DQS18T DQ18T DQ18T DQ18T DQ18T DQ19T DQ19T DQSn19T DQS19T DQ19T DQ19T DQS for X8/X9 for F1932 DQS11T/CQ11T DQ11T DQ11T DQ11T DQ11T DQ12T DQ12T DQ12T DQ12T/CQn12T DQ12T DQ12T DQSn12T/DQ12T DQS12T/CQ12T DQ12T DQ12T DQ12T DQ12T DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQ17T DQSn17T/DQ17T DQS17T/CQ17T DQ17T DQ17T DQ17T DQ17T DQS for X16/ X18 for F1932 DQ10T/CQn10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQSn10T/DQ10T DQS10T/CQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQS for X32/ X36 for F1932 DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T Page 14 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T34p DIFFIO_RX_T34n DIFFIO_RX_T35p DIFFIO_RX_T35n PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 DIFFIO_RX_T36p DIFFIO_RX_T36n DIFFIO_RX_T37p DIFFIO_RX_T37n DIFFIO_RX_T38p DIFFIO_RX_T38n DIFFIO_RX_T39p DIFFIO_RX_T39n RUP8C RDN8C DIFFIO_RX_T40p DIFFIO_RX_T40n DIFFIO_RX_T41p DIFFIO_RX_T41n DIFFIO_RX_T42p DIFFIO_RX_T42n DIFFIO_RX_T43p DIFFIO_RX_T43n DIFFIO_RX_T44p DIFFIO_RX_T44n DIFFIO_RX_T45p DIFFIO_RX_T45n DIFFIO_RX_T46p DIFFIO_RX_T46n Pin List Emulated LVDS Output Channel DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T67n DIFFOUT_T68p DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T69n DIFFOUT_T70p DIFFOUT_T70n DIFFOUT_T71p DIFFOUT_T71n DIFFOUT_T72p DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T73n DIFFOUT_T74p DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T75n DIFFOUT_T76p DIFFOUT_T76n DIFFOUT_T77p DIFFOUT_T77n DIFFOUT_T78p DIFFOUT_T78n DIFFOUT_T79p DIFFOUT_T79n DIFFOUT_T80p DIFFOUT_T80n DIFFOUT_T81p DIFFOUT_T81n DIFFOUT_T82p DIFFOUT_T82n DIFFOUT_T83p DIFFOUT_T83n DIFFOUT_T84p DIFFOUT_T84n DIFFOUT_T85p DIFFOUT_T85n DIFFOUT_T86p DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T87n DIFFOUT_T88p DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T89n DIFFOUT_T90p DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T91n DIFFOUT_T92p F1932 N23 J24 H23 T23 R24 G25 G24 M25 L25 K25 J25 G23 F23 E25 D25 F24 F25 D24 D23 A22 A23 C23 B23 A24 C24 B25 A26 C25 A25 P25 N25 R25 T25 P26 N26 K26 N27 M28 M27 L26 M26 H26 G26 J26 J27 H28 G28 F29 G29 J29 H29 J28 Dynamic OCT Support No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 DQ20T DQ20T DQS20T DQSn20T DQ20T DQ20T DQ21T DQ21T DQ21T DQ21T DQS21T DQSn21T DQ22T DQ22T DQS22T DQSn22T DQ22T DQ22T DQ23T DQ23T DQ23T DQ23T DQS23T DQSn23T DQ24T DQ24T DQS24T DQSn24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ25T DQS25T DQSn25T DQ26T DQ26T DQS26T DQSn26T DQ26T DQ22T DQ22T DQ22T DQ22T DQS22T/CQ22T DQSn22T/DQ22T DQ22T DQ22T DQ22T/CQn22T DQ22T DQ22T DQ22T DQ27T DQ27T DQ27T DQ27T DQS27T/CQ27T DQSn27T/DQ27T DQ27T DQ27T DQ27T/CQn27T DQ27T DQ27T DQ27T DQ28T DQ28T DQ28T DQ28T DQS28T/CQ28T DQSn28T/DQ28T DQ28T DQ28T DQ28T/CQn28T DQ28T DQ28T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQS29T/CQ29T DQSn29T/DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T/CQn29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQS30T/CQ30T DQSn30T/DQ30T DQ30T Page 15 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T47p DIFFIO_RX_T47n DIFFIO_RX_T48p DIFFIO_RX_T48n DIFFIO_RX_T49p DIFFIO_RX_T49n DIFFIO_RX_T50p DIFFIO_RX_T50n DIFFIO_RX_T51p DIFFIO_RX_T51n DIFFIO_RX_T52p DIFFIO_RX_T52n DIFFIO_RX_T53p DIFFIO_RX_T53n DIFFIO_RX_T54p DIFFIO_RX_T54n DIFFIO_RX_T55p DIFFIO_RX_T55n DIFFIO_RX_T56p DIFFIO_RX_T56n DIFFIO_RX_T57p DIFFIO_RX_T57n DIFFIO_RX_T58p DIFFIO_RX_T58n DIFFIO_RX_T59p DIFFIO_RX_T59n Pin List Emulated LVDS Output Channel DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T93n DIFFOUT_T94p DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T95n DIFFOUT_T96p DIFFOUT_T96n DIFFOUT_T97p DIFFOUT_T97n DIFFOUT_T98p DIFFOUT_T98n DIFFOUT_T99p DIFFOUT_T99n DIFFOUT_T100p DIFFOUT_T100n DIFFOUT_T101p DIFFOUT_T101n DIFFOUT_T102p DIFFOUT_T102n DIFFOUT_T103p DIFFOUT_T103n DIFFOUT_T104p DIFFOUT_T104n DIFFOUT_T105p DIFFOUT_T105n DIFFOUT_T106p DIFFOUT_T106n DIFFOUT_T107p DIFFOUT_T107n DIFFOUT_T108p DIFFOUT_T108n DIFFOUT_T109p DIFFOUT_T109n DIFFOUT_T110p DIFFOUT_T110n DIFFOUT_T111p DIFFOUT_T111n DIFFOUT_T112p DIFFOUT_T112n DIFFOUT_T113p DIFFOUT_T113n DIFFOUT_T114p DIFFOUT_T114n DIFFOUT_T115p DIFFOUT_T115n DIFFOUT_T116p DIFFOUT_T116n DIFFOUT_T117p DIFFOUT_T117n DIFFOUT_T118p F1932 K28 D27 D26 F26 E26 F28 F27 D28 E28 D29 C29 E29 D30 C26 B26 A27 A28 C28 B28 A29 B29 A31 A30 C30 B31 T27 R27 N28 P28 R28 P29 N29 N30 N31 M30 L29 M29 J30 H31 K29 K30 G31 G30 J32 H32 L32 K31 J33 K32 F31 E31 D31 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1932 DQ26T DQ27T DQ27T DQ27T DQ27T DQS27T DQSn27T DQ28T DQ28T DQS28T DQSn28T DQ28T DQ28T DQ29T DQ29T DQ29T DQ29T DQS29T DQSn29T DQ30T DQ30T DQS30T DQSn30T DQ30T DQ30T DQ31T DQ31T DQ31T DQ31T DQS31T DQSn31T DQ32T DQ32T DQS32T DQSn32T DQ32T DQ32T DQ33T DQ33T DQ33T DQ33T DQS33T DQSn33T DQ34T DQ34T DQS34T DQSn34T DQ34T DQ34T DQ35T DQ35T DQ35T DQS for X8/X9 for F1932 DQ28T DQ29T DQ29T DQ29T DQ29T DQS29T/CQ29T DQSn29T/DQ29T DQ29T DQ29T DQ29T/CQn29T DQ29T DQ29T DQ29T DQ30T DQ30T DQ30T DQ30T DQS30T/CQ30T DQSn30T/DQ30T DQ30T DQ30T DQ30T/CQn30T DQ30T DQ30T DQ30T DQ35T DQ35T DQ35T DQ35T DQS35T/CQ35T DQSn35T/DQ35T DQ35T DQ35T DQ35T/CQn35T DQ35T DQ35T DQ35T DQ36T DQ36T DQ36T DQ36T DQS36T/CQ36T DQSn36T/DQ36T DQ36T DQ36T DQ36T/CQn36T DQ36T DQ36T DQ36T DQ37T DQ37T DQ37T DQS for X16/ X18 for F1932 DQ29T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQS30T/CQ30T DQSn30T/DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T/CQn30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQS37T/CQ37T DQSn37T/DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T/CQn37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ38T DQ38T DQ38T DQS for X32/ X36 for F1932 DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T/CQn30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQS38T/CQ38T DQSn38T/DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T Page 16 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL3 QL2 QL2 QL2 QL2 QL2 QL2 QL2 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_TX_L15p GXB_TX_L15n GXB_RX_L15p GXB_RX_L15n GXB_TX_L14p GXB_TX_L14n GXB_RX_L14p GXB_RX_L14n GXB_CMUTX_L7p GXB_CMUTX_L7n REFCLK_L7p,GXB_CMURX_L7p REFCLK_L7n,GXB_CMURX_L7n GXB_CMUTX_L6p GXB_CMUTX_L6n REFCLK_L6p,GXB_CMURX_L6p REFCLK_L6n,GXB_CMURX_L6n GXB_TX_L13p GXB_TX_L13n GXB_RX_L13p GXB_RX_L13n GXB_TX_L12p GXB_TX_L12n GXB_RX_L12p GXB_RX_L12n GXB_TX_L11p GXB_TX_L11n GXB_RX_L11p GXB_RX_L11n GXB_TX_L10p GXB_TX_L10n GXB_RX_L10p Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T60p DIFFIO_RX_T60n DIFFIO_RX_T61p DIFFIO_RX_T61n DIFFIO_RX_T62p DIFFIO_RX_T62n DIFFIO_RX_T63p DIFFIO_RX_T63n RUP8A RDN8A DIFFIO_RX_T64p DIFFIO_RX_T64n Pin List Emulated LVDS Output Channel DIFFOUT_T118n DIFFOUT_T119p DIFFOUT_T119n DIFFOUT_T120p DIFFOUT_T120n DIFFOUT_T121p DIFFOUT_T121n DIFFOUT_T122p DIFFOUT_T122n DIFFOUT_T123p DIFFOUT_T123n DIFFOUT_T124p DIFFOUT_T124n DIFFOUT_T125p DIFFOUT_T125n DIFFOUT_T126p DIFFOUT_T126n DIFFOUT_T127p DIFFOUT_T127n DIFFOUT_T128p DIFFOUT_T128n F1932 C31 F32 E32 E35 G33 F34 E34 F35 F33 D33 C33 D32 C32 B32 A32 A34 B34 C34 B35 C35 D35 D37 C37 B38 A38 D39 C39 B40 A40 B42 A42 D43 D44 E41 E42 F43 F44 G41 G42 H43 H44 J41 J42 K43 K44 L41 L42 M43 M44 N41 N42 P43 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQ35T DQS35T DQSn35T DQ36T DQ36T DQS36T DQSn36T DQ36T DQ36T DQ37T DQ37T DQ37T DQ37T DQS37T DQSn37T DQ38T DQ38T DQS38T DQSn38T DQ38T DQ38T DQS for X8/X9 for F1932 DQ37T DQS37T/CQ37T DQSn37T/DQ37T DQ37T DQ37T DQ37T/CQn37T DQ37T DQ37T DQ37T DQ38T DQ38T DQ38T DQ38T DQS38T/CQ38T DQSn38T/DQ38T DQ38T DQ38T DQ38T/CQn38T DQ38T DQ38T DQ38T DQS for X16/ X18 for F1932 DQ38T DQ38T DQ38T DQ38T DQ38T DQS38T/CQ38T DQSn38T/DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T/CQn38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQS for X32/ X36 for F1932 DQ38T DQ38T/CQn38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T Page 17 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GXB_RX_L10n GXB_CMUTX_L5p GXB_CMUTX_L5n REFCLK_L5p,GXB_CMURX_L5p REFCLK_L5n,GXB_CMURX_L5n GXB_CMUTX_L4p GXB_CMUTX_L4n REFCLK_L4p,GXB_CMURX_L4p REFCLK_L4n,GXB_CMURX_L4n GXB_TX_L9p GXB_TX_L9n GXB_RX_L9p GXB_RX_L9n GXB_TX_L8p GXB_TX_L8n GXB_RX_L8p GXB_RX_L8n GXB_TX_L7p GXB_TX_L7n GXB_RX_L7p GXB_RX_L7n GXB_TX_L6p GXB_TX_L6n GXB_RX_L6p GXB_RX_L6n GXB_CMUTX_L3p GXB_CMUTX_L3n REFCLK_L3p,GXB_CMURX_L3p REFCLK_L3n,GXB_CMURX_L3n GXB_CMUTX_L2p GXB_CMUTX_L2n REFCLK_L2p,GXB_CMURX_L2p REFCLK_L2n,GXB_CMURX_L2n GXB_TX_L5p GXB_TX_L5n GXB_RX_L5p GXB_RX_L5n GXB_TX_L4p GXB_TX_L4n GXB_RX_L4p GXB_RX_L4n GXB_TX_L3p GXB_TX_L3n GXB_RX_L3p GXB_RX_L3n GXB_TX_L2p GXB_TX_L2n GXB_RX_L2p GXB_RX_L2n GXB_CMUTX_L1p GXB_CMUTX_L1n REFCLK_L1p,GXB_CMURX_L1p Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 P44 R41 R42 T43 T44 U41 U42 V43 V44 W41 W42 Y43 Y44 AA41 AA42 AB43 AB44 AC41 AC42 AD43 AD44 AE41 AE42 AF43 AF44 AG41 AG42 AH43 AH44 AJ41 AJ42 AK43 AK44 AL41 AL42 AM43 AM44 AN41 AN42 AP43 AP44 AR41 AR42 AT43 AT44 AU41 AU42 AV43 AV44 AW41 AW42 AY43 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 18 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function REFCLK_L1n,GXB_CMURX_L1n GXB_CMUTX_L0p GXB_CMUTX_L0n REFCLK_L0p,GXB_CMURX_L0p REFCLK_L0n,GXB_CMURX_L0n GXB_TX_L1p GXB_TX_L1n GXB_RX_L1p GXB_RX_L1n GXB_TX_L0p GXB_TX_L0n GXB_RX_L0p GXB_RX_L0n GXB_RX_R0n GXB_RX_R0p GXB_TX_R0n GXB_TX_R0p GXB_RX_R1n GXB_RX_R1p GXB_TX_R1n GXB_TX_R1p REFCLK_R0n,GXB_CMURX_R0n REFCLK_R0p,GXB_CMURX_R0p GXB_CMUTX_R0n GXB_CMUTX_R0p REFCLK_R1n,GXB_CMURX_R1n REFCLK_R1p,GXB_CMURX_R1p GXB_CMUTX_R1n GXB_CMUTX_R1p GXB_RX_R2n GXB_RX_R2p GXB_TX_R2n GXB_TX_R2p GXB_RX_R3n GXB_RX_R3p GXB_TX_R3n GXB_TX_R3p GXB_RX_R4n GXB_RX_R4p GXB_TX_R4n GXB_TX_R4p GXB_RX_R5n GXB_RX_R5p GXB_TX_R5n GXB_TX_R5p REFCLK_R2n,GXB_CMURX_R2n REFCLK_R2p,GXB_CMURX_R2p GXB_CMUTX_R2n GXB_CMUTX_R2p REFCLK_R3n,GXB_CMURX_R3n REFCLK_R3p,GXB_CMURX_R3p GXB_CMUTX_R3n Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AY44 BB43 BB44 BC41 BD41 BA40 BB40 BC39 BD39 BA38 BB38 BC37 BD37 BD8 BC8 BB7 BA7 BD6 BC6 BB5 BA5 BB1 BB2 BD4 BC4 AY1 AY2 AW3 AW4 AV1 AV2 AU3 AU4 AT1 AT2 AR3 AR4 AP1 AP2 AN3 AN4 AM1 AM2 AL3 AL4 AK1 AK2 AJ3 AJ4 AH1 AH2 AG3 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 19 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 QR3 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GXB_CMUTX_R3p GXB_RX_R6n GXB_RX_R6p GXB_TX_R6n GXB_TX_R6p GXB_RX_R7n GXB_RX_R7p GXB_TX_R7n GXB_TX_R7p GXB_RX_R8n GXB_RX_R8p GXB_TX_R8n GXB_TX_R8p GXB_RX_R9n GXB_RX_R9p GXB_TX_R9n GXB_TX_R9p REFCLK_R4n,GXB_CMURX_R4n REFCLK_R4p,GXB_CMURX_R4p GXB_CMUTX_R4n GXB_CMUTX_R4p REFCLK_R5n,GXB_CMURX_R5n REFCLK_R5p,GXB_CMURX_R5p GXB_CMUTX_R5n GXB_CMUTX_R5p GXB_RX_R10n GXB_RX_R10p GXB_TX_R10n GXB_TX_R10p GXB_RX_R11n GXB_RX_R11p GXB_TX_R11n GXB_TX_R11p GXB_RX_R12n GXB_RX_R12p GXB_TX_R12n GXB_TX_R12p GXB_RX_R13n GXB_RX_R13p GXB_TX_R13n GXB_TX_R13p REFCLK_R6n,GXB_CMURX_R6n REFCLK_R6p,GXB_CMURX_R6p GXB_CMUTX_R6n GXB_CMUTX_R6p REFCLK_R7n,GXB_CMURX_R7n REFCLK_R7p,GXB_CMURX_R7p GXB_CMUTX_R7n GXB_CMUTX_R7p GXB_RX_R14n GXB_RX_R14p GXB_TX_R14n Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AG4 AF1 AF2 AE3 AE4 AD1 AD2 AC3 AC4 AB1 AB2 AA3 AA4 Y1 Y2 W3 W4 V1 V2 U3 U4 T1 T2 R3 R4 P1 P2 N3 N4 M1 M2 L3 L4 K1 K2 J3 J4 H1 H2 G3 G4 F1 F2 E3 E4 D1 D2 A3 B3 A5 B5 C6 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 20 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number QR3 QR3 QR3 QR3 QR3 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GXB_TX_R14p GXB_RX_R15n GXB_RX_R15p GXB_TX_R15n GXB_TX_R15p GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 D6 A7 B7 C8 D8 W37 Y37 AY10 V8 AB23 BC12 BC15 BC18 BC21 BC24 BC27 BC30 BC33 AY12 AY15 AY18 AY21 AY24 AY27 AY30 AY33 AV9 AV36 AU7 AU12 AU15 AU18 AU21 AU24 AU30 AU33 AU38 AT27 AR9 AR36 AP7 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33 AP38 AM9 AM36 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 21 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AL7 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AL33 AL38 AJ15 AH7 AH13 AH17 AH19 AH21 AH23 AH25 AH27 AH29 AH32 AH38 AG16 AG18 AG20 AG22 AG24 AG26 AG28 AF17 AF19 AF21 AF23 AF25 AF27 AF31 AE7 AE13 AE15 AE18 AE20 AE22 AE24 AE26 AE28 AE32 AE38 AD17 AD19 AD21 AD23 AD25 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 22 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AD27 AC18 AC20 AC24 AC26 AC28 AC30 AB7 AB13 AB15 AB17 AB19 AB21 AB25 AB27 AB32 AB35 AB38 AA18 AA20 AA22 AA24 AA26 AA28 Y17 Y19 Y21 Y23 Y25 Y27 Y30 W7 W13 W15 W18 W20 W22 W24 W26 W28 W32 W39 V17 V19 V21 V23 V25 V27 V29 U16 U18 U20 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 23 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 U22 U24 U26 U28 T7 T13 T29 T32 T38 P12 P15 P18 P21 P24 P27 P30 P33 N7 N9 N36 N38 L12 L15 L18 L21 L24 L27 L30 L33 K7 K9 K36 K38 H12 H15 H18 H21 H24 H27 H30 H33 G7 G9 G36 G38 E12 E15 E18 E21 E24 E27 E30 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 24 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 E33 B12 B15 B18 B21 B24 B27 B30 B33 A43 BD36 BD38 BD40 BD42 BC36 BC38 BC40 BC42 BC43 BB36 BB37 BB39 BB41 BB42 BA37 BA39 BA41 BA42 BA43 BA44 AY41 AY42 AW43 AW44 AV41 AV42 AU43 AU44 AT41 AT42 AR43 AR44 AP41 AP42 AN43 AN44 AM41 AM42 AL43 AL44 AK41 AK42 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 25 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AJ35 AJ43 AJ44 AH41 AH42 AG34 AG36 AG43 AG44 AF41 AF42 AE35 AE43 AE44 AD41 AD42 AC34 AC36 AC43 AC44 AB41 AB42 AA35 AA43 AA44 Y41 Y42 W34 W36 W43 W44 V41 V42 U35 U43 U44 T41 T42 R34 R36 R43 R44 P41 P42 N43 N44 M41 M42 L43 L44 K41 K42 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 26 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 J43 J44 H41 H42 G43 G44 F41 F42 E43 E44 D36 D38 D40 D41 D42 C36 C38 C40 C41 C42 C43 C44 B37 B39 B41 B43 A37 A39 A41 BC44 AA40 AC40 AG40 AL40 AN40 AT40 AU40 AV40 AA36 AA37 AB36 AB37 AC37 AE36 AE33 AF37 AF36 AF35 AF34 AF33 AG33 AH37 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 27 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AJ37 AJ36 AJ33 AK36 AK35 AK34 AK33 W40 AD40 A8 BD3 BD5 BD7 BD9 BC1 BC2 BC3 BC5 BC7 BC9 BB3 BB4 BB6 BB8 BB9 BA1 BA2 BA3 BA4 BA6 BA8 AY3 AY4 AW1 AW2 AV3 AV4 AU1 AU2 AT3 AT4 AR1 AR2 AP3 AP4 AN1 AN2 AM3 AM4 AL1 AL2 AK3 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 28 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AK4 AJ1 AJ2 AJ10 AH3 AH4 AG1 AG2 AG9 AG11 AF3 AF4 AE1 AE2 AE10 AD3 AD4 AC1 AC2 AC9 AC11 AB3 AB4 AA1 AA2 AA10 Y3 Y4 W1 W2 W9 W11 V3 V4 U1 U2 U10 T3 T4 R1 R2 R9 R11 P3 P4 N1 N2 M3 M4 L1 L2 K3 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 29 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 K4 J1 J2 H3 H4 G1 G2 F3 F4 E1 E2 D3 D4 D5 D7 D9 C1 C2 C3 C4 C5 C7 C9 B2 B4 B6 B8 A2 A4 A6 E8 E7 K5 AA5 AC5 AG5 AL5 AN5 AT5 AU5 AV5 AK12 AK11 AK10 AK9 AK8 AJ12 AJ9 AJ8 AH12 AH8 AG8 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 30 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AF12 AF11 AF10 AF9 AE9 AE8 AC8 AB11 AB10 AB9 AB8 AA9 AA8 Y8 U9 W5 AD5 AB22 AH18 AH28 AG17 AG21 AG23 AG25 AG27 AF18 AF20 AF22 AF24 AF28 AE17 AE21 AE23 AE25 AE27 AD18 AD20 AD22 AD24 AD28 AC17 AC21 AC23 AC25 AC27 AB18 AB20 AB24 AB28 AA17 AA21 AA23 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 31 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AA25 AA27 Y18 Y20 Y22 Y24 Y28 W17 W21 W23 W25 W27 V16 V18 V20 V22 V24 V28 U17 U27 U29 T28 AJ23 AH20 AH22 AH24 AH26 AG19 AF26 AE19 AD26 AC19 AB26 AA19 Y26 W19 V26 U19 U21 U23 U25 T22 AH34 AJ34 AE34 Y34 U34 T34 AJ11 AH11 AE11 Y11 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 32 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function VCC VCC VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT DNU VCCPGM VCCPGM TEMPDIODEn TEMPDIODEp VCC_CLKIN3C VCC_CLKIN4C VCC_CLKIN7C VCC_CLKIN8C VCCBAT VCCA_PLL_B1 VCCA_PLL_B2 VCCA_PLL_L1 VCCA_PLL_L2 VCCA_PLL_L3 VCCA_PLL_L4 VCCA_PLL_R1 VCCA_PLL_R2 VCCA_PLL_R3 VCCA_PLL_R4 VCCA_PLL_T1 VCCA_PLL_T2 VCCD_PLL_B1 VCCD_PLL_B2 VCCD_PLL_L1 VCCD_PLL_L2 VCCD_PLL_L3 VCCD_PLL_L4 VCCD_PLL_R1 VCCD_PLL_R2 VCCD_PLL_R3 VCCD_PLL_R4 VCCD_PLL_T1 VCCD_PLL_T2 VCCIO1A VCCIO1A VCCIO1A VCCIO1A VCCIO1A VCCIO1C VCCIO1C VCCIO1C VCCIO1C VCCIO2A Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 U11 T11 AC31 AC32 AT22 AC13 AC14 J23 AC22 AM32 AM13 G11 B9 AR24 AR21 K21 K24 L13 AR23 AR22 M32 AA32 AD32 AP32 M13 AA13 AE12 AP13 K23 K22 AP23 AP22 N32 AB31 AD31 AN32 N13 AB14 AD13 AN13 L23 L22 U31 M34 L37 H35 H39 V33 V38 T37 N37 AV39 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 33 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function VCCIO2A VCCIO2A VCCIO2A VCCIO2A VCCIO2B VCCIO2B VCCIO2C VCCIO2C VCCIO2C VCCIO2C VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3C VCCIO3C VCCIO3C VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4C VCCIO4C VCCIO4C VCCIO5A VCCIO5A VCCIO5A VCCIO5A VCCIO5A VCCIO5B VCCIO5B VCCIO5C VCCIO5C VCCIO5C VCCIO5C VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 AT35 AR38 AN36 AM34 AL37 AH33 AJ38 AG37 AD37 AB34 BB34 AW32 AV30 AP29 AL31 BB29 BB27 AW27 AT28 AN27 BB24 AU25 AK25 AW13 BB11 AT15 AN16 AL16 BB16 BB19 AV17 AR18 AK19 AV21 BA21 AN21 AU6 AP8 AN10 AK13 AH15 AM8 AF14 AF8 AD8 AC7 Y7 T12 T14 N11 L8 J10 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 34 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function VCCIO6C VCCIO6C VCCIO6C VCCIO6C VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7B VCCIO7B VCCIO7B VCCIO7B VCCIO7B VCCIO7C VCCIO7C VCCIO7C VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8B VCCIO8B VCCIO8B VCCIO8B VCCIO8B VCCIO8C VCCIO8C VCCIO8C VCCPD1A VCCPD1C VCCPD2A VCCPD2B VCCPD2C VCCPD3A VCCPD3B VCCPD3C VCCPD4A VCCPD4B VCCPD4C VCCPD5A VCCPD5B VCCPD5C VCCPD6A VCCPD6C VCCPD7A VCCPD7B VCCPD7C VCCPD8A VCCPD8B VCCPD8C Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 Y13 W8 T8 M7 C11 K14 G13 E10 D13 C16 M18 J17 G16 F18 C21 R20 G22 G32 M31 J31 D34 A33 G27 R26 K27 F30 C27 E23 M24 H25 W29 AA29 AG29 AE29 AC29 AJ29 AJ27 AJ25 AJ17 AJ19 AJ21 AH16 AF16 AD16 Y16 AB16 T16 T18 T20 R29 T26 T24 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 35 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number 1A 1C 2A 2B 2C 3A 3B 3C 4A 4B 4C 5A 5B 5C 6A 6C 7A 7B 7C 8A 8B 8C PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2BN0 VREFB2CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB5AN0 VREFB5BN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 Pin Name/Function VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2BN0 VREFB2CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB5AN0 VREFB5BN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCAUX VCCAUX VCCAUX VCCAUX VCCA_L VCCA_L VCCA_L VCCA_L VCCA_R VCCA_R Optional Function(s) VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2BN0 VREFB2CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB5AN0 VREFB5BN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 R32 Y33 AG30 AK37 AE37 AP31 AP26 AN25 AP14 AR17 AN22 AM10 AG12 AF7 K10 R7 M15 L19 M20 L31 L28 M23 A35 BA35 AW11 A10 AW39 AW40 AW6 AW5 AJ26 AJ28 AF29 AC16 AB29 AA16 Y29 W16 E39 E40 E6 E5 K33 AR33 AR12 K12 AK40 V40 AJ40 U40 V5 AK5 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 36 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. VREF Pin Name/Function VCCA_R VCCA_R VCCH_GXBL0 VCCH_GXBL1 VCCH_GXBL2 VCCH_GXBL3 VCCH_GXBR0 VCCH_GXBR1 VCCH_GXBR2 VCCH_GXBR3 VCCL_GXBL0 VCCL_GXBL0 VCCL_GXBL1 VCCL_GXBL1 VCCL_GXBL2 VCCL_GXBL2 VCCL_GXBL3 VCCL_GXBL3 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBR1 VCCL_GXBR1 VCCL_GXBR2 VCCL_GXBR2 VCCL_GXBR3 VCCL_GXBR3 VCCR_L VCCR_L VCCR_L VCCR_L VCCR_L VCCR_R VCCR_R VCCR_R VCCR_R VCCR_R VCCT_L VCCT_L VCCT_L VCCT_L VCCT_L VCCT_R VCCT_R VCCT_R VCCT_R VCCT_R VCCHIP_L VCCHIP_L VCCHIP_L VCCHIP_L VCCHIP_L VCCHIP_R Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1932 U5 AJ5 AH36 AD36 Y36 T36 AH9 AD9 Y9 T9 AG35 AH35 AC35 AD35 W35 Y35 R35 T35 AG10 AH10 AC10 AD10 W10 Y10 R10 T10 T40 AB40 AH40 AP40 AR40 T5 AB5 AH5 AP5 AR5 P40 Y40 AF40 AM40 AE40 P5 Y5 AF5 AM5 AE5 AA34 AB33 AC33 AD34 AD33 AA11 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Page 37 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Note (1) Bank Number VREF Pin Name/Function VCCHIP_R VCCHIP_R VCCHIP_R VCCHIP_R RREF_L0 RREF_L1 RREF_R0 RREF_R1 Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1932 AB12 AC12 AD12 AD11 BD43 B44 BD2 B1 Dynamic OCT Support No No No No No No No No DQS for X4 for F1932 DQS for X8/X9 for F1932 DQS for X16/ X18 for DQS for X32/ X36 F1932 for F1932 Notes: (1) If the p pin or n pin is not available, the particular differential pair is not supported. (2) Pins with * can be used as clock pins when the data rate for the transceiver blocks is below 6.5 Gbps. PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. Pin List Page 38 of 43 ® Pin Information for the Stratix IV GT EP4S100G4 Device Version 1.3 Notes (1), (2), (5) Pin Name Pin Type (1st and 2nd Function) Pin Description CLK[1,3,8,10]p CLK[1,3,8,10]n CLK[4:7,9, 11:15]p CLK[4:7,12:15]n PLL_[L4,R4]_CLKp PLL_[L4,R4]_CLKn PLL_[L1, L2, L4]_CLKOUT0n PLL_[R1, R2, R3, R4]_CLKOUT0n PLL_[L1, L2, L4]_FB_CLKOUT0p PLL_[R1, R2, R3, R4]_FB_CLKOUT0p PLL_[T1,T2,B1,B2]_FBp/CLKOUT1 PLL_[T1,T2,B1,B2]_FBn/CLKOUT2 PLL_[T1,T2,B1,B2]_CLKOUT[3,4] PLL_[T1,T2,B1,B2]_CLKOUT0p PLL_[T1,T2,B1,B2]_CLKOUT0n Clock, Input Clock, Input I/O, Clock I/O, Clock Clock, Input Clock, Input I/O, Clock nIO_PULLUP Input TEMPDIODEp TEMPDIODEn MSEL[0:2] nCE nCONFIG Input Input Input Input Input CONF_DONE Bidirectional (open-drain) nCEO nSTATUS Output Bidirectional (open-drain) PORSEL Input nCSO ASDO DCLK Output Output Input (PS, FPP) Output (AS) Input Input Input Output Input TCK TMS TDI TDO TRST CRC_ERROR I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock DEV_CLRn (Note 6) I/O, Output (open-drain) I/O, Input DEV_OE (Note 6) I/O, Input DATA0 (Note 6) I/O, Input DATA[1:7] (Note 6) I/O, Input PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. Clock and PLL Pins Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins. Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins. These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins. Dedicated clock input pins to PLL L4 and R4 respectively. Dedicated negative clock input pins for differential clock input to PLL L4 and R4 respectively. Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin. Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin. These pins can be used as I/O pins or two single-ended clock output pins. I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. Dedicated Configuration/JTAG Pins Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (DATA[0:7], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during configuration. A logic high turns off the weak pull-up, while a logic low turns them on. Pin used in conjunction with the temperature sensing diode (bias-high input) inside the FPGA. Pin used in conjunction with the temperature sensing diode (bias-low input) inside the FPGA. Configuration input pins that set the FPGA device configuration scheme. Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state, and tristate all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. This is a dedicated configuration done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin. Output that drives low when device configuration is complete. This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin. Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high selects a POR time of 12 ms and a logic low selects POR time of 100 ms. Dedicated output control signal from the FPGA to the serial configuration device in AS mode that enables the configuration device. Control signal from the FPGA to the serial configuration device in AS mode used to read out configuration data. Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS mode, DCLK is an output from the FPGA that provides timing for the configuration interface. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG output pin. Dedicated active low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. Optional/Dual-Purpose Configuration Pins Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. Optional pin that allows designers to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high (VCCPGM), all registers behave as programmed. Optional pin that allows designers to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high (VCCPGM), all I/O pins behave as defined in the design. Dual-purpose configuration data input pin. The DATA0 pin can be used for bit-wide configuration or as an I/O pin after configuration is complete. Dual-purpose configuration input data pins. The DATA[0:7] pins can be used for byte-wide configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration. Pin Definitions Page 39 of 43 ® Pin Information for the Stratix IV GT EP4S100G4 Device Version 1.3 Notes (1), (2), (5) Pin Name INIT_DONE Pin Type (1st and 2nd Function) Pin Description I/O, Output This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates (open-drain) when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. CLKUSR (Note 6) I/O, Input DIFFIO_RX[##]p, DIFFIO_RX[##]n I/O, RX channel DIFFIO_TX[##]p, DIFFIO_TX[##]n I/O, TX channel These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DIFFOUT_[##]p, DIFFOUT_[##]n I/O, TX channel These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DQS[##][T,B], DQS[##][L,R] I/O,DQS External Memory Interface Pins Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic. DQSn[##][T,B], DQSn[##][L,R] I/O,DQSn Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. DQ[##][T,B], DQ[##][L,R] I/O,DQ CQ[##][T,B], CQ[##][L,R] CQn[##][T,B], CQn[##][L,R] DQS Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Optional data strobe signal for use in QDR II SRAM. These are the pins for echo clocks. DQS Optional complementary data strobe signal for use in QDR II SRAM. These are the pins for echo clocks. RUP[1:8]A, (Note 7) RUP[3,8]C RDN[1:8]A, (Note 7) RDN[3,8]C DNU NC I/O, Input VCC VCCD_PLL_[L,R][1:4], VCCD_PLL_[T,B][1:2] VCCPT VCCA_PLL_[L,R][1:4], VCCA_PLL_[T,B][1:2] VCCAUX VCCIO[1:8][A,C], VCCIO[2,3,4,5,7,8]B Power Power VCCPGM VCCPD[1:8][A,C], VCCPD[2,3,4,5,7,8]B VCC_CLKIN[3,4,7,8]C VCCBAT Power Power Configuration pins power supply. Dedicated power pins. This supply is used to power the I/O pre-drivers. Power Power Differential clock input power supply for top and bottom I/O banks. Battery back-up power supply for design security volatile key register. PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. I/O, Input Do Not Use No Connect Power Power Power Power Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. Differential I/O Pins These are true LVDS receiver channels on side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. Reference Pins Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin. Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin. Do not connect to power or ground or any other signal; must be left floating. Do not drive signals into these pins. Supply Pins VCC supplies power to the core and periphery. Digital power for PLL[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in data sheet, even if the PLL is not used. Power supply for the programmable power technology. Analog power for PLL [L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in data sheet, even if the PLL is not used. It is advised to keep this pin isolated from other VCC for better jitter performance. Auxiliary supply for the programmable power technology. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), HSTL(12, 15, 18), SSTL(15, 18, 2), 3.0 V PCI/PCI-X I/O as well as LVTTL 3.3 V I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), 3.0 V PCI/PCI-X and LVTTL 3.3 V I/O standards. Pin Definitions Page 40 of 43 ® Pin Information for the Stratix IV GT EP4S100G4 Device Version 1.3 Notes (1), (2), (5) Pin Name GND VREF[1:8][A,C]N0, VREF[2,3,4,5,7,8]BN0 Pin Type (1st and 2nd Function) Pin Description Device ground pins. Ground Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the Power bank. Transceiver (I/O Banks) Pins Power PCIe Hard IP digital power supply, specific to the left (L) side or right (R) side of the device. Power Analog power, receiver, specific to the left (L) side or right (R) side of the device. Power Analog power, transmitter, specific to the left (L) side or right (R) side of the device. Power Analog power, block level clock distribution. Power Analog power, block level TX buffers, specific to left (L) side and right (R) side. Power Analog power, TX driver, RX receiver, CDR, specific to the left (L) side or right (R) side of the device. Input High speed positive differential receiver channels. Specific to the left (L) side or right (R) side of the device. Input High speed negative differential receiver channels. Specific to the left (L) side or right (R) side of the device. Output High speed positive differential transmitter channels. Specific to the left (L) side or right (R) side of the device. Output High speed negative differential transmitter channels. Specific to the left (L) side or right (R) side of the device. Input High speed differential reference clock positive, or CMU receiver channels, specific to the left (L) side or right (R) side of the device. VCCHIP_[L,R] VCCR_[L,R] VCCT_[L,R] VCCL_GXB[L,R][0:3] VCCH_GXB[L,R][0:3] VCCA_[L,R] GXB_RX_[L,R][0:15]p (Note 3) GXB_RX_[L,R][0:15]n (Note 3) GXB_TX_[L,R][0:15]p (Note 3) GXB_TX_[L,R][0:15]n (Note 3) REFCLK_[L,R][0:7]p, GXB_CMURX_[L,R][0:7]p (Note 3 and 4) REFCLK_[L,R][0:7]n, Input High speed differential reference clock complement, or CMU complementary receiver channel, specific to the left (L) side or right (R) side of the device. GXB_CMURX_[L,R][0:7]n (Note 3 and 4) GXB_CMUTX_[L,R][0:7]p, (Note 4) Output CMU transmitter channels, specific to the left (L) side or right (R) side of the device. GXB_CMUTX_[L,R][0:7]n RREF_[L,R][0:1] Input Reference resistor for transceiver, specific to the left (L) side or right (R) side of the device. Notes: 1. This pin definition is prepared based on the EP4S100G5. 2. Some of the pull-up /pull down resisitors mentioned in the table above may not be required, depending on the exact device configuration scheme. The ability to NC or short them may be valuable during the debug phase, should you be required to use a different configuration scheme. Refer to the Configuring Stratix IV GX Devices chapter in the Stratix IV GX Device Handbook for more information. 3. Transceiver signals GXB_RX[15..0] and GXB_TX[15..0] are device specific. 4. Dual purpose CMU Receiver channels. Can be used either as reference clock or CMU receiver channels in devices with 5th and 6th channels. 5. Refer to pin connections guidelines and data sheet for the recommended operating voltage. 6. Although some configuration pins may indicate that they serve as dual purpose (I/O and configuration) pins, this functionality is device dependent. Refer to the pin list to determine if the regular I/O function is available for the specific dual-purpose configuration pin. 7. The regular I/O function is not available for some of these reference pins. The availability of the regular I/O function on these reference pins is device dependent. Refer to the pin list to determine if the regular I/O function is available for the specific reference pin. PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. Pin Definitions Page 41 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Notes (1), (2) PLL_L4 5B 5A 2B 2A 3A 3B 3C VREFB3AN0 VREFB3BN0 VREFB3CN0 PLL_B1 PLL_B2 4C 4B 4A VREFB4CN0 VREFB4BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB5CN0 PLL_R3 5C PLL_L3 2C PLL_R2 Transceiver Block (QR3) PLL_R1* Transceiver Block (QR2) 7A VREFB7AN0 Transceiver Block (QR1) 7B VREFB7BN0 Transceiver Block (QR0) 7C VREFB7CN0 VREFB6CN0 VREFB6AN0 PLL_T2 6A PLL_T1 6C 8C VREFB8CN0 1A 8B VREFB8BN0 1C VREFB1CN0 VREFB1AN0 8A VREFB8AN0 PLL_L2 VREFB2AN0 VREFB2BN0 VREFB2CN0 Transceiver Block (QL0) Transceiver Block (QL1) Transceiver Block (QL2) Transceiver Block (QL3) PLL_L1* PLL_R4 Notes: 1. This is only a pictorial representation to provide an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations. 2. PLLs with * do not have dedicated input pins. PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. Bank & PLL Diagram Page 42 of 43 Pin Information for the Stratix® IV GT EP4S100G4 Device Version 1.3 Version Number 1.0 Date 9/18/2009 1.1 12/3/2009 1.2 10/10/2013 1.3 2/4/2015 PT-EP4S100G4-1.3 Copyright © 2015 Altera Corp. Changes Made Initial release. - Added bank number for JTAG pins. - Added Note (6) and Note (7) in Pin Definitions. - Grouped nCSO, ASDO, and DCLK into dedicated configuration/JTAG pins in Pin Definitions. - Marked * to pin AY5, AY6, AY39, and AY40 in F1932 package. - Added note to F1932 package. Added the Dynamic OCT Support column in the Pin List. Revision History Page 43 of 43