Report - Active-Semi

QUALCOMM® QUICK CHARGE™ 2.0 TECHNOLOGY
VERIFICATION TEST REPORT
FOR
QC2.0 CHIPSET
MODEL NUMBER: ACT4526
REPORT NUMBER: 4787034072-1
ISSUE DATE: AUGUST 21, 2015
Prepared for
ACTIVE-SEMI INC.
700 CENTRAL EXPRESSWAY SOUTH
ONE ALLEN CENTER, SUITE 330
ALLEN, TX 75013, U.S.A
Prepared by
UL VERIFICATION SERVICES INC.
47173 BENICIA STREET
FREMONT, CA 94538, U.S.A.
TEL: (510) 771-1000
FAX: (510) 661-0888
REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
DATE: August 21,2015
Revision History
Rev.
--
Issue
Date
Revisions
Revised By
08/21/2015
Initial Issue
E. Rincand
Page 2 of 23
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
DATE: August 21,2015
TABLE OF CONTENTS
1.
ATTESTATION OF TEST RESULTS ................................................................................. 4
2.
TRADEMARK NOTICES ..................................................................................................... 5
3.
TEST METHODOLOGY ..................................................................................................... 5
4.
FACILITIES AND ACCREDITATION ................................................................................. 5
5.
CALIBRATION AND UNCERTAINTY ................................................................................ 5
6.
5.1.
MEASURING INSTRUMENT CALIBRATION .............................................................. 5
5.2.
TEST AND MEASUREMENT EQUIPMENT................................................................. 5
EQUIPMENT UNDER TEST ............................................................................................... 6
6.1.
7.
DESCRIPTION OF EUT .............................................................................................. 6
TEST RESULTS ................................................................................................................. 7
7.1.
Charger Insertion and D+/D- Shorting Time ................................................................. 7
7.2.
D+/D- Shorting at 3.3 V ................................................................................................ 8
7.3.
Rdcp_dat ..................................................................................................................... 9
7.4. HVDCP Negotiation ....................................................................................................10
7.4.1. One second Glitch Filter ......................................................................................10
7.4.2. Rdm_dwn ............................................................................................................11
7.5.
Rdat_lkg .....................................................................................................................11
7.6. PD Request Recognition .............................................................................................12
7.6.1. Output Voltage .....................................................................................................12
7.6.2. Transition from 5 V to 12 V ..................................................................................13
7.6.3. Transition from 12 V to 9 V ..................................................................................14
7.6.4. Class A: Maintain 9 V with 20 V Request .............................................................15
7.6.5. Class A: Maintain 9 V with Reserved Request .....................................................16
7.6.6. Class A: Transition from 12 V to 5 V ....................................................................17
7.7. PD Removal................................................................................................................18
7.7.1. Unplug Vbus Discharge Time ..............................................................................18
7.7.2. Re-insertion .........................................................................................................19
7.8. PD USB PHY Error Rejection .....................................................................................20
7.8.1. Square Wave Error Rejection ..............................................................................20
7.8.2. D+/D- External Short Error Rejection ...................................................................21
7.8.3. Recovery from D+/D- External Short ....................................................................22
8.
SETUP PHOTO .................................................................................................................23
Page 3 of 23
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
DATE: August 21,2015
1. ATTESTATION OF TEST RESULTS
COMPANY NAME:
ACTIVE-SEMI INC.
700 CENTRAL EXPRESSWAY SOUTH
ONE ALLEN CENTER, SUITE 330
ALLEN, TX 75013, U.S.A
EUT DESCRIPTION:
QC2.0 REFERENCE DESIGN
MODEL:
ACT4526
SERIAL NUMBER:
001
DATE TESTED:
AUGUST 17, 2015
APPLICABLE STANDARDS
STANDARD
TEST RESULTS
High Voltage Dedicated Charging Port
Pass
Interface Specification Revision AG
UL Verification Services Inc. tested the above equipment in accordance with the requirements
set forth in the above standards. All indications of Pass/Fail in this report are opinions
expressed by UL Verification Services Inc. based on interpretations and/or observations of test
results. Measurement Uncertainties were not taken into account and are published for
informational purposes only. The test results show that the equipment tested is capable of
demonstrating compliance with the requirements as documented in this report.
Note: The results documented in this report apply only to the tested sample, under the
conditions and modes of operation as described herein. This document may not be altered or
revised in any way unless done so by UL Verification Services Inc. and all revisions are duly
noted in the revisions section. Any alteration of this document not carried out by UL Verification
Services Inc. will constitute fraud and shall nullify the document. This report must not be used
by the client to claim product certification, approval, or endorsement by Qualcomm.
Approved & Released For
UL Verification Services Inc. By:
Tested By:
EDGARD RINCAND
PROJECT LEAD
UL Verification Services Inc.
KALVIN CHIU
LABORATORY TECHNICIAN
UL Verification Services Inc.
Page 4 of 23
UL VERIFICATION SERVICES INC.
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
DATE: August 21,2015
2. TRADEMARK NOTICES
Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other
countries. Qualcomm Quick Charge is a trademark of Qualcomm Incorporated. All Qualcomm
Incorporated marks are used with permission.
3. TEST METHODOLOGY
The tests documented in this report were performed in accordance with High Voltage Dedicated
Charging Port HVDCP Compliance Plan Revision D.
4. FACILITIES AND ACCREDITATION
The test sites and measurement facilities used to collect data are located at 47173 Benicia
Street, Fremont, California, USA.
UL Verification Services Inc. is accredited by NVLAP, Laboratory Code 200065-0. The full
scope of accreditation can be viewed at http://ts.nist.gov/standards/scopes/2000650.htm.
Notes:
1. All measurements documented in this report are outside the scope of the Laboratory’s
NVLAP accreditation.
2. The Laboratory used for performing the measurements documented in this report is third
party accredited to ISO 17025.
5. CALIBRATION AND UNCERTAINTY
5.1.
MEASURING INSTRUMENT CALIBRATION
The measuring equipment utilized to perform the tests documented in this report has been
calibrated in accordance with the manufacturer's recommendations, and is traceable to
recognized national standards.
5.2.
TEST AND MEASUREMENT EQUIPMENT
The following test and measurement equipment was utilized for the tests documented in this
report:
Description
TEST EQUIPMENT LIST
Manufacturer
Model
Asset
Cal Date
Cal Due
SourceMeasure Unit
Keithley
2602B
83535
12/11/2015
12/11/2015
Oscilloscope
Teledyne Lecroy
HDO6034
82997
12/9/2013
12/9/2015
Electronic Load
Agilent
6060B
82985
1/14/2015
1/14/2016
Page 5 of 23
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
DATE: August 21,2015
6. EQUIPMENT UNDER TEST
6.1.
DESCRIPTION OF EUT
The EUT is a QUALCOMM® Quick Charge™ 2.0 Class A chipset.
Input power is furnished by a 13.5 Vdc.
The rated output current at each output voltage is as follows:
Output Voltage
(Volts)
5
9
12
Rated Current
(Amps)
2.4
2.4
2.4
HVDCP detection is performed by U1, Part Number ACT4526.
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
DATE: August 21,2015
7. TEST RESULTS
7.1.
Charger Insertion and D+/D- Shorting Time
LIMITS AND RESULTS
Parameter
Td+_d-_short
Start of
End of
Timing
Timing
Measured Maximum Pass/Fail
Value
Limit
(ms)
(ms)
2.05
20
Vbus >= 0.8 V
D- >= 0.5 V
(Min Votg_sess_vld) (Min Vdm_src)
PASS
WAVEFORM AND MEASUREMENTS
D+/D- SHORTING TIME
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
7.2.
DATE: August 21,2015
D+/D- Shorting at 3.3 V
LIMITS AND RESULTS
Requirement: D- remains shorted to D+ when D+ is set to 3.3 V and D- Floats
Beginning 1.5 seconds (Max Tglitch_bc_done) after D+ >= 2.2 V (Max Vsel_ref),
confirm D- >= 2.2 V (Max Vsel_ref)
Parameter Measured Minimum Pass/Fail
Value
D-
Limit
(V)
(V)
2.26
2.2
PASS
WAVEFORM AND MEASUREMENTS
D+/D- SHORTING AT 3.3 V
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
7.3.
DATE: August 21,2015
Rdcp_dat
LIMITS AND RESULTS
Measured Measured Measured Rdcp_dat Rdcp_dat Pass/Fail
D+
D-
D-
Measured Maximum
Voltage
Voltage
Current
Value
Limit
(V)
(V)
(mA)
(ohms)
(ohms)
0.200
0.190
-1.000
10.0
40
PASS
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
7.4.
DATE: August 21,2015
HVDCP Negotiation
7.4.1. One second Glitch Filter
LIMITS AND RESULTS
Parameter
Tglitch_bc_done
Start of
End of
Timing
Timing
Measured Minimum Maximum Pass/Fail
D+ >= 0.4 V
D- <= 0.25 V
(Max Vdat_ref) (Min Vdat_ref)
Value
Limit
Limit
(s)
(s)
(s)
1.19
1.0
1.5
PASS
WAVEFORM AND MEASUREMENTS
HVDCP NEGOTIATION
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
DATE: August 21,2015
7.4.2. Rdm_dwn
LIMITS AND RESULTS
Parameter Measured Minimum Maximum Pass/Fail
Rdm_dwn
7.5.
Value
Limit
Limit
(k ohms)
(k ohms)
(k ohms)
18.830
14.25
24.80
PASS
Rdat_lkg
LIMITS AND RESULTS
Parameter Measured Minimum Maximum Pass/Fail
Rdat_lkg
Value
Limit
Limit
(k ohms)
(k ohms)
(k ohms)
822.0
300
1500
PASS
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REPORT NO: 4787034072-1
EUT: QC2.0 CHIPSET
7.6.
DATE: August 21,2015
PD Request Recognition
7.6.1. Output Voltage
LIMITS AND RESULTS
Output Voltage at No Load
Nominal
Load
Measured
Minimum
Maximum
Pass/Fail
Vbus
Current
Vbus
Limit
Limit
(V)
(A)
(V)
(V)
(V)
5
0.0
5.10
4.75
5.50
PASS
9
0.0
9.22
8.10
9.90
PASS
12
0.0
12.23
10.80
13.20
PASS
Output Voltage at Max Rated Load
Nominal
Load
Measured
Minimum
Vbus
Current
Vbus
Limit
Pass/Fail
(V)
(A)
(V)
(V)
5
2.4 A
5.19
4.75
PASS
9
2.4 A
9.31
8.10
PASS
12
2.4 A
12.33
10.80
PASS
Page 12 of 23
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EUT: QC2.0 CHIPSET
DATE: August 21,2015
7.6.2. Transition from 5 V to 12 V
LIMITS AND RESULTS
Parameter
Tglitch_v_change
Tv_new_request
Start of
End of
Timing
Timing
Measured Minimum Maximum Pass/Fail
Value
Limit
Limit
(ms)
(ms)
(ms)
41.14
20
D- >= 0.4 V
Vbus >= 5.5 V
(Max Vdat_ref) (Max Vbus,5v)
D- >= 0.4 V Vbus >= 10.8 V
(Max Vdat_ref) (Min Vbus,hv)
63.21
PASS
200
PASS
WAVEFORM AND MEASUREMENTS
TRANSITION FROM 5 V TO 12 V
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EUT: QC2.0 CHIPSET
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7.6.3. Transition from 12 V to 9 V
LIMITS AND RESULTS
Parameter
Tglitch_v_change
Tv_new_request
Start of
End of
Timing
Timing
Measured Minimum Maximum Pass/Fail
Value
Limit
Limit
(ms)
(ms)
(ms)
52.27
20
D+ >= 2.2 V Vbus <= 10.8 V
(Max Vsel_ref) (Min Vbus,hv)
D+ >= 2.2 V
Vbus <= 9.9 V
(Max Vsel_ref) (Max Vbus,hv)
59.91
PASS
200
PASS
WAVEFORM AND MEASUREMENTS
TRANSITION FROM 12 V TO 9 V
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EUT: QC2.0 CHIPSET
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7.6.4. Class A: Maintain 9 V with 20 V Request
LIMITS AND RESULTS
Initial Condition: Vbus is 9 volts
Observation Period: Monitor for longer than 200 ms (Min Tv_new_request) after 20 Volt
Request is asserted
Parameter Measured Minimum Maximum Pass/Fail
Vbus
Value
Limit
Limit
(V)
(V)
(V)
9.210
8.10
9.90
PASS
WAVEFORM AND MEASUREMENTS
MAINTAIN 9 V WITH 20 V REQUEST
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EUT: QC2.0 CHIPSET
DATE: August 21,2015
7.6.5. Class A: Maintain 9 V with Reserved Request
LIMITS AND RESULTS
Initial Condition: Vbus is 9 volts
Observation Period: Monitor for longer than 200 ms (Min Tv_new_request) after Reserved
Request is asserted
Parameter Measured Minimum Maximum Pass/Fail
Vbus
Value
Limit
Limit
(V)
(V)
(V)
9.210
8.10
9.90
PASS
WAVEFORM AND MEASUREMENTS
MAINTAIN 9 V WITH RESERVED REQUEST
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EUT: QC2.0 CHIPSET
DATE: August 21,2015
7.6.6. Class A: Transition from 12 V to 5 V
LIMITS AND RESULTS
Parameter
Tglitch_v_change
Tv_new_request
Start of
End of
Timing
Timing
D- <= 0.25 V Vbus <= 10.8 V
(Min Vdat_ref) (Min Vbus,hv)
D- <= 0.25 V Vbus <= 5.5 V
(Min Vdat_ref) (Max Vbus,5v)
Measured Minimum Maximum Pass/Fail
Value
Limit
Limit
(ms)
(ms)
(ms)
50.66
20
99.25
PASS
200
PASS
WAVEFORM AND MEASUREMENTS
TRANSITION FROM 12 V TO 5 V
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EUT: QC2.0 CHIPSET
7.7.
DATE: August 21,2015
PD Removal
7.7.1. Unplug Vbus Discharge Time
LIMITS AND RESULTS
Parameter Product
Type
Tv_unplug Class A
Start of
End of
Timing
Timing
Measured Maximum Pass/Fail
D+ <= 0.5 V Vbus <= 5.5 V
(Min Vdp_src) (Max Vbus,5v)
Value
Limit
(ms)
(ms)
61.95
500
PASS
WAVEFORM AND MEASUREMENTS
PD REMOVAL
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7.7.2. Re-insertion
LIMITS
Requirement: D- remains shorted to D+ when PD is re-inserted to downstream port with D+ at
3.3 V and D- Floating
Beginning 1.5 seconds (Max Tglitch_bc_done) after D+ >= 2.2 V (Max Vsel_ref),
confirm D- >= 2.2 V (Max Vsel_ref)
Parameter Measured Minimum Pass/Fail
D-
Value
Limit
(V)
(V)
3.30
2.2
PASS
WAVEFORM AND MEASUREMENTS
PD RE-INSERTION
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7.8.
DATE: August 21,2015
PD USB PHY Error Rejection
7.8.1. Square Wave Error Rejection
LIMITS AND RESULTS
Initial Condition: Vbus is 5 volts
Applied Waveform: 0.6 Volt square wave is applied to D+
Requirements: D- is square wave that tracks square wave on D+, and Vbus remains at 5 volts
Observation Period: Monitor during square wave and at least 2 seconds after square wave
Parameter
Measured Minimum Maximum Pass/Fail
Value
Limit
Limit
(V)
(V)
(V)
5.080
4.75
5.50
D+/ D- Tracking
Vbus
PASS
PASS
WAVEFORM AND MEASUREMENTS
SQUARE WAVE ERROR REJECTION
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7.8.2. D+/D- External Short Error Rejection
LIMITS AND RESULTS
Initial Condition: Vbus is 5 volts
Applied Waveform: D+ and D- externally shorted together and held at 0 volts
Then 0.6 volts is applied to D+/DRequirement: Vbus remains at 5 volts
Observation Period: Monitor at least 2 seconds after 0.6 volts is applied
Parameter Measured Minimum Maximum Pass/Fail
Vbus
Value
Limit
Limit
(V)
(V)
(V)
5.080
4.75
5.50
PASS
WAVEFORM AND MEASUREMENTS
D+/D- EXTERNAL SHORT ERROR REJECTION
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7.8.3. Recovery from D+/D- External Short
LIMITS AND RESULTS
Initial Condition: D+ and D- externally shorted together and held at 0.6 volts
Setup: Short is removed and D- allowed to float
Response: HVCDP asserts Rdm_dwn
Applied Waveform: 0.6 V is applied to DRequirement: Vbus makes a normal transition from 5 volts to 12 volts
Parameter
Tglitch_v_change
Tv_new_request
Start of
End of
Timing
Timing
Measured Minimum Maximum Pass/Fail
Value
Limit
Limit
(ms)
(ms)
(ms)
40.80
20
D- >= 0.4 V
Vbus >= 5.5 V
(Max Vdat_ref) (Max Vbus,5v)
D- >= 0.4 V Vbus >= 10.8 V
(Max Vdat_ref) (Min Vbus,hv)
63.00
PASS
200
PASS
WAVEFORM AND MEASUREMENTS
RECOVERY FROM D+/D- EXTERNAL SHORT
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EUT: QC2.0 CHIPSET
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8. SETUP PHOTO
MEASUREMENT SETUP
END OF REPORT
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