NCV7381 FlexRay Bus Driver Application Note

AND9081/D
NCV7381 FlexRay Bus
Driver Application Note
Introduction
NCV7381 is a single-channel FlexRay bus driver compliant with
the FlexRay Electrical Physical Layer Specification Rev. 3.0.1,
capable of communicating at speeds of up to 10 Mbit/s.
It provides differential transmit and receive capability between
a wired FlexRay communication medium on one side and a protocol
controller and a host on the other side. The NCV7381 mode control
functionality is optimized for nodes permanently connected to the car
battery.
This document provides additional output characteristics for the
digital output and INH pins, it gives PCB Layout recommendation and
it analyzes the behavior of the NCV7381 in case of operating mode
transition request.
• Digital outputs DC characteristics
• INH pin output characteristics
• Bus Driver PCB Layout
• Mode Transitions – STBN and EN Pin Filtering Time
• Optional ESD Protection
IN
OUT
CVIO
1
VIO
(Top View)
VBAT
IN
OUT
CVCC
VCC
CVBAT
INH VBAT
RWAKE2
TxD
Rtxd
Rrxd
Bus Guardian
RxD
RxEN
NCV7381
CMC
BP
BP
BM
BM
BGE
RBUS1
STBN
Host Interface
WAKE
WAKE
TxEN
Rtxen
VCC
BP
BM
GND
WAKE
VBAT
ERRN
RxEN
INH
EN
VIO
TxD
TxEN
RxD
BGE
STBN
EN
RBUS2
FlexRay
Communication
Controller
NCV7381 Pin Connections
VCC
reg.
VIO
reg.
MCU
APPLICATION NOTE
RWAKE1
ECU
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ERRN
GND
CBUS
ESD
GND
Figure 1. NCV7381 Application Diagram
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 2
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Publication Order Number:
AND9081/D
AND9081/D
Digital Outputs DC Characteristics
Typical digital outputs (RxD, RxEN and ERRN)
characteristics are shown in the figures below. The
characteristics are measured at room ambient temperature,
in Normal mode (STBN and EN forced High), with no
undervoltage and with supply voltages: VBAT = 12 V,
VCC = 5 V, VIO = 3.3 V and 5 V.
VIO
LOW
VIO
DOUT
HIGH
iDOUT
V
DOUT
uDOUT
V
(VIO−uDOUT)
−iDOUT
GND
GND
Figure 2. Test Setup for Output Low
Characteristics on Digital Output Pins
Figure 3. Test Setup for Output High
Characteristics on Digital Output Pins
RxD Digital Output
1200
VIO = 3.3 V
TEMP = 25°C
TEMP = 25°C
600
VIO−uRxDOH, VIO−OUTPUT
VOLTAGE (mV)
uRxDOL, OUTPUT VOLTAGE (mV)
700
VIO = 3.3 V
1000
500
VIO = 5 V
400
300
200
100
800
VIO = 5 V
600
400
200
0
0
0
5
10
15
20
25
0
30
iRxDOL, OUTPUT SINK CURRENT (mA)
5
10
15
20
25
30
−iRxDOH, OUTPUT SOURCE CURRENT (mA)
Figure 4. Typical RxD Output Sink
Characteristics
Figure 5. Typical RxD Output Source
Characteristics
RxEN Digital Output
1200
VIO = 3.3 V
TEMP = 25°C
VIO = 3.3 V
TEMP = 25°C
350
VIO−uRxENOH, VIO−OUTPUT
VOLTAGE (mV)
uRxENOL, OUTPUT VOLTAGE (mV)
400
1000
300
VIO = 5 V
250
200
150
100
50
800
VIO = 5 V
600
400
200
0
0
0
5
10
15
20
25
0
30
iRxENOL, OUTPUT SINK CURRENT (mA)
5
10
15
20
25
−iRxENOH, OUTPUT SOURCE CURRENT (mA)
Figure 6. Typical RxEN Output Sink
Characteristics
Figure 7. Typical RxEN Output Source
Characteristics
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AND9081/D
ERRN Digital Output
1000
VIO = 3.3 V
TEMP = 25°C
VIO−uERRNOH, VIO−OUTPUT
VOLTAGE (mV)
uERRNOL, OUTPUT VOLTAGE (mV)
1000
800
VIO = 5 V
600
400
200
VIO = 3.3 V
TEMP = 25°C
VIO = 5 V
800
600
400
200
0
0
0
1
2
3
4
0
5
iERRNOL, OUTPUT SINK CURRENT (mA)
1
2
3
4
5
−iERRNOH, OUTPUT SOURCE CURRENT (mA)
Figure 8. Typical ERRN Output Sink
Characteristics
Figure 9. Typical ERRN Output Source
Characteristics
INH Pin Output Characteristics
in Normal mode (STBN and EN forced High), with no
undervoltage and with VBAT = 4.9 V and 14 V.
The NCV7381 provides a high-voltage output pin INH
which can be used to control an external voltage regulator
(see Figure 1). The pin INH is driven by a switch to VBAT
supply. In Normal, Receive-only, Standby and Go-to-Sleep
modes, the switch is activated thus forcing a High level on
the pin INH. In Sleep mode, the switch is open and INH pin
remains floating. If a regulator is directly controlled by the
INH, it is then active in all operating modes with an
exception of the Sleep mode.
A typical INH switch voltage drop as a function of the
INH pin output load current is shown in Figure 11. The
characteristics are measured at room ambient temperature,
VBAT
V
(VBAT−uINH)
INH
NCV7381
−iINH
GND
VBAT−uINH, INH VOLTAGE DROP (mV)
Figure 10. Test Setup for INH Output Characteristics
300
VBAT = 14 V
TEMP = 25°C
250
VBAT = 4.9 V
200
150
100
50
0
0
1
2
3
4
−iINH, OUTPUT CURRENT (mA)
Figure 11. Typical INH Output Characteristic
(INH signaling Not_Sleep)
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AND9081/D
Bus Driver PCB Layout
• Route the BP and BM signal lines symmetric.
• Keep the distance between the lines BP and BM
An example PCB layout is shown in the figure below.
Modification of this layout is possible with the following
recommendations:
• Place the NCV7381, the common mode choke and the
optional ESD protection as near as possible to the BP
and BM pins of the ECU connector.
minimal.
• Keep the decoupling capacitors close to the particular
•
supply pins.
Keep the ground plane uninterrupted if possible.
Top Layer Copper
Bottom Layer Copper
Top Layer Overlay
Bottom Layer Overlay
Figure 12. Example PCB Layout
Table 1. NCV7381: RECOMMENDED EXTERNAL COMPONENTS
Component
Function
Value
Unit
Note
CVBAT
Decoupling Capacitor on Battery Line, Ceramic (X7R)
100
nF
Type 0603
CVCC
Decoupling Capacitor on VCC Supply Line, Ceramic (X7R)
100
nF
Type 0603
CVIO
Decoupling Capacitor on VIO Supply Line, Ceramic (X7R)
100
nF
Type 0603
RWAKE1
Pull-up Resistor on WAKE Pin
33
kW
Type 0805
RWAKE2
Serial Protection Resistor on WAKE Pin
3.3
kW
Type 0805
RBUS1
Bus Termination Resistor
47.5
W
Type 0805, (Note 2)
RBUS2
Bus Termination Resistor
47.5
W
Type 0805, (Note 2)
CBUS
Common-mode Stabilizing Capacitor, Ceramic
4.7
nF
Type 0805, ±20%
CMC
Common-mode Chokes
100
mH
(Note 1)
ESD
Optional ESD Protection
NUP2115
−
Type SOT−23
1. Recommended common-mode chokes:
MURATA DLW43SH101XK2
MURATA DLW43SH510XK2
MURATA DLW43SH101XP2
EPCOS B82799C0104N001
TDK ACT45R−101−2P−TL001
2. Tolerance ±1%; the value RBUS1 + RBUS2 should match the nominal cable impedance.
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AND9081/D
MODE TRANSITIONS – STBN AND EN PIN FILTERING TIME
should be taken especially in case the EN falling edge is
delayed too much with respect to the STBN falling edge, this
could be considered as a Sleep mode transition request.
Taking into account that the EN pin is ignored in Sleep
mode, the original intention to enter Standby mode would
not be completed (Figure 15).
If both STBN and EN go from High to Low at the same
time (driven externally or driven by internal pull-down
resistors), Standby mode is entered (Figure 13).
Even if the EN pin goes Low worst case 2 oscillator
periods later than the STBN pin, the resulting operating
mode is still Standby. Considering dGo-To-Sleep limiting
values, the delay between STBN and EN pin falling edge
should be less than 14 ms, in order to enter Standby mode
successfully (Figure 14).
A delay between 14 ms and 51 ms leads to an uncertain
mode transition – Standby mode or Sleep mode may be
entered.
In case the delay STBN falling edge to EN falling edge is
more than 51 ms, it is guaranteed that Sleep mode is entered.
In summary, the Standby mode is successfully entered if
the delay between STBN and EN pin falling edges is less
than 14 ms. Sleep mode is successfully entered if the delay
between STBN and EN pin falling edges is more than 51 ms.
The resulting operating mode is a function of the host
signals STBN and EN, the state of the supply voltages and
the wakeup detection.
During normal operation, the operating mode is directed
by a host command – the host is directly driving pins STBN
and EN to an appropriate logical state. In some cases these
pins may be disconnected − usually during a microcontroller
reset state, when the microcontroller’s outputs may be put
into a high-impedance state. In this case the resulting
operating mode is determined by the NCV7381 EN and
STBN pins internal pull-down resistors.
The STBN and EN pins are internally debounced and
synchronized with the internal oscillator. The implemented
debouncing time is 3 internal oscillator periods. Due to the
synchronization, the actual delay between a change at the
pin and a change of the internal signal may vary between
3 and 4 oscillator periods (parameter dBDModeChange, see
the pictures below). The internal STBN and EN signal
change is aligned with the internal oscillator rising edge.
Operating Mode Transition − Normal to Standby
A transition from Normal mode to Standby mode is
initialized, when both STBN and EN, originally being High,
are set Low (Figure 13). The STBN and EN falling edge do
not need to occur exactly at the same time. However caution
Int OSC
STBN Pin
EN Pin
STBN
Internal
EN
Internal
OP MODE
NORMAL MODE
STANDBY
dBDModeChange 3−4 OSC periods
Figure 13. Mode Transition Example – STBN and EN Go Low at the Same Time
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AND9081/D
Int OSC
STBN Pin
EN Pin
STBN
Internal
EN
Internal
OP MODE
NORMAL MODE
GO−TO−SLEEP MODE
STANDBY
dBDModeChange
3−4 OSC periods
dBDModeChange 3−4 OSC periods
Figure 14. Mode Transition Example – EN goes Low max. 2 Osc. Period later than STBN
Int OSC
STBN Pin
EN Pin
STBN
Internal
EN
Internal
OP MODE
NORMAL MODE
GO−TO−SLEEP MODE
dBDModeChange
(3−4 OSC periods)
dGo−To−Sleep 2 OSC periods
More than 2 OSC periods
dBDModeChange (3−4 OSC periods)
SLEEP MODE
Figure 15. Mode Transition Example – EN goes Low more than 2 Osc. Period later than STBN
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AND9081/D
OPTIONAL ESD PROTECTION
In order to improve system reliability an additional
external ESD protection may be used. As a result of the high
speed nature, the FlexRay specification calls for a low
capacitance protection of up to 20 pF and a tight deviation
in capacitance between the signal pairs limited to 2%. The
reason is that any additional ESD protection represents a
capacitive load on the bus lines which can have undesired
effects on electromagnetic emissions and immunity if the
bus lines capacitive load does not match properly.
The NUP2115, dual line FlexRay Bus Protector, is
designed for the highest possible signal integrity by limiting
the stray capacitance to 10 pF max while having a nominal
capacitance matching at 0.26% and achieving the ESD and
other transient protection requirements.
System ESD measurement results are shown in the
Table 2. Tested without external bus filter network, which is
the worst case. The absolute values are from internal
measurements. It indicates noticeable increase of the
maximum possible discharge voltage. The values measured
by external laboratory are visible in device datasheets [1][4].
Table 2. SYSTEM HBM ON PINS BP AND BM,
per IEC 61000-4-2; 150 pF/330 W
NCV7381
NCV7381 + NUP2115L
±6 kV
Requirement
Pin
No failure up to:
BP
±13 kV
±21 kV
BM
±13 kV
±21 kV
For more information on the device details, see the
product datasheet [4].
Figure 16. SOT−23 Package
REFERENCES
[3] FlexRay Consortium. FlexRay Communications
System − Physical Layer EMC Measurement
Specification, V3.0.1, October 2010
[4] ON Semiconductor, NUP2115L/D, Datasheet, Rev.0,
April 2013
[1] ON Semiconductor, NCV7381/D Datasheet, Rev.0,
May 2012
[2] FlexRay Consortium. FlexRay Communications
System − Electrical Physical Layer Specification,
V3.0.1, October 2010
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