AND8460/D Implementing a 12 V / 240 W Power Supply with the NCP4303B, NCP1605 and NCP1397B http://onsemi.com Prepared by: Roman Stuler, Jaromir Uherek and Ivan Seifert APPLICATION NOTE ON Semiconductor Overview height of only 35 mm. An overview of the entire SMPS architecture is provided in Figure 1. Careful consideration was given to optimizing performance while minimizing the total solution cost. The following document describes a 12 V / 20 A output switch mode power supply (SMPS) intended for use as an ATX power supply main converter or as an All−In−One PC power supply. The reference design circuit consists of a double sided 135 x 200 mm printed circuit board with a NCP4303B SR controller EMI Filter Synchronous Rectification for improved efficiency NCP1605 PFC Controller 90V – 265Vac Frequency Clamped Critical Conduction Mode Power Factor Controller NCP1397B Resonant Controller with built−in Half Bridge Driver Resonant Technology for Increased Efficiency and Lower EMI Bias circuitry 12V / 20A NCP4303B SR controller TL431 Figure 1. Demoboard Block Diagram Architecture Overview Demoboard Specification The circuit utilizes the NCP1605 for an active power factor correction front end. This stage provides a well regulated PFC output voltage that allows optimization of the downstream converter. The NCP1605 controller operates using a Frequency Clamped Critical conduction Mode control technique. The SMPS stage uses a Half Bridge Resonant LLC topology since it improves efficiency, reduces EMI signature and provides better transformer utilization compared to conventional topologies. The NCP1397B controller is used to control the Half Bridge Resonant LLC converter. To maximize efficiency of the LLC power stage, Synchronous Rectification (SR) has been implemented on the secondary side. The NCP4303B SR controller is used to achieve accurate turn−on and turn−off of the SR MOSFETs. In summary, the architecture selected for this reference design allows system optimization so that the maximum efficiency is achieved without significantly increasing the component cost and circuit complexity. Most of today’s computing applications like ATX PC, game consoles and All−in−one PC use 12 V as the main power rail. This voltage is then further decreased to 5 V and 3.3 V by DC/DC step down converters. Because nearly all power passes through the 12 V output, it is critical that the efficiency of the main power stage be optimized. Most designs today utilize an LLC topology for the power stage to provide high efficiency at a reasonable cost. The LLC power stage provides inherently high efficiency results thanks to zero voltage switching (ZVS) on the primary side and zero current switching (ZCS) on the secondary side. Efficiency however decreases for higher output currents as the secondary RMS current reaches a high level. The solution for these losses on the secondary side is to use synchronous rectification instead of conventional rectifiers (Schottky diode). Consideration was also give to optimizing light and no load efficiency, which is particularly important in All−in−one PC SMPS that usually do not utilize an additional standby power supply. © Semiconductor Components Industries, LLC, 2010 August, 2010 − Rev. 2 1 Publication Order Number: AND8460/D AND8460/D di(t)/dt product. This technique allows the use of standard leaded SR MOSFETs, which can reduce assembly process costs (SMT MOSFETs usually require a more expensive PCB and soldering). Based on the above considerations, the following is the required specifications of the SMPS reference design: Table 1. DEMOBOARD SPECIFICATION Min Max Unit Input voltage (ac) Requirement 90 265 V Output voltage (dc) − 12 V Output current 0 20 A Total output power 0 240 W Consumption for a 500 mW output load in STBY mode − 1.7 W Consumption for a 100 mW output load in STBY mode − 1.2 W No load consumption SR operating − 870 mW No load consumption SR turned off, no bypass Shottky used − 1 W 20 mV Load regulation Current Sense Pin Capability of 200 V The high voltage capability of the CS pin allows for direct connection to the SR MOSFET drain. This avoids the use of a high impedance series resistor which would delay the CS signal. Disable Input to Enter Standby or Low Consumption Mode The trigger/disable input integrates two functions: 1st it can be used to turn−off the SR MOSFET in Continuous Current Mode applications (like CCM flyback). 2nd it can be used to switch the controller into standby mode. The SR standby mode decreases SMPS power consumption when the output is not loaded. Parallel Schottky diodes can be used for conduction in this mode rather than the SR MOSFETs. Adjustable Minimum On and Off Times Independent of VCC Level The NCP4303A/B provides the following beneficial features for SR implementation in an LLC power stage: Due to the various impedances in the application (parasitic inductances and capacitances) spurious ringing can occur after the SR MOSFET is turned on or off. To overcome controller false switching due to this parasitic ringing, the NCP4303 utilizes adjustable minimum on and off times. The driver state cannot be changed during these minimum periods. The duration of the minimum on time and minimum off time can be adjusted independently of each other and independent of the IC Vcc level. Precise Zero Current Detection with Adjustable Threshold The NCP4303 SR controller provides a default Zero Current Detection (ZCD) threshold of 0 mV. A 100 mA current source on the CS input allows the customer to decrease this basic ZCD threshold by using a resistor in series with the CS input. The turn−off current threshold can therefore be precisely adjusted down to 0 A to maximize the SR MOSFET conduction time. The result is optimized system efficiency. 5 A / 2.5 A Peak Current Sink / Source Drive Capability The SR MOSFETs for high current applications usually feature high input capacitance. The strong sink driver capability of the NCP4303 decreases the turn−off time and thus allows for optimized conduction time of the SR MOSFET. Typically 40 ns Turn−off Delay from Current Sense Input to Driver Output Once the CS input detects that the secondary current has reached zero, it is necessary to turn−off the SR MOSFET as fast as possible. The extremely low 40 ns propagation delay of the NCP4303 assures that the SR MOSFET will be turned−off quickly, avoiding reverse current flow back into the transformer winding from the secondary filtering capacitor. Operating Voltage Range Up to 30 V The NCP4303 VCC input can be connected directly to the application output voltage without any additional pre−regulation. This feature simplifies driver implementation and reduces application cost. Automatic Parasitic Inductance Compensation Input Gate Driver Clamp of Either 12 V (NCP4303A) or 6 V (NCP4303B) The high secondary RMS current in the LLC stage has a high di(t)/dt product that can induce a high error voltage on the parasitic inductances of the SR MOSFET package (TO220 for instance). Parasitic error voltages shift the drain to source voltage and affect the accuracy of the ZCD system. As a result, the SR MOSFET is turned−off prematurely and efficiency is decreased. NCP4303 offers a method to compensate for this effect via a special input that offsets the ZCD comparator threshold with a compensation voltage. Thanks to this feature, the ZCD comparator can perform precise detection independent of the secondary current Some of today’s SR MOSFETs provide low channel resistance for lower gate voltages (< 6 V). Thus it is beneficial to clamp the driver voltage at a lower level and reduce driving losses. This technique helps to maintain high efficiency, especially under medium and light load conditions. On the other hand, some MOSFETs still require higher gate voltage. NCP4303A provides 12 V gate driver clamp for these cases. Please refer to the datasheet for more http://onsemi.com 2 AND8460/D The rectified AC line is connected to the PFC front end stage (Figure 3). The PFC stage modulates input current to achieve a high power factor and also to prepare a pre−regulated voltage for the LLC power stage. Energy is stored in coil L7 when the MOSFET Q4 is turned−on. The energy stored in coil L7 during on time is added to the rectified voltage on capacitor C15 when MOSFET Q4 is turned−off. The bulk capacitors C16 and C17 are thus charged through diode D5. Bulk voltage is divided down by resistors R17, R28, R34, R46 and R63. The emitter follower Q10 is implemented to allow the use of a high impedance divider, which decreases the SMPS standby consumption. The output voltage from this emitter follower is used for two proposes: 1st to prepare skip mode function of the PFC stage and 2nd to provide the LLC controller with information about the bulk voltage (i.e. is it sufficient for operation of the LLC stage or not). information and a detailed description of the NCP4303A/B SR controller. Detailed Demoboard Description A complete schematic of the demoboard is shown in Figure 58. As mentioned above, the SMPS is composed of three blocks. The PFC front stage accepts input voltages from 90 V ac / 60 Hz up to 265 V ac / 50 Hz and converts it to 395 Vdc nominal. The second block is the LLC power stage that converts the bulk voltage to 12 V / 20 A output. The third block is the synchronous rectification which replaces conventional Schottky rectifiers. PFC Front Stage The input voltage passes through an EMI filter (Figure 2), which protects the distribution network against noise generated by the SMPS. The EMI filter is composed of capacitors CY1, CY2, C33, C47, current compensated choke L15 and differential mode chokes L12, L13. Varistor R48 protects the SMPS from surges passed from the mains. Filtered ac voltage is rectified by a bridge rectifier B1 and connected to the PFC power stage. To minimize the risk of electrical shock after unplugging the power supply, X2 capacitor discharge circuitry is required. Usually safety resistors are used to perform this function. Such a solution however brings some disadvantages. The discharge time increases to unacceptable levels for higher X2 capacitor values. The power loss in the discharge resistors needs to be increased in order to decrease X2 capacitor discharge time. As a result, the no load consumption of the application suffers. To avoid this, a special discharge circuitry has been implemented in this design to minimize X2 capacitor discharge time, without impacting no load consumption. This circuit is composed of charge pump R19, R43, R53, D8, D10, D11, C14, C30, C31, transistors Q6, Q8, discharge resistors R16, R22 and auxiliary bias circuitry R1, R21, C1, D1. When the application is plugged into the mains, the charge pump provides voltage to the Q8 MOSFET gate and keeps it turned−on. The drain of MOSET Q8 pulls down the base of the transistor Q6, which disconnects discharge resistors R16, R22 from the HV input to improve no load efficiency. When the SMPS is disconnected from the mains, the charge pump no longer delivers any current and MOSFET Q8 is turned−off. The auxiliary voltage remains on capacitor C1 and therefore transistor Q6 is turned−on and resistors R16 and R22 discharge the X2 capacitors via the bridge rectifier. The discharge time is shorter than one second. The power consumption of this circuitry is about 6.5 mW for 230 Vac input, a savings of about 86 mW compared to the standard solution with equivalent discharge time. Implementation of the proposed X2 capacitor discharge circuitry also helps to reduce conducted EMI emission because the SMPS designer is less limited by X2 capacitor size vs. discharge time ratio. Figure 2. EMI Filter with X2 Capacitor Discharge Circuitry http://onsemi.com 3 AND8460/D Figure 3. The PFC Stage Connection stage startup there is no voltage available on the PFC_OK pin of IC3 – the LLC stage thus can not start operation. The PFC_OK pin increases to 5 V after the PFC stage reaches regulation level. Current that is sourced by PFC_OK pin voltage and R83 resistor is added to the current flowing out from resistor R87 and together they create a voltage drop on resistors R92, R93. The LLC stage controller uses this network to protect the application when the bulk voltage drops below the adjusted threshold. The PFC output voltage is regulated according to information provided to the FB pin. Output voltage is divided down by resistor divider R18, R27, R35, R47, R56, R57 and connected to the FB pin. Filtering capacitor C26 is used because this is a high impedance divider. The bulk voltage compensation network is composed of capacitors C36, C40 and resistor R75. This network also performs soft start when the PFC stage is turned on. The NCP1605 uses negative current sensing to limit the maximum coil current and to detect the core reset. Current flowing through PFC coil L7 creates a negative voltage on the current sense resistor R38. The PFC controller sources current out of the CS pin in order to maintain a null CS pin voltage. As a result, the CS pin current is directly proportional to the coil current. Resistors R44, R45 are inserted to adjust the CS pin current. When the current The NCP1605 PFC controller features a skip mode function with thresholds that are fixed to the feedback (FB) regulation level. However, the bulk voltage ripple during skip mode would be too high for the LLC topology. Thus, in this design, the PFC skip mode is implemented via the PFC controller OVP input using external bipolar transistor Q11. The operating frequency of the LLC stage increases when output load diminishes. The LLC stage enters skip mode and disables drivers when load further drops. Transistor Q11 is thus turned−off and resistor R76 is disconnected. The PFC OVP pin voltage thus increases above OVP threshold and PFC stage operation is interrupted. The output voltage then naturally drops and the LLC stage recovers operation – the Q11 is turned−on again and PFC stage operation is re−enabled as well because resistor R76 pulls down the OVP pin. With this method, the PFC is forced to periodically recharge the bulk capacitor during light load and no load conditions – the PFC skip mode with adjustable bulk voltage ripple is thus implemented. Because the skip mode is implemented externally via the OVP pin rather than via the standby input, it is necessary to bias the STBY pin above 0.3 V using resistor divider R69, R74. Voltage from the Q10 transistor emitter is also divided down by divider R87, R92, R93 and used to control LLC stage operation via the NCP1397 brown out input. During the PFC http://onsemi.com 4 AND8460/D To protect the PFC from sudden drops in the line voltage, the controller monitors the rectified line voltage via brownout divider R15, R23, R31, R50, R71 and C39. The driver output is connected to MOSFET Q4 via resistors R25, R26 and diode D7 to regulate turn−on speed. Transistor Q7 is used to speed up the MOSFET turn−off time and thus reduce turn−off losses. Please refer to the application note AND8281/D for detailed information on the PFC stage design and operation. flowing through inductor L7 and switch Q4 is higher than the maximum current limit level, the CS pin current increases above the OPC threshold (250 uA) and the driver is turned off. The CS input is also used to detect coil demagnetization for zero current detection. The zero current detection prevents the MOSFET from turning on when current flows through the coil. As long as there is no coil current, the NCP1605 operates at a frequency determined by the internal oscillator and external capacitor C38. Zero current detection circuitry sensitivity is adjusted by resistor R70 and R81. Figure 4. The LLC Stage Primary Side Connection LLC Power Stage Primary Side Primary Side Power Loop Connection The PFC and LLC controllers are powered from the auxiliary winding W4 of transformer TR1. The PFC controller charges up the VCC capacitors C3, C42 first when the demoboard is plugged into the mains. Once the PFC stage starts operation and the bulk voltage is within the nominal operating range, the LLC stage is enabled. The auxiliary winding also provides bias voltage for the X2 capacitor discharge circuitry via diode D1, resistor R1 and capacitor C1. The X2 capacitor discharge circuitry is described in the PFC Stage section (refer to page 3). The PFC stage prepares a regulated voltage on bulk capacitors C16 and C17 for the downstream LLC stage (refer to Figure 3). The LLC stage power loop is closed through Q3 and Q5, transformer TR1 and resonant capacitors C7, C18 (Figure 4). The NCP1397 LLC controller features a 600 V high−side driver and is capable of driving the HB power stage directly without the use of a driver transformer. Resistors R54 and R55 are used to suppress ringing and control EMI noise on the power MOSFET gates. Bootstrap capacitor C53 provides the energy required for controlling the high side MOSFET. When Q5 is turned−on, the HB pin voltage drops and bootstrap capacitor C53 is charged through resistor R96 and high−voltage diode D23. At turn−on and after any restart, the LLC controller turns on MOSFET Q5 first to charge up the bootstrap capacitor. FB Loop and Skip Mode: The minimum operating frequency of the LLC converter is set by resistor R104 (refer to Figure 5). The maximum operating frequency is set by resistor R102. The LLC stage http://onsemi.com 5 AND8460/D Overload and Short Circuit Protection, Soft−Start: will reach maximum operating frequency during no load conditions. Figure 5. The Primary FB Loop and Skip−Mode Circuitry Connection Feedback is provided by optocoupler OK1. The optocoupler current adjusts the FB voltage applied to the LLC controller. The LLC stage operating frequency is thus modulated to assure output voltage regulation. Resistor R84 is used to limit the maximum voltage excursion on the FB pin in case the LLC controller goes out of the regulation range (like during skip mode or transient loading). The skip mode function improves the efficiency of the power supply by omitting switching cycles during light load or no load conditions. The skip mode is implemented using the Skip/Disable pin of the LLC controller. The FB pin voltage increases when the load diminishes. Once the load is too low, the LLC stage is not able to maintain regulation because the operating frequency can not increase further (Fmax clamp – resistor R102). The FB voltage then goes above the Vfb_max limit of 5.3 V. The resistor divider R101 and R105 provides the FB pin voltage to the Skip/Fault input. The output drivers are thus automatically turned−off and the device begins to skip switching cycles. For efficient skip mode, the FB voltage should overshoot from 50% to 70% (depends on FB loop response time) of its nominal regulation level. The FB voltage divider R101 = 5.6 kW and R105 = 820 W was used to allow Vfb to swing between 5 – 7.5 V. This setup provides 20 mV pk−pk output voltage ripple during no load conditions. Figure 6. The Output Overload and/or Short Protection Schematic The Over Current Protection (OCP) is implemented in this design to protect the application from overload conditions. The primary current is sensed indirectly by monitoring the resonant capacitor voltage via the charge pump formed by resistors R42, R52, R64, capacitor C29 and diodes D14, D15 (refer to Figure 6). The charge pump output is loaded by resistor R60 and filtered by capacitor C28. The Soft Start capacitor discharge switch on pin 1 is turned−on once the Fault pin voltage reaches the VRef_fault threshold (1.04 V). The LLC stage operating frequency is thus automatically increased as the Soft−Start capacitor voltage drops and higher current flows out from the Rt pin. The frequency shift naturally reduces the primary current and protects the primary MOSFETs against damage. Also at this time, the Itimer1 current source is activated on pin 3 and it begins charging external timing capacitor C56. If the overload condition lasts for longer than the time constant set by Itimer1 current and timer pin components (C56, R103), the controller enters protection mode and output drivers are disabled. Once the timer capacitor C56 is discharged to 1 V, by resistor R103, the application attempts to restart with a Soft Start period. The application can also resume operation with a VCC reset if the LLC controller VCC drops prior to the C56 discharging down to 1 V. The fault timer duration is too long to protect the application against damage due to a short circuit on the http://onsemi.com 6 AND8460/D current flows through the resonant capacitor and creates an ac voltage VCs_ac that is given by Equation 2. secondary side (output terminals short or secondary transformer winding short). To protect against this possibility, there is a second OCP comparator monitoring the fault pin voltage. When the frequency shift (via Soft Stat pin and resistors R97, R100) is no longer sufficient to keep the primary current limited, the resonant capacitor voltage increases up to such a level that the fault input voltage reaches the Vref_OCP threshold (1.55 V). The application then latches off and protects the power stage components from damage. The circuit remains latched until the VCC is cycled down below VCC_reset and then back above the VCC_on threshold. The primary current level that will activate the overload protection is given by the maximum secondary current transformed to the primary side and also by the transformer magnetizing current. The RMS value of primary current can be approximately calculated using Equation 1. I Primary_rms [ [ Ǹǒ 1 8 I 2out_max @ p 2 @ G nom 2 ) V bulk_nom 2 V Cs_ac + + I Primary_rms 2 @ p @ f op_ovld @ C s 2 @ 3.14 @ 78 @ 10 3 @ 30 @ 10 −9 Ǔ Rs + Ǹ V Cs_peak I f_limit + 1 @ 10 3 20 @ 10 −3 1 V + 50 kW (eq. 3) Where: Rs− Is the total series resistance to be used (R42+R52) VCs_peak − is the peak resonant capacitor voltage If_limit – is the maximum forward current of D14, D15 The final application uses a series resistance of Rs = R42 + R52 = 48 kW. The load resistance of 1 kW (R60) has been implemented to assure good noise immunity on the Fault input. When the fault input voltage has reached the 1.04 V threshold, the 1st fault comparator is activated. The filtering capacitor C28 needs to be low capacitance to assure fast OCP system response. However, this means there will be a ripple present in the fault input voltage. To avoid any issues, the average output voltage of the OCP sensing network has been selected at least 10% below the 1st fault comparator threshold (VOCP_sense out = 0.9 * VRef_fault). Additional series resistor R64 allows fine overload threshold adjustment if needed. The charge pump capacitor value can be calculated using Equation 4. Where: Iout_max − is the maximum output current of the LLC stage (23 A) Gnom – is the nominal LLC stage gain (Gnom = 0.062 − refer to Page 13) Vbulk_nom − is the nominal bulk voltage Lm – is the primary magnetizing inductance (715 mH) fop_ovld − is the operating frequency during overload conditions (78 kHz) The above equation is an accurate approximation for applications operating at resonant frequency. Accuracy decreases for applications operated far below or above series resonant frequency. The most accurate approach is to measure primary RMS current either from simulation or directly in the application. For the application at hand, the primary RMS current level is 1.68 A when output power is 276 W (i.e. 115% of nominal output power). The primary ȧ2 @ ǒ ȧ ȧ + 114 Vac Where: Cs − is the resonant capacitor value i.e. C7+C18 The DC offset, that is present on the resonant capacitor, is not transferred to the Fault pin as the charge pump cannot handle DC voltages. A critical failure (like short circuit) can cause the resonant capacitor voltage to swing above the nominal bulk voltage. High peak current can then flow through the charge pump diodes D14, D15. The series resistors R42, R52 limit the charge pump diode current to a safe level. The total series resistance can be approximately calculated using Equation 3. (eq. 1) 2 @ p @ f op_ovld @ (eq. 2) 1.68 24 @ L m 2 @ f op_ovld 2 C 29 + + Cs_ac p@V @R 60 @0.9 ref_faul Where: VRef_fault – is the 1st fault comparator threshold voltage A charge pump capacitor with standard value (C29 = 220 pF) is used in the final application. As aforementioned, the filtering capacitor C28 affects the OCP system response time and precision. The filtering capacitance should be selected in such a way that the time constant R60 − C28 is at least 5 times higher than the operating period of the converter (Equation 5). * ǒR60)R64Ǔ 2 C 28 + Ǔ + 214.6 pF 2 * ǒR 42 ) R 52Ǔ 5 f op_ovid @ R 60 + 2 (eq. 4) 5 78 @ 10 3 @ 1000 [ 68 nF (eq. 5) The total power loss generated in the series combination of resistors R42, R52 needs to be verified (Equation 6). P Rs + http://onsemi.com 7 ǒ Ǔ p @ V ref_fault @ 0.9 Ǹ2 @ R 60 2 @ R s + 0.208 W (eq. 6) AND8460/D = 1 mF, in combination with R100 resistor provide output voltage ramp−up time of 18 ms. During an overload condition, the fault timer is activated to turn−off the application after a programmed time period. This technique prevents the SMPS from thermal damage. If the overload condition disappears before the timer expires, the controller doesn’t interrupt operation. The fault timer duration is given by capacitor C56, resistor R103 and Ctimer pin charging current Itimer1. The fault timer capacitor charging time can be calculated using Equation 10. The charging period should be selected such that there is enough margin for the Soft−Start period and transient overloading. A fault period of 100 ms has been used in this design. As already mentioned, the first fault comparator threshold is reached when the overload conditions occur. The Soft−Stat capacitor discharge switch is activated and the operating frequency of the converter is automatically increased, limiting the primary current. The series resistor R97 = 5.6 kW is used on the Soft−Start input to overcome erratic oscillations during transition between normal and overload operating modes. This resistor also decreases the maximum operating frequency during the overload conditions to 150 kHz. A startup frequency of 200 kHz has been chosen for this design to limit the primary current during the Soft−Start phase. The startup frequency is given by the total current sourced from the Rt pin during startup. When the application starts up both the PFC and LLC controllers reach operating VCC voltage. The LLC controller is disabled via brownout input until the PFC stage output reaches regulation level. The Soft Start capacitor discharge switch is active during this time period as well as the Rt pin reference voltage source. The soft start capacitor thus charges to the voltage that is given by the Rt pin reference voltage (2.3 V) and resistor divider composed of resistors R97, R100. The Soft−Start capacitor initial voltage can be calculated using Equation 7. V SS_start + 2.3 @ R 97 R 97 ) R 100 + 5.6 + 1.1 V 5.6 ) 6.2 ǒ T fault + −R 103 @ C 56 @ ln 1 * R 104 @ ǒR 97 ) R 100Ǔ R 104 ) R 97 ) R 100 ǒ + 6.2 kW R 104 * R Rt_start (eq. 10) 4 Ǔ+ 150 @ 10 3 @ 175 @ 10 −6 Where: Vtimer(on) − is the fault timer upper threshold Itimer1 − is the timer pin charging current The off−time period of the fault timer is given by Equation 11 when the LLC controller VCC stays at sufficient level (i.e. above VCC_off). (eq. 7) ǒ T off + R 103 @ C 56 @ ln V timer(on) Ǔ V timer(off) + (eq. 11) ǒǓ 4 + 977 ms + 150 @ 10 3 @ 4.7 @ 10 −6 @ ln 1 Where: Vtimer(off) − is the fault timer lower threshold The recovery time should be selected with respect to the thermal stress of the power stage components. The timer duration is determined by the VCC capacitor discharge time in this design. This is because the primary controller supply voltage naturally drops when the LLC stage is turned−off. In this application, the SMPS recovery time is 1.8 s. The PCB design features options for over current protection diodes D6, D9. Protection diodes, when implemented, limit the maximum resonant capacitor voltage excursion to Vbulk level. The primary current is thus naturally limited to a safe level. The use of protection diodes when making changes to the demoboard circuitry is recommended. The OCP diodes can be removed again after the modified system is verified to be working correctly. (eq. 8) R Rt_start @ R 104 ) R Rt_start @ R 97 * R 97 @ R 104 + + 117 ms For a 200 kHz startup frequency, a RRt_star value of 8.47 kW is required (refer to the NCP1397A/B datasheet − fop vs. RRt chart). The value of resistor R100 can be calculated by rearranging Equation 8 to Equation 9. R 100 + Ǔ R 103 @ I timer1 + −150 @ 10 3 @ 4.7 @ 10 −6 @ ln 1 * The internal resistance of the Soft start switch can be neglected as it’s value is small at 100 W. When the LLC controller reaches operating VCC prior to the BO_OK signal, the startup frequency can be calculated using the serial and parallel combination of resistors R97, R100 and R104. The total Rt pin resistance during Soft−Start is calculated using Equation 8. R Rt_start + V timer(on) + (eq. 9) The Soft−Start capacitor value is given by the required output voltage ramp−up time. The Soft−Start capacitor, C55 http://onsemi.com 8 AND8460/D LLC Power Stage Secondary Side Figure 7. The LLC Secondary Side Schematic sense input monitors the SR MOSFET drain voltage to determine when to turn on and off the SR MOSFET. The NCP4303 driver is connected directly to the SR MOSFET without any external gate resistor in order to minimize turn−off delay. No ringing or EMI issues related to driver current occur assuming a proper layout is used i.e. driver circuitry loop area is minimized. The power losses related to the SR MOSFET gate driving can be calculated using Equation 12. The secondary side uses synchronous rectification with a center tapped transformer configuration in order to provide high efficiency full wave rectification (Figure 7). The SR MOSFETs Q2, Q9 are connected in series with secondary windings W2, W3, inductors L1, L8, filtering capacitor bank C8−C11, C21−C24. Standard TO−220 package SR MOSFETs have been selected for the application because they reduce manufacturing costs. However, the parasitic inductances of the SR MOSFET package create an error voltage that increases the turn off current threshold. The shift in turn off threshold results in a less than optimal conduction period, reducing the efficiency. In order to avoid this unwanted shift, the NCP4303 features a package parasitic inductance compensation technique. The technique requires the use of a small compensation inductance (L1, L8). The secondary current creates a voltage on the compensation inductance and dynamically offsets the ZCD comparator threshold via the COMP input. This method assures maximum conduction time of the SR MOSFET and therefore increases efficiency. The compensation inductor is formed by a square loop of copper wire with diameter of f = 1.2 mm (refer to Figure 66). The compensation inductance value is approximately 4 nH. SR controllers IC1, IC2 are powered from the application output. Resistors R10, R32 together with decoupling capacitors C5, C6, C19 and C20 form RC filters to smooth current spikes created during SR driver turn−on. The current P DRV + V CC @ V clamp @ C g_ZVS @ f sw_max (eq. 12) Where: VCC − is the NCP4303 supply voltage (Vout in this case) Vclamp − is the driver clamp voltage Cg_ZVS − is the gate to source capacitance of the SR MOSFET in ZVS mode fsw_max − is the maximum switching frequency of the application The SR MOSFET conduction losses can be calculated from the secondary RMS current and channel resistance for a given gate voltage (Equation 13). ǒ Ǔ p P COND + I out @ 4 Where: Iout − is the output current http://onsemi.com 9 2 @ R DS(on)@Vgs_clamp (eq. 13) AND8460/D resistance (1.55 W) Rdrv_high_eq − is the SR driver high side switch equivalent resistance (7 W) Rg_int − is the internal gate resistance of the SR MOSFET Power losses related to the SR controller internal consumption are given by Equation 16. RDS(on) @ Vgs_clamp − is the SR MOSFET channel resistance for the given driver voltage clamp level The body diode conduction time and related losses can be significantly reduced due to the NCP4303 compensation capability. If the body diode losses are neglected, the total losses of the SR system can be approximated by summing the driving and conduction losses and then multiplying by the number of SR MOSFETs (Equation 14). P SR + 2 @ ǒP COND ) P DRVǓ P ICC + V CC @ I CC + 35 mW Where: ICC − is the NCP4303 driver supply current for Cload = 0 nF and maximum operating frequency (refer to the NCP4303 datasheet for the ICC versus fop chart) The DIE temperature is given by the thermal resistance from junction to ambient, total power dissipation of the SR controller, and ambient temperature (Equation 17). (eq. 14) The SR MOSFET selection has been made with both cost and efficiency considerations. Another important step is selecting which NCP4303 driver clamp version to use (6 V or 12 V). The choice can be made using the above equations. The theoretical power losses calculated for a SR system using IRFB3206 MOSFETs and two different gate driver clamp voltages can be seen in Figure 8. Vclamp= 6 V 1.6 Total SR MOSFETs power losses (conduction+driving) [W] ǒ Ǔ T DIE + P DRV_IC ) P ICC @ R qJA ) T A + (eq. 17) + (0.076 ) 0.035) @ 180 ) 60 + 80° C 1.8 Vclamp= 12 V Where: RqJA − is the IC thermal resistance from junction to ambient TA – is the ambient temperature (worst case when the board is fully loaded) High DIE temperature could appear in applications with high operating frequencies. Additional copper heat sinking in the PCB or a thermal conductor between the SR controller and SMPS package should be used to maintain DIE temperature below the maximum ratings. The snubber networks R8, R9, R40, R41, C4 and C25 dampen the voltage ringing that occurs on the SR MOSFET drain when the secondary winding voltage reverses. The ringing frequency is given by the secondary leakage inductance Lsec,leak and output capacitance Coss of the SR MOSFET. The snubber resistance should be equal to the characteristic impedance of the ringing circuitry in order to effectively dampen the oscillations Reference 9, (Equation 18). 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 5 10 15 20 Output current [A] Figure 8. Theoretical Losses of the IRFB3206 SR MOSFET as a Function of Output Current Figure 8 shows that theoretically calculated losses increase for output current lower than 14 A when 12 V gate driver clamp is used. The maximum efficiency requirement is specified at 50% of full load by the 80 PLUS® program. Therefore the NCP4303B (6 V gate drive clamp) has been selected due to it’s improved efficiency at light to medium load. The power dissipation within the IC package needs to be considered in order to avoid overheating issues. Losses related to the driving of the SR MOSFET gate can be calculated using Equation 15. P DRV_IC + @ (eq. 16) ǒ 1 @ C g_ZVS @ V clamp 2 @ f SW @ 2 R drv_low_eq Ǔ R drv_low_eq ) R g_int ǒ R snubber + L sec,leak C OSS (eq. 18) Where: Rsnubber − is the snubber resistance Lsec,leak − is the secondary leakage inductance Coss−is the SR MOSFET output capacitance The snubber capacitance Csnubber must be larger than the SR MOSFET output capacitance, but small enough to minimize dissipation in the snubber resistor. The snubber capacitance is generally chosen to be at least 3 to 4 times higher than the value of the parasitic resonant capacitor. (eq. 15) ) C g_ZVS @ V clamp @ f SW @ C snubber + 3 ³ 4 @ C OSS Ǔ 1 @ V CC * V clamp ) @ C g_ZVS @ V clamp 2 @ 2 R drv_high_eq @ f SW @ + 76 mW R drv_high_eq ) R g_int ǒ Ǹ (eq. 19) The NCP4303 minimum on time and off time generators protect against unwanted switching that could be triggered by ringing on the ZCD comparator. Resistors R11, R39 set the minimum on time period. The minimum on time period is selected based on the maximum operating frequency of the LLC stage as well as the secondary current waveform. Ǔ Where: Rdrv_low_eq − is the SR driver low side switch equivalent http://onsemi.com 10 AND8460/D the SR MOSFETs and turning the SR system into sleep mode during light load. The demoboard provides a control input that can be used for this purpose. The external SR standby on/off circuitry can be implemented by monitoring output current. It is critical to assure correct layout of the SR system to avoid issues with the zero current detection circuitry. Please refer to the NCP4303 datasheet for layout considerations and more information on how the ZCD and the compensation systems work. The secondary filtering capacitor bank RMS current during full load series resonant frequency operation can be calculated using Equation 22. During light load conditions, the secondary current oscillation can cause unwanted SR MOSFET switching. A minimum on time of 1.1 ms is needed to prevent this behavior. The required value of min Ton adjust resistors can be calculated using Equation 20. R T_on_min + + T on_min * 4.66 @ 10 −8 9.82 @ 10 −11 1.1 @ 10 −6 * 4.66 @ 10 −8 9.82 @ 10 −11 + (eq. 20) [ 11 kW Where: RT_on_min −is the minimum on time adjust resistor The minimum off time period is given by resistors R7, R37. To prevent issues when the application operates at minimum frequency, the minimum off time should be set to as long as possible. However, the minimum off time value is limited by the maximum operating frequency clamp. In our case, the minimum switching period of the LLC stage is 9.1 ms. Thus the minimum off time period is selected to be 3.9 ms in order to provide a long minimum off time with some margin for the minimum switching period. The minimum off time adjust resistor value can by calculated using Equation 21. R T_off_min + + T off_min * 5.4 @ 10 −8 9.56 @ 10 −11 3.9 @ 10 −6 * 5.4 @ 10 −8 9.56 @ 10 −11 I Cf_RMS + I out_nom @ Ǹp8 * 1 + 20 @ 0.483 + 9.7 A (eq. 22) 2 Where: Iout_nom – is the nominal output current Filtering capacitors must be used in parallel to handle the total RMS current. Low impedance type capacitors have been used in this design. The total equivalent series resistance (ESR) of the capacitor bank is 2.25 mW. The output voltage ripple related to the filtering capacitor bank is composed from two components: 1st the ESR related ripple (Equation 23) and 2nd the ripple related to the capacitor bank capacitance (Equation 24). + (eq. 21) V Cf_ripple_pk*pk + ESR @ I rect_peak + 2.2 @ 10 −3 @ [ 39 kW @ Where: Rt_off_min −is the minimum off time adjust resistor If the LLC converter uses a very wide operating frequency range, it is beneficial to modulate the minimum off time period. The modulation is possible using a resistor connected from the SR MOSFET drain to the opposite SR controller min Toff pin. When the drain voltage is at a high level, current is injected into the min Toff pin. The internal capacitance charging current is thus decreased and the minimum off time period increases. Please refer to the NCP4303 datasheet for more information on how to modulate the minimum off time period. The NCP4303 features a trigger input that can be used to implement synchronous rectification systems in CCM applications. Additionally, the trigger input can be used to disable the IC and activate a low consumption standby mode. The demoboard layout features optional circuitry (refer to complete schematic − page 31) that allows the customer to implement a primary triggering signal. Normally this is not need in LLC applications as the NCP4303 features a low propagation delay from the CS input to the DRV output. The trigger circuitry option is implemented to allow the customer to test the trigger input functionality. The no load consumption of the application can be reduced by implementing parallel Schottky diodes across p @ 20 + 69 mV 2 (eq. 23) Where: Irect_peak – is the peak current through the secondary V out_ripple_cap_pk*pk + @ ǒ p * 2Ǔ + I out_nom 2 @ Ǹ3 @ p @ f op_nom @ C f 20 2 @ Ǹ3 @ 80 @ 10 3 @ 8 @ 10 −3 @ (eq. 24) @ ǒ p * 2Ǔ + 10 mV Where: fop_nom – is the nominal operating frequency Cf – is the total capacitance of the capacitor bank The capacitive component of the output ripple is negligible in this case because of the total filtering capacitance value. The power losses that are created by the filtering capacitor bank ESR can be calculated using Equation 25. P Cf_ESR + + ǒ I out_nom @ ǒ Ǹ 20 @ Ǹp8 * 1Ǔ 2 Ǔ p2 *1 8 2 @ ESR + (eq. 25) 2 @ 2.25 @ 10 −3 + 0.21 mW The PCB secondary side layout can significantly affect current distribution among the filtering capacitors. Ideally, the secondary layout should result in an equal distribution of http://onsemi.com 11 AND8460/D filtering capacitor connection series parasitic impedances (refer to Figure 9). If mismatched, capacitors with lower series impedance within the bank handle a higher current, which results in decreased life time. 120 40 30 80 40 10 0 0 −10 Phase [o] Gain [dB] 20 −40 −20 −80 −30 −40 100 1000 −120 10000 Frequency [Hz] Gain (dB) Phase (Degree) Figure 10. Closed Loop Gain and Phase of the LLC Power Stage for Nominal Output Current As previously mentioned, the secondary RMS currents are quite high in this application. Parasitic layout resistances can thus affect the LLC stage efficiency. A PCB with 70 mm copper plating has been used for this demo board to minimize power losses related to the secondary side layout. Figure 9. Ideal Configuration of the Capacitor Bank The capacitor bank provides the bulk of filtering for the secondary currents, but it does not fully filter out narrow glitches produced when the secondary winding reverses. Thus an additional LC filter (L2, C12) has been implemented. The resonant frequency of this filter should be as low as possible but on the other hand it can affect system loop gain if selected too close to the crossover frequency. A resonant frequency of 24 kHz has been selected for this design. The filter inductor of 200 nH features a low DC resistance, which helps keep efficiency high at medium and full load conditions. A filtering capacitor C12 of 220 uF (low impedance type) has been implemented. The filter provides higher peaking around the resonant frequency when a low ESR capacitor is used. On the other hand, if a capacitor with too high of ESR is used, the output voltage drop during fast transient loading increases. The additional LC filter also reduces output voltage ripple at nominal operating frequency and full load conditions by −10 dB. The output voltage regulation is assured by IC4. Divider R89, R98 and R99 provides the regulator IC with output voltage information. Resistor R85 limits the maximum current that can pass through optocoupler OK1. Resistor R90 bypasses the optocoupler and provides a bias path for IC4. The compensation network is composed of resistor R95 and capacitors C49, C51. Please refer to application note AND8327/D to learn how to calculate the compensation network. The Bode plot of the full loaded LLC stage is shown in Figure 10. Resonant tank and transformer design: An LLC transformer from Pulse engineering has been selected for this design. This transformer offers extra high leakage inductance thanks to a special bobbin arrangement (see demo board photo in Figure 63). The transformer leakage inductance is used as a resonant inductance. This solution eliminates the need for an additional resonant inductor, reducing the overall application cost. On the other hand, a transformer with high leakage inductance causes a stronger proximity effect in the windings, resulting in increased requirements for the winding construction. Another disadvantage of the leaky transformer is high stray flux that negatively impacts the radiated EMI emission. Significant eddy currents can be induced by stray flux in the surrounding metal parts. Therefore it is important to not place these parts too close to the transformer. The transformer is designed in such a way that the LLC stage is operated in, or very close to, the series resonant frequency (fs) for full load conditions and nominal bulk voltage. Efficiency is optimized for these operating conditions. The LLC stage operating frequency is increased up to 110 kHz to maintain output voltage regulation when the load diminishes. When the output load drops further down below 1.4 A, the maximum operating frequency clamp is reached and the application enters skip mode operation to reduce the LLC stage power losses. On the other http://onsemi.com 12 AND8460/D hand, when the bulk voltage drops, the secondary regulator decreases the LLC stage operating frequency down to 65 kHz to achieve the necessary gain for output voltage regulation. First harmonic approximation (FHA, refer to References 7 or 11) is a common method for resonant converter analysis. In the actual application, the resonant tank is driven by a square wave voltage. However, FHA modeling does not use a square wave drive. Instead, an equivalent load resistance is used for FHA analysis to compensate for the difference (Equation 26): R ac + 8 p2 @ V out I out_nom @ h + 0.51 The resonant tank characteristic impedance (Equation 30) and quality factor (Equation 31) affect the operating frequency range requirement for output voltage regulation. Z0 + Q+ The LLC converter behaves like a frequency dependent divider i.e. the power stage gain can be modified by changing the operating frequency. The LLC stage gain needed for output voltage regulation under full load conditions and selected bulk voltage range (350 Vdc – 425 Vdc) can be calculated based on Equations 27 – 29. G nom + G max + ǒ Ǔ V bulk_max ǒ + Ǔ 2 @ V out ) V f_SR V bulk_nom ǒ Ǔ 2 @ V out ) V f_SR V bulk_min 2 @ (12 ) 0.2) + + 425 395 2 @ (12 ) 0.2) 350 n 2 @ R ac (eq. 31) Z0 I Cs_RMS_nom [ I sec_RMS_nom @ G nom [ [ [ p @ I out_nom @ G nom [ 2 @ Ǹ2 p 2 @ Ǹ2 (eq. 32) @ 20 @ 0.062 [ 1.38 A Where: Iout_nom_ – is the nominal output current The above calculation does not include magnetizing current because it has only a minor impact. The resonant capacitor capacitance can now be calculated based on the selected capacitor peak voltage (Equation 33). + 0.057 (eq. 27) 2 @ (12 ) 0.2) (eq. 30) The lower the resonant capacitor value, the higher the resonant inductance needs to be in order to assure nominal operating frequency. A higher resonant inductance value generally results in a more narrow operating frequency range throughout the line and load conditions. It is always beneficial to keep a narrow operating frequency range to optimize efficiency and EMI performance Based on the above considerations, it is evident that the resonant tank with minimized resonant capacitance provides optimum performance. However, the resonant capacitor voltage can reach unacceptable levels if the resonant capacitance value is too low. It is beneficial to limit the resonant capacitor voltage excursion to a level that is below nominal bulk voltage level. There are three main reasons for this consideration: 1st the lower voltage ratings for the resonant capacitor 2nd less voltage stress for the PCB 3rd simple OCP circuitry can be implemented using clamping diodes (D6 and D9 options in demoboard PCB). The nominal resonant capacitor RMS current can be approximated using Equation 32. (eq. 26) Figure 11. Equivalent Schematic for FHA Analysis 2 @ V out ) V f_SR Ls Cs Where: Ls – is the resonant inductor value Cs − is the resonant capacitor value Where: Rac – is the equivalent load resistance for the FHA model h − is expected efficiency of the LLC stage (94.5%) The FHA equivalent schematic of an LLC stage with external resonant inductor Ls and standard transformer with magnetizing inductance Lm and negligible leakage inductance can be seen in Figure 11. G min + Ǹ + 0.0618 (eq. 28) Cs + + 0.0697 (eq. 29) I Cs_RMS_nom @ Ǹ2 ǒ V 2 @ p @ f op_nom @ V Cs_peak_nom * Where: Vf_SR – is the expected average drop of the SR rectifier including the secondary layout drop Vbulk_max – is the maximum operating bulk voltage Vbulk_nom – is the nominal operating bulk voltage Vbulk_min – is the minimum operating bulk voltage + 1.38 @ Ǹ2 2 @ p @ 80 @ 10 3 @ ǒ320 * 395Ǔ 2 http://onsemi.com 13 Ǔ + bulk_nom 2 + 31.6 nF (eq. 33) AND8460/D current results in higher losses generated in the transformer and primary MOSFETs. The magnetizing to resonant inductance ratio of k = Lm / Ls = 5.5 has been chosen for this design as a compromise between losses generation and LLC stage operating frequency range. Magnetizing inductance can be calculated using Equation 36. Where: VCs_peak_nom – is the resonant capacitor peak voltage under nominal load and bulk voltage conditions Practically there are two possible choices for implementing the resonant capacitor: a) one resonant capacitor of 33 nF b) two resonant capacitors of 15 nF Variant b) has been selected for this design i.e. two 15 nF capacitors (C7 and C18 in Figure 6). The advantage of this solution is that the primary current divides equally between two capacitors and the bulk capacitor ripple current is reduced by 30%. The resonant inductance value can be calculated from the selected nominal operating frequency using rearranged Thompson law (Equation 34). A nominal operating frequency of 80 kHz was selected for this application. Ls + + 1 C s @ ǒ2 @ p @ f sǓ 2 L m + k @ L s + 5.5 @ 130 @ 10 −6 + 715 mH Where: k – is the ratio between magnetizing and resonant inductance All of the above calculations have been performed with the expectation that the application will operate at the series resonant frequency for nominal load (20 A) and bulk voltage (395 Vdc). The nominal gain of an LLC converter, that features external resonant inductance Ls, a transformer with negligible leakage inductance (Llk ³ 0), and primary inductance Lprimary = Lm, is equal to the inverse of the transformer turns ratio when operated at series resonant frequency (Equation 37). + (eq. 34) 1 30 @ 10 −9 @ ǒ2 @ p @ 80 @ 10 3Ǔ 2 + 131.9 mH [ 130 mH G nom + Where: fs – is the series resonant frequency (fs = fop_nom in our case) The magnetizing inductance of the future transformer should be selected with respect to the LLC stage operating frequency range. The operating frequency range is reduced when a high magnetizing inductance value is used. On the other hand, the maximum gain of the LLC stage is reduced and the magnetizing current is not sufficient to overcharge the total bridge capacitance and maintain a ZVS condition when the magnetizing inductance value is too high. The maximum magnetizing inductance value that will still assure ZVS during no load conditions can be calculated based on the selected deadtime period, maximum operating frequency and total bridge capacitance (Equation 35). The bridge capacitance is composed of the primary MOSFETs output capacitances and the primary layout parasitic capacitance. L m_max + + DT 8 @ f op_max @ C HB_total + 8 @ 110 @ 10 3 @ 360 @ 10 −12 1 n discrete + Ǹ 2 @ (12 ) 0.2) 395 L secondary L primary + ǒ Ǔ 2 @ V out ) V f V bulk_nom + (eq. 37) + 0.0618 Where: Lprimary – is the primary inductance measured with secondary winding opened Lsecondary – is the secondary inductance measured with primary winding opened ndiscrete – is the transformer turns ratio for the LLC design with external resonant coil Required secondary inductance can then be calculated using Equation 38. L secondary + L primary @ G nom 2 + 715 @ 10 −6 @ 0.0618 2 + (eq. 38) + 2.73 mH A simulation model can be built to verify the full load gain characteristic of the proposed LLC design with external resonant inductor (Figure 12). A transformer with high coupling coefficient is expected => coupling ³ 1. + 350 @ 10 −9 (eq. 36) (eq. 35) + 1.1 mH Where: DT –is the selected deadtime period (350 ns for this design) Fop_max –is the maximum operating frequency CHB_total_–is the total bridge parasitic capacitance (2 * Coss + Clayout) The primary RMS current increases if too low of magnetizing inductance value is used. Increased RMS Figure 12. Simulation Model for the LLC Stage with External Resonant Inductance http://onsemi.com 14 AND8460/D 80mV Gmax=69.767m @ fop=56.1kHz x Gnon=61.826m @ fop=80.3kHz Gmin=57.081m @ fop=99.2kHz x 60mV x 40mV 20mV 0V 10KHz V(Out_Lext+ideal_Tr) 30KHz 100KHz 300KHz 1.0MHz Frequency Figure 13. Simulated Gain Characteristic for the LLC Stage Design with External Resonant Inductance, Full Load Conditions solution. The gain of the LLC design with integrated resonant tank, that uses transformer with primary inductance Lprimay = Lm, leakage inductance Llk_primary = Ls and secondary to primary turns ratio ndisc, is thus higher than the inversed turns ratio for the discrete solution when operated at series resonant frequency (Equation 39). The simulated full load gain characteristic in Figure 13 shows that the proposed design will work in series resonant frequency for full load and nominal bulk voltage conditions. The difference between the LLC design with external resonant inductance and the design that uses a transformer with high leakage inductance can be determined with simulations. The integrated resonant tank gain differs from the inversed transformer turns ratio when operated in series resonant frequency. This phenomenon is related to the fact that the leakage inductance is physically not located in series with the primary winding like in the external resonant coil G nom_integrated u 1 n discrete (eq. 39) Figure 14 shows the simulated gain characteristics comparison for both solutions. 80mV Gb=68.4m @ fop=80.3kHz x 60mV Ga= 61.8m @ fop= 80.3kHz x 40mV 20mV Ga − gain when external Ls solution is used Gb − gain when transformer with leakage is udes 0V 10KHz 30KHz V(Out_Lext+ideal_Tr)V(Out_Tr_with_leakage) 100KHz 300KHz 1.0MHz Frequency Figure 14. Simulated Gain Characteristics − Comparison Between Resonant Tanks with External Resonant Inductance and with Leakage Resonant Inductance. Both Designs Feature the Same Secondary to Primary Transformer Ratio ndiscrete. The primary to secondary turns ratio has to be increased by coupling coefficient to assure the same nominal gains at series resonant frequency for both LLC resonant tank solutions. The new turns ratio of the design with integrated leakage inductance is defined by Equation 40. n integrated + n discrete Ǹ 1* http://onsemi.com 15 Ls Lm + 16.18 Ǹ1 * 130 715 + 17.88 (eq. 40) AND8460/D Where: Ls = Llk_primary – is the primary inductance measured with secondary winding shorted Lm = Lprimary – is the primary inductance measured with secondary winding opened A SPICE model of the modified integrated resonant tank can be seen in Figure 15. Figure 15. Simulation Model of the LLC Stage with Integrated Resonant Tank and Modified Turns Ratio nintegrated 80mV Gnom=61.8m @ fop=80.3kHz 60mV 40mV 20mV 0V 10KHz 30KHz V(Out_Tr_with_leakage) V(Out_Lext+ideal_Tr) 100KHz 300KHz 1.0MHz Frequency Figure 16. Simulated Characteristics − Comparison Between Resonant Tanks with External Resonant Inductance and with Leakage Resonant Inductance and Modified Turns Ratio. Lprimary = 715 mH Lsecondary = Lprimary/nintegrated2 = 2.23 mH Llk_primary = 130 mH when secondary winding is shorted The transient simulation results for the proposed LLC resonant tank design are shown in Figure 17. Bulk voltage of 395 Vdc and output load of 20 A have been applied during this simulation. The results show that the output voltage is regulated to the target level i.e. 12 Vdc when the application works at a frequency of 80.3 kHz, which meets the target resonant frequency (80 kHz). Simulation results from Figure 16 show that the nominal gains for both solutions are the same when the operating frequency is equal to the resonant frequency. The modified integrated resonant tank solution also provides higher gain below series resonant frequency. This is beneficial as the operating frequency range will be reduced compared to the LLC design with external resonant coil. The calculated resonant tank components are as follows: Resonant capacitor: Cs = 2 x 15 nF Transformer with divided bobbin: http://onsemi.com 16 AND8460/D Iprimary_pk=2.16 A 2.0 Vout= 12V 0 Vbulk=395 Vdc Iload=20 A −2.0 1.7965ms 1.8000ms 1.8040ms 1.8080ms I(R64) V(out_int)/10 1.8120ms 1.8160ms 1.8200ms 1.8226ms Time Figure 17. Transient Simulation for Proposed Resonant Tank Design The number of primary turns needs to be calculated with respect to the transformer flux density excursion. Maximum flux density will be reached for the minimum operating frequency and maximum bulk voltage (Equation 41). Np + + V bulk*max 8 @ DB max @ f SWmin @ A e A ferrite core with air gap on the center leg has to be used to allow for primary inductance adjustment. The air gap stores most of the magnetizing energy related to the primary winding. Thus it is beneficial to place the air gap below the primary winding to minimize additional stray flux and reduce the proximity effect. The air gap position within the bobbin affects primary and secondary inductance values. Generally, the inductance of an inductor with gapped ferrite core is lower when the gap is located below the coil winding rather than outside of the winding. The difference between both cases is due to the magnetic flux bulging out from the gap and coil. When the air gap is not located under the coil winding there will be higher stray flux – refer to Figure 18. + 420 8 @ 0.125 @ 67 @ 10 3 @ 167 @ 10 −6 [ 38 turns (eq. 41) Where: Bmax – is the selected peak flux density Fsw_min – is the minimum operating frequency clamp Ae – is the effective area of the ferrite core center leg cross section Ferrite core Air gap Ferrite core Winding Air gap Winding Figure 18. Inductor Inductance and Stray Flux Dependency on the Air Gap Position shielded by the primary winding only. The magnetic conductivity of the primary winding Lprimary is thus lower than the magnetic conductivity for the secondary winding Lsecondary (Equations 42 − 44). A similar situation occurs in the transformer with divided bobbin and air gap located below the primary winding – Figure 19. There is only one ferrite core but it does not feature the same magnetic conductivity (permanence) for the primary and secondary windings! This is because the air gap is http://onsemi.com 17 AND8460/D Secondary winding Primary winding Ferrite core Ns + Air gap L primary Np 2 L secondary L secondary + Ns 2 L primary t L secondary (eq. 42) (eq. 43) (eq. 44) Due to this core non−homogeneity, the physical turns ratio (N) is not equal to the electrical turns (n) ratio that is given by the primary and secondary inductances (Equation 45). Np Ns 0 Ǹ L primary L secondary N aux + (eq. 45) + + Ǹ 1 @ 8 ǒ I out_nom 2 @ p 2 @ G nom 2 ) Ǹǒ 1 @ 8 20 2 @ p 2 @ 0.0618 2 ) V bulk_nom 2 V aux ) V f_daux V out ) V f_SR Ǔ 24 @ L m 2 @ f op_nom 2 + 395 2 2 24 @ ǒ715 @ 10 −6Ǔ @ ǒ80 @ 10 3Ǔ (eq. 46) @ Ns + 18 ) 0.7 @ 2 + 3 turns 12 ) 0.2 (eq. 47) (eq. 48) Ǔ 2 + 1.46 A frequency. The skin depth for copper wire can be calculated based on Equation 50. The secondary winding RMS current for operation in resonant frequency and full load conditions is the same as the secondary rectifier current (Equation 49). p p I sec_RMS + I out_nom @ + 20 @ + 15.7 A 4 4 A L_secondary Where: Vaux – is the target auxiliary voltage Vf_daux – is the forward voltage drop of the diode used in the auxiliary VCC path Vf_SR – is the forward voltage drop of the SR system including layout dropouts The primary winding RMS current can be calculated using Equation 48. Where: Np – is the primary winding turns number Ns – is the secondary winding turns number The number of the secondary winding turns can be calculated based on the magnetic conductivity for the secondary winding and the required secondary inductance (Equation 46). I primary_RMS_nom + L secondary The air gap position also affects the total transformer leakage inductance, which needs to be adjusted to the required value. The primary and secondary magnetic conductivities calculation and the total transformer stray flux calculation are not a simple task for a transformer with divided bobbin. Finite Element numerical Methods (FEM) with a precisely prepared model need to be used. Often the “cut−and−try” method is used during the transformer prototype design. Finally, the secondary winding composed from two turns (Ns = 2) of copper strip has been used in this LLC transformer design to reach the required secondary inductance. The auxiliary winding is used to power the SMPS primary controllers during normal and no load operating conditions. The auxiliary voltage of 18 V needs to be used for nominal operating conditions to assure a sufficient VCC level when the board is not loaded. The coupling coefficient between auxiliary and secondary windings has to be as high as possible to assure proper auxiliary voltage regulation. Thus it is beneficial to locate the auxiliary winding directly above the secondary windings. The safety requirements then push for triple insulated wire. The required number of turns for the auxiliary winding can be calculated using Equation 47. Figure 19. Transformer with Divided Bobbin and Air Gap Below Primary Winding L primary + Ǹ d+ (eq. 49) The LLC transformer skin effect needs to be considered during windings design for the nominal operating http://onsemi.com 18 65 Ǹf op_nom + 65 Ǹ80 @ 103 + 0.23 mm (eq. 50) AND8460/D The maximum winding wire diameter that will be effectively used by the AC current is then two times higher than the calculated skin depth i.e. f = 0.46 mm. It makes no sense to use wires with higher diameter in primary or secondary windings because current cannot penetrate deeper into the conductor than to the calculated skin depth. As aforementioned, the proximity effect caused by the primary and secondary windings positioning is another limitation in transformers with divided bobbin construction. The winding turns located closer to the opposite winding on the bobbin are affected by the field of other turns from the winding and have the strongest proximity effect. Proximity effect analysis is out of scope of this application note – one can refer to Reference 12 for more information on this subject. After considering the skin effect and proximity effect it is evident that the best solution to winding construction is to use litz wire composed of several insulated conductors with diameter smaller than 0.46 mm. The secondary winding conducts a high RMS current compared to the primary, so it is beneficial to use copper strip lines instead of multiple litz wires. The primary winding has been implemented with litz wire 22xØ0.16. The secondary windings are composed of copper strip lines 8 mm wide and 0.2 mm thick. The auxiliary winding is composed of three turns of triple insulated wire with a diameter of Ø = 0.25 mm. This winding is located directly above the secondary windings to assure good coupling as mentioned above. Some manufacturers specify the leakage inductance under the condition of all secondary windings shorted. This approach cannot be applied for a center tapped secondary side design because only one winding from the pair contributes resonance each switching period half cycle. Figure 20 with Table 2 shows how to measure the leakage inductances of a transformer with center tapped secondary side. Table 2. WINDINGS CONFIGURATIONS DURING MEASUREMENTS OF LEAKAGE INDUCTANCE Parameter Measured Between Pins Secondary Pins Configuration Llk(p−s1) A−B C−D short D−E open Llk(p−s2) A−B C−D open D−E short Llk(total) A−B C−D short D−E short Lprimary A−B C−D open D−E open It is necessary to assure good matching between Llk(p−s1) and Llk(p−s2) leakage inductances otherwise the series resonant frequency would differ in each switching half cycle. As a result, the secondary current through each secondary branch would differ. The secondary current difference would increase losses and temperature in one of the secondary branches. Figure 21 shows the simulated results for a case where the secondary currents leakage inductances imbalance is 5%. 16A 12A 8A 4A 0A 608.00us I(D6) I(D3) 612.00us 616.00us 620.00us 624.00us 628.00us 632.00us 635.45us Time Figure 21. Simulated Secondary Currents for Application with Primary Leakage Inductances Imbalance of 5% Other possible sources of imbalance in the LLC power stage are the secondary layout parasitic inductances. The transformer turns ratio between primary and secondary is quite high for a 12 V output application. When reflected to the resonant tank circuitry, the secondary parasitic inductances are multiplied by the transformer turns ratio squared. This means that even very small secondary layout parasitic inductance asymmetry (like 50 nH) causes a big difference in resonant frequencies for each switching half period. The secondary layout thus needs to be as symmetrical as possible to achieve balanced LLC stage operation. Figure 20. Transformer Primary Leakage Inductance Measurements http://onsemi.com 19 AND8460/D The final transformer specification is summarized in below figures and tables. Figure 22. The Transformer Windings Arrangement Within the Bobbin Figure 23. Transformer Windings Pinout Figure 24. Transformer Winding Directions Table 3. TRANSFORMER PRIMARY INDUCTANCE SPECIFICATION Primary Inductance Between Pins 3 Lp (mH) Tolerance R (mW) Tolerance 715 $10% 101 $15% 5 Table 4. TRANSFORMER LEAKAGE INDUCTANCES SPECIFICATION Primary Inductance LLK (mH) Tolerance Shorted Pins $7% Between Pins 3 5 130.5 9−10−12−13 Between Pins 3 5 131.8 12−13−15−16 Between Pins 3 5 126.8 http://onsemi.com 20 9−10−12−13−15−16 AND8460/D Table 5. TRANSFORMER WINDINGS SPECIFICATION Pin # Winding # Start Turns and Gauge Finish Insulation Tape Turns Wire Gauge Layers (Turns) Winding Method 5 (9 + 9 + 9 + 9 + 2) CW Closed 2 CCW 1 CW Closed W1 3 5 38 UEW+NY LIT Z 0.16Ox22# Grade 2 (NEMA MW80C/IEC 317−21) Thermal Class 155°C W2 9, 10 12, 13 2 Cu Foil W = 8 mm T = 0.2 mm W3 12, 13 15, 16 2 Cu Foil W = 8 mm T = 0.2 mm W4 8 7 3 TIW 0.25O Thermal Class B PCB Design Turns 2 Thickness Width 2 mils 9 mm rectification controller and is not intended as a final design for end customers. The main goal of this document is to introduce a typical application and illustrate how the various features help to decrease total cost and increase SMPS efficiency. Optional features are included in the PCB layout, thus it is easy to update the application according to specific requests. The PCB layout of the LLC stage primary side is not very critical because switching of the main MOSFETs happens only under ZVS conditions and the influence of the PCB parasitic inductances on the operating frequency is negligible. The LLC stage secondary side layout is very critical especially in applications with low output voltages. It is recommended that both paths from the secondary windings to the filtering capacitor bank should be made with the same length. A difference in parasitic inductance between paths results in a different resonant frequency for each half of the switching period. As the secondary RMS current is high, the parasitic resistance of the secondary layout should be minimized. This SMPS is designed on a two layer PCB with 70 mm copper plating. References: 1. NCP4303 data sheet 2. NCP1605 data sheet 3. NCP1397 data sheet 4. Application note AND8257/D 5. Application note AND8327/D 6. Application note AND8281/D 7. Bo Yang − Topology Investigation for Front−End DC−DC Power Conversion for Distributed Power System 8. M. B. Borage, S. R. Tiwari and S. Kotaiah − Design Optimization for an LCL − Type Series Resonant Converter 9. Dr. Ray Ridley − http://www.ridleyengineering.com/snubber.htm 10. ON Semiconductor documentation TND399/D – 216 W All in One SMPS Reference Design 11. M. Jovanovic, “Principle of Resonant Power Conversion”, in−house seminar, Toulouse 2004. 12. Xi Nan, C. R. Sullivan − An Improved Calculation of Proximity−Effect Loss in High−Frequency Windings of Round Conductor Results Please follow the steps detailed in the test procedure for the NCP4303 demo/evaluation board if testing the demoboard performance. Below measurements are shown for further information on how this design operates in practice. Thanks I would like to thank the below companies for providing the samples used in this demoboard. Epcos − http://www.epcos.com Koshin − http://www.koshin.com.hk Pulse − http://www.pulseeng.com Wurth − http://www.we−online.com Coilcraft − http://www.coilcraft.com Conclusion This demoboard shows only one of many possible implementations of the NCP4303A/B synchronous http://onsemi.com 21 AND8460/D Figure 25. Application Input Current Measured for 110 VAC / 60 Hz Input and Full Load Conditions Figure 28. LLC Primary Current and Bridge Voltage for Iload = 10 A Figure 26. Application Input Current Measured for 230 VAC /50 Hz Input and Full Load Conditions Figure 29. LLC Primary Current and Bridge Voltage for Iload = 5 A Figure 27. LLC Primary Current and Bridge Voltage for Iload = 20 A Figure 30. LLC Primary Current and Bridge Voltage for Iload = 2.5 A http://onsemi.com 22 AND8460/D Figure 31. LLC Primary Current and Bridge Voltage for Iload = 0 A, SR is Operating Figure 34. SMPS Response to Transient Loading 20 A to 0 A, 1.6 A/ms Figure 32. LLC Primary Current and Bridge Voltage for Iload = 0 A, SR is Not Operating Figure 35. SMPS response to Transient Loading 2 A to 20 A, 1.6 A/ms Figure 33. SMPS Response to Transient Loading 0 A to 20 A, 1.6 A/ms Figure 36. SMPS Response to Transient Loading 20 A to 2 A, 1.6 A/ms http://onsemi.com 23 AND8460/D Figure 37. SMPS Response to Transient Loading 8 A to 20 A, 1.6 A/ms Figure 40. Bulk Voltage Ripple Image in the Output Voltage Under Full Load Conditions, 110 Vac/60 Hz Figure 38. SMPS Response to Transient Loading 20 A to 8 A, 1.6 A/ms Figure 41. Output Voltage Ripple During No Load Conditions – SR is Turned Off Figure 39. Output Voltage Ripple Under Full Load Conditions Figure 42. Transition From Full Load to Output Short−Circuit http://onsemi.com 24 AND8460/D Figure 43. Transition From No Load Operation to Output Short−Circuit Figure 46. Secondary Side Currents, SR Gate and Vds signals for Iout = 20 A, IRFB3206 Figure 44. SMPS Operation Under Overload Conditions, Restart Time Given by VCC Restart Figure 47. Secondary SR Gate Signals Comparison for Compensated and Uncompensated SR System Iout = 20 A, IRFB3206 Figure 45. Secondary Side Currents and SR Gate Drive Signals for Iout = 2.5 A, IRFB3206 Figure 48. Secondary Side Currents, SR Gate and Vds Signals for Iout = 20 A, IPP015N04N – Uncompensated http://onsemi.com 25 AND8460/D Figure 49. Secondary Side Currents, SR Gate and Vds Signals for Iout = 20 A, IPP015N04N – Compensated 95.0 92.5 Efficiency [%] 90.0 87.5 85.0 82.5 80.0 77.5 75.0 0 5 10 Iout [A] Vin= 110 Vac/60 Hz 15 20 Vin = 230 Vac/ 50Hz Figure 50. Demoboard Efficiency versus Output Current for Compensated SR System and IRFB3206 SR MOSFETs http://onsemi.com 26 AND8460/D 94 Iout = 20 A 93 Efficiency [%] 92 91 90 89 88 90 110 130 150 170 190 210 230 250 270 Input Voltage [Vac] Figure 51. Demoboard Full Load Efficiency versus Input Voltage for Compensated SR System and IRFB3206 SR MOSFETs 1.20 Iout= 0 A Input Power [W] 1.00 0.80 0.60 0.40 0.20 0.00 90 120 150 180 210 240 Input Voltage [Vac] SR system working SR system OFF Figure 52. Demoboard No Load Consumption for SR System Working and Turned Off http://onsemi.com 27 270 AND8460/D 1.80 1.60 Input Power [W] 1.40 1.20 1.00 0.80 0.60 0.40 90 120 150 180 210 240 270 Input Voltage [Vac] Pout= 100 mW Pout= 500 mW Figure 53. Demoboard Consumption for 100 mW and 500 mW Loads (SR System Working) 98 Vbulk= 400 V LLC Stage Efficiency [%] 96 94 92 90 88 86 0 5 10 15 20 Iout [A] IRFB3206 compensated IRFB3206 uncompensated Figure 54. LLC Stage Efficiency versus Output Current for Compensated and Uncompensated SR Systems Featuring IRFB3206 MOSFETs and Nominal Bulk Voltage of 400 Vdc http://onsemi.com 28 AND8460/D 98 Vbulk=400 Vdc 96 Efficiency [%] 94 92 90 88 86 0 5 10 15 20 Output Current [A] IPP015N014N compensated IPP015N04N uncompensated Figure 55. LLC Stage Efficiency versus Output Current for Compensated and Uncompensated SR Systems Featuring IPP015N04N MOSFETs and Nominal Bulk Voltage of 400 Vdc Conducted Emission Quasi−peak dBmV (Domestic) 90 80 Level [dBmV] 70 60 50 40 30 20 10 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Frequency [Hz] Figure 56. Conducted EMI Signature of the Board at Full Load and 110 VAC Input http://onsemi.com 29 AND8460/D Conducted Emission Quasi−peak dBmV (Domestic) 90 80 Level [dBmV] 70 60 50 40 30 20 10 1.0E+05 1.0E+06 1.0E+07 Frequency [Hz] Figure 57. Conducted EMI Signature of the Board at Full Load and 230 VAC Input http://onsemi.com 30 1.0E+08 PE R48 L 2 L15 7mH 3 2 NU 1uF/275Vac C47 NU C44 3 L14 AC INPUT 90 − 265Vac 1 4 1 4 1uF/275Vac C33 CY2 2n2/Y1 CY1 GND1 2n2/Y1 N R91 strap C31 22n 22n MRA4007 C30 R53 220 R43 220 MRA4007 D11 D10 D8 7.5V C14 1uF 2N7002E Q8 R21 220k Q6 MPSA44 R22 47k R16 47k R31 1M8 R23 1M8 R15 1M8 GND R75 43k R70 24k 470n C36 R44 8k2 C15 R45 6k2 1.2n C26 R72 220R C34 6.8n 1uF/275Vac GND R74 10k R25 R38 R81 47k R80 27k C43 10n Q7 D7 100k R69 1uF C55 HV STBY NC BO VCTRL OVP FB STDW N CSINPFCOK ZCD VCC CT DRV OSC GND IC3 NCP1605 120uH L7 R26 6k2 R100 R73 10k R102 27k R97 5k6 R33 10k 2R2 GND R103 R104 150k 30k GND 100n C41 +17V GND Q4 C35 D22 R83 15k 100p R29 1k 1N5408 MSR860 D5 D4 STP20NM60FP PE1 MOUNT−PAD−ROUND3.6 GND R92 7k5 R101 6k2 2n2 C52 R93 200k R63 150k R105 820R 47n C46 5k6 R77 C17 CSS VBOOT FMAX MUPP CTMR HB RT NC BO VCC FB MLOW DT GND FF SF R96 18R D23 +17V 51k R57 C16 GND R82 5k6 D21 R79 2k7 Q11 R76 560k GND R56 430k R47 1M8 R35 1M8 R27 1M8 R18 1M8 IC5 NCP1397BSMD R87 43k C57 2n2 R67 13k GND R106 13k R66 56k R65 22k Q10 BC846 +17V R46 1M8 R34 1M8 R28 1M8 R17 1M8 V bulk R54 10R C53 100n R58 N.U. D13 N.U. GND Q1 NU +17V R62 N.U. R55 10R D12 N.U. R36 10k C54 100n R59 N.U. Q5 Q3 R60 1k D2 NU R64 10k 68n C28 R5 0R GND STP12NM50FP R20 10k STP12NM50FP +17V C2 NU GND D6 N.U. GND NU C50 GND TR1 PULSE GND R107 4M7 CY3 2n2/Y1 2 3 PC817 1 4 R94 2k2 GND R84 1k +17V OK1 D15 1N4148SMD 220p C29 GND R52 24k R42 24k D14 1N4148SMD C32 NU D3 1N4148SMD C3 + 220uF/25V C18 D9 N.U. C7 R6 2R2 R4 NU W2 W1 D1 W3 W4 NU 1N4148SMD 0.1R/2W 47 L3 BC807−16LT1SMD KBU810 GND2 L13 100u + 100uF/450V R19 56k GND 15nF/1000Vdc 15nF/1000Vdc B1 VDRH10S275TSE L12 F1 100u T−4A 470n C39 R50 62k R71 1M8 100n C40 560p C38 3n9 GND1 Auxiliary trigger main transformer input R40 27R C25 R8 27R C4 3n9 R41 27R R9 27R IRFB3206 R90 1k R85 1k IC4 TL431 C45 N.U. D20 N.U. Lcomp2 R51 10k Q9 R12 10k Q2 JP2 1 2 IRFB3206 2702.0012 2722.005A 4u7/35V + 220u/25 C42 1N4148SMD L11 R L10 L9 L8 R30 NU R10 22R NU NU C51 10n R88 N.U. 1uF NU R98 8k2 9k1 R95 R68 NU R99 5k1 N.U. C48 R2 0R R14 N.U. R108 NU VCC MIN_TOFF MIN_TON TRIG 0R R24 VCC MIN_TOFF MIN_TON TRIG IC1 NCP4303 R61 N.U. 1 2 3 4 R86 N.U. D19 D17 GND1 C27 N.C. 39k 11k 100n R37 R39 C20 1 2 3 4 C6 IC2 1uF NCP4303 C19 R89 12k 0R N.C. 1k 39k 11k 2 SJ1 0R 0805 C13 R13 R7 R11 R78 D18 C5 100n R49 1k D16 1 GND1 C49 1n GND1 NU 4n R32 22R GND1 C37 NU 0R Lcomp1 L6 NU NU 4n L1 L5 L4 0R R3 HEATSINK_1 8 7 6 5 8 7 6 5 SK 454 150 SA DRV GND COMP CS DRV GND COMP CS GND1 C8 GND1 C9 HEATSINK_2 GND + + SK 454 135 SA BC846 1N4148SMD C10 22uF/25V + GND + + 1N4148SMD GND R1 22R GND1 + IC2_TRIG IC1_TRIG 1000u/35 1000u/35 + + C21 + 100uF/450V MURA160SMD GND + Figure 58. Demoboard Schematic Including PCB Options C56 C A 31 GND1 http://onsemi.com GND2 1000u/35 1000u/35 C22 1000u/35 1000u/35 SJ2 2 1 N.U. 1000u/35 1000u/35 C23 C11 + C24 200nH L2 C12 + GND1 220u/25V GND1 C1 1.0 JP3 1 2 3 X1−3 X1−4 X1−1 X1−2 AND8460/D AND8460/D Figure 59. Top Side of the PCB Figure 60. Bottom Side of the PCB http://onsemi.com 32 AND8460/D Figure 61. Top Labels Figure 62. Bottom Labels http://onsemi.com 33 AND8460/D Figure 63. Demoboard Photo – Top Side Figure 64. Demoboard Photo – Bottom Side http://onsemi.com 34 AND8460/D Figure 65. Demoboard Photo, Top Side with Measured Temperatures on the Full Loaded Board Figure 66. Detail Photo of the SR Compensation Inductances http://onsemi.com 35 AND8460/D Table 6. BILL OF MATERIALS FOR THE NCP4303 DEMO BOARD Designator Qty Description Value Tolerance Footprint Manufacturer Manufacturer Part Number Substitution Allowed Pb−Free B1 1 Bridge Rectifier KBU8M − KBU8M Fairchild KBU8M Yes Yes C1 1 Electrolytic Capacitor 22 mF / 25 V 20% Through Hole Koshin KZH−025V220MC110 Yes Yes C3, C12, C42 3 Electrolytic capacitor 220 mF / 25 V 20% Through Hole Koshin KZH−025V221MF115 Yes Yes C2, C13, C27 3 MKP Capacitor NU − 805 − − Yes Yes C6, C14, C20, C55 4 Ceramic Capacitor 1 mF 10% 1206 Kemet C1206F105K5RACTU Yes Yes C15, C33, C47 3 MKP Capacitor 1.0 mF / 275 Vac 20% Through Hole Epcos B32923C3105M Yes Yes C16, C17 1 Electrolytic Bulk Capacitor 100 mF / 450 V 20% Through Hole Koshin KPH−450V100UF Yes Yes C50 1 Ceramic Capacitor NU − 805 − − Yes Yes C26 1 Ceramic Capacitor 1.2 nF 10% 805 Kemet C0805C124K1RACTU Yes Yes C38 1 Ceramic Capacitor 560 pF 10% 805 Kemet C0805C561K5RACTU Yes Yes C28 1 Ceramic Capacitor 68 nF 10% 805 Kemet C0805C683K5RACTU Yes Yes C29 1 Ceramic Capacitor 220 pF 10% Through Hole Kemet C0805C221K5RACTU Yes Yes C30, C31 2 Ceramic Capacitor 22 nF / 1 kV 10% 1812 Kemet C1812C223KDRACTU Yes Yes C32, C37 2 Ceramic Capacitor NU − 1206 − − Yes Yes C34 1 Ceramic Capacitor 6.8 nF 10% 805 Kemet C0805C682K5RACTU Yes Yes C35 1 Ceramic Capacitor 100 pF 10% 805 Kemet C0805C101K5GACTU Yes Yes C36, C39 2 Ceramic Capacitor 470 nF 10% 1206 Kemet C1206C474K5RACTU Yes Yes C4, C25 2 Ceramic Capacitor 3.9 nF 10% 1206 Kemet C1206C392K5RACTU Yes Yes C5, C19,C40, C41, C53, C54 6 Ceramic Capacitor 100 nF 10% 1206 Kemet C1206C104K5RACTU Yes Yes C43, C51 2 Ceramic Capacitor 10 nF 10% 805 Kemet C0805C103K5RACTU Yes Yes C44 1 Capacitor NU − Through Hole − − Yes Yes C45 1 Ceramic Capacitor NU − 1206 − − Yes Yes C46 1 Ceramic Capacitor 47 nF 10% 805 Kemet C0805C473K5RACTU Yes Yes C48 1 Ceramic Capacitor NU − 805 − − Yes Yes C49 1 Ceramic Capacitor 1 nF 10% 805 Kemet C0805C102K5RACTU Yes Yes C52, C57 2 Ceramic Capacitor 2.2 nF 10% 805 Kemet C0805C222K5RACTU Yes Yes C56 1 Electrolytic Capacitor 4.7 mF / 50 V 20% Through Hole Koshin KLH−050V4R7MC110 Yes Yes C7, C18 2 Metal Film Capacitor 15 nF / 1600 V 5% Through Hole Epcos B32652A1153J No Yes C8, C9, C10, C11, C21, C22, C23, C24 8 Electrolytic Capacitor 1000 mF / 35 V 20% Through Hole Koshin KZH−035V102MH250 Yes Yes CY1, CY2, CY3 3 Ceramic Capacitor 2.2 nF / Y1/X1 20% Through Hole Murata DE1E3KX222MA5B Yes Yes D1, D3, D7, D14, D15, D21, D22, D23, R6 9 Switching Diode MMSD4148 − SOD−123 ON Semiconductor MMSD4148T3G No Yes D10, D11 2 Surface Mount Ultrafast Power Rectifier MURA160 − SMA ON Semiconductor MURA160T3G No Yes D12, D13 2 Diode NU − SOD−123 − − Yes Yes D16, D17, D18, D19 4 Diode NU − SOD−123 − − Yes Yes D2 1 Diode NU − SOD−123 − − Yes Yes D20 1 Diode NU − SOD−123 − − Yes Yes D4 1 Standard Recovery Rectifier 1N5408 − Axial Lead ON Semiconductor 1N5408RLG No Yes D5 1 Soft Recovery Rectifier MSRF860 − TO220 (2 LEAD) ON Semiconductor MSRF860G No Yes D6, D9 2 Diode NU − SMA − − Yes Yes http://onsemi.com 36 AND8460/D Table 6. BILL OF MATERIALS FOR THE NCP4303 DEMO BOARD Designator Qty Description Value Tolerance Footprint Manufacturer Manufacturer Part Number Substitution Allowed Pb−Free D8 1 Zener Diode 7.5 V 5% SOD−123 ON Semiconductor MMSZ7V5T1G No Yes HEATSINK_1 1 Heat Sink SK 454 150 SA − SK 454 150 SA Fischer Elektronik SK 454 150 SA Yes Yes HEATSINK_2 1 Heat Sink SK 454 135 SA − SK 454 135 SA Fischer Elektronik SK 454 135 SA Yes Yes IC1, IC2 2 Secondary Side Synchronous Rectifier NCP4303B − SOIC−8 ON Semiconductor NCP4303BDR2G No Yes IC3 1 Power Factor Controller NCP1605 − SOIC−16 ON Semiconductor NCP1605ADR2G No Yes IC4 1 Programmable Precision Reference TL431 0.4% TO−92 ON Semiconductor TL431BCLPG No Yes IC5 1 Resonant Mode Controller NCP1397B − SOIC−16 ON Semiconductor NCP1397BDR2G No Yes J1 1 Input Terminal Block Pitch 7.5 mm − CTB0110/2 Camden El. CTB0110/2 Yes Yes JP2 1 Jumper 1x2 − − 2 x 2.54 mm Various − Yes Yes JP3 1 Jumper 1x3 − − 3 x 2.54 mm Various − Yes Yes L1, L8 2 Inductor − Wire Strap − − Wire Strap − − Yes Yes L12, L13 2 Inductor 100 mH 20% DO5040H Coilcraft DO5040H−104MLB Yes Yes L14 1 Inductor NU − − − − Yes Yes L15 1 EMI filter 7 mH 15% TLBI Pulse 6001.0069 Yes Yes L2 1 Inductor 200 nH 20% L−US20A Bohemia Electric TC−05001510−00 Yes Yes L3 1 Inductor NU − − − − Yes Yes L4, L5, L6, L9, L10, L11 6 Inductor NU − − − − Yes Yes L7 1 Inductor 120 mH 10% 2722.0005C Pulse 2722.0005C Yes Yes OK1 1 Opto Coupler HCPL−817 − DIP−4 Avago Technologies HCPL−817−000E Yes Yes Q1 1 General Purpose Transistor NU − SOT−123 − Yes Yes Q10, Q11 2 General Purpose Transistor NPN BC846 − SOT−123 ON Semiconductor BC846ALT1G No Yes Q2, Q9 2 MOSFET transistor IRFB3206 − TO−220 International Rectifier IRFB3206GPBF Yes Yes Q3, Q5 2 MOSFET transistor STP12NM50FP − TO−220 ST Microelectronics STP12NM50FP Yes Yes Q4 1 MOSFET transistor STP20NM60FP − TO−220 ST Microelectronics STP20NM60FP Yes Yes Q6 1 High Voltage Transistor NPN MPSA44 − TO−92 ON Semiconductor MPSA44RL1G No Yes Q7 1 PNP General Purpose Transistor BC807−16L − SOT−22 ON Semiconductor BC807−16LT1G No Yes Q8 1 Small Signal MOSFET N−Channel 2N7002E − SOT−23 ON Semiconductor 2N7002ET1G No Yes R1, R10, R32 3 Resistor SMD 22 R 1% 805 Rohm Semiconductor MCR10EZPF22R0 Yes Yes R100, R101 2 Resistor SMD 6.2 k 1% 805 Rohm Semiconductor MCR10EZHF6201 Yes Yes R104 1 Resistor SMD 30 k 1% 805 Rohm Semiconductor MCR10EZHF3002 Yes Yes R105 1 Resistor SMD 820 R 1% 805 Rohm Semiconductor MCR10EZPF8200 Yes Yes R107 1 Resistor trough hole, high voltage 4.7 M 5% 414 Vishay VR37000004704JA100 Yes Yes R11, R39 2 Resistor SMD 11 k 1% 805 Rohm Semiconductor MCR10EZPF1102 Yes Yes R12, R20, R33, R36, R51, R64, R73, R74 8 Resistor SMD 10 k 1% 805 Rohm Semiconductor MCR10EZPF1002 Yes Yes R13, R49, R60, R84, R85, R90 6 Resistor SMD 1k 1% 805 Rohm Semiconductor MCR10EZPF1001 Yes Yes R14, R58, R59, R61, R62, R86, R88 7 Resistor SMD NU − 805 − − Yes Yes http://onsemi.com 37 AND8460/D Table 6. BILL OF MATERIALS FOR THE NCP4303 DEMO BOARD Designator Qty Description Value Tolerance Footprint Manufacturer Manufacturer Part Number Substitution Allowed Pb−Free R15, R17, R18, R23, R27, R28, R31, R34, R35, R46, R47, R50 12 Resistor SMD 1.8 M 1% 805 Rohm Semiconductor MCR10EZHF1804 Yes Yes R16, R22 2 Resistor SMD 47 k 5% 2010 Vishay CRCW201047K0JNEF Yes Yes R19, R66 2 Resistor SMD 56 k 1% 805 Rohm Semiconductor MCR10EZHF5602 Yes Yes R2, R3, R24, R30, R78 5 Resistor SMD 0R − 805 Rohm Semiconductor MCR10EZPJ000 Yes Yes R21 1 Resistor SMD 220 k 1% 805 Rohm Semiconductor MCR10EZPF2203 Yes Yes R25 1 Resistor SMD 47 R 1% 805 Rohm Semiconductor MCR10EZPF47R0 Yes Yes R29 1 Resistor SMD 1k 1% 1206 Rohm Semiconductor MCR18EZPF1001 Yes Yes R38 1 Resistor Through Hole 0.1 R / 3 W 1% Axial Lead Vishay PAC300001007FAC000 Yes Yes R4, R68, R108 3 Resistor SMD NU − 805 − − Yes Yes R42, R52 2 Resistor SMD 24 k 1% 1206 Rohm Semiconductor MCR18EZPF2402 Yes Yes R43, R53 2 Resistor SMD 220 R 5% 2010 Vishay CRCW2010220RJNEF Yes Yes R44, R98 2 Resistor SMD 8.2 k 1% 805 Rohm Semiconductor MCR10EZHF8201 Yes Yes R45 1 Resistor SMD 6.2 k 1% 805 Rohm Semiconductor MCR10EZHF6201 Yes Yes R48 1 Varistor S10K275 − Disc − 10 mm Epcos B72210S0271K101 Yes Yes R54, R55 2 Resistor SMD 10 R 1% 805 Rohm Semiconductor MCR10EZPF10R0 Yes Yes R56 1 Resistor SMD 430 k 1% 805 Rohm Semiconductor MCR10EZPF4303 Yes Yes R57 1 Resistor SMD 51 k 1% 805 Rohm Semiconductor MCR10EZHF5102 Yes Yes R5, R26 2 Resistor SMD 2.2 R 1% 805 Rohm Semiconductor MCR10EZHJ2R2 Yes Yes R63, R103 2 Resistor SMD 150 k 1% 805 Rohm Semiconductor MCR10EZPF1503 Yes Yes R65 1 Resistor SMD 22 k 1% 805 Rohm Semiconductor MCR10EZHF2202 Yes Yes R67, R106 2 Resistor SMD 13 k 1% 805 Rohm Semiconductor MCR10EZHF1302 Yes Yes R69 1 Resistor SMD 100k 1% 805 Rohm Semiconductor MCR10EZPF1003 Yes Yes R7, R37 2 Resistor SMD 39 k 1% 805 Rohm Semiconductor MCR10EZHF3902 Yes Yes R70 1 Resistor SMD 24 k 1% 805 Rohm Semiconductor MCR10EZHF2402 Yes Yes R71 1 Resistor SMD 62 k 1% 805 Rohm Semiconductor MCR10EZHF6202 Yes Yes R72 1 Resistor SMD 220 R 1% 805 Rohm Semiconductor MCR10EZPJ221 Yes Yes R75, R87 2 Resistor SMD 43 k 1% 805 Rohm Semiconductor MCR10EZHF4302 Yes Yes R76 1 Resistor SMD 560 k 1% 805 Rohm Semiconductor MCR10EZPF5603 Yes Yes R77, R82, R97 3 Resistor SMD 5.6 k 1% 805 Rohm Semiconductor MCR10EZHF5601 Yes Yes R79 1 Resistor SMD 2.7 k 1% 805 Rohm Semiconductor MCR10EZHF2701 Yes Yes R8, R9, R40, R41 4 Resistor SMD 27 R 1% 1206 Rohm Semiconductor MCR18EZPF27R0 Yes Yes R80, R102 2 Resistor SMD 27 k 1% 805 Rohm Semiconductor MCR10EZHF2702 Yes Yes R81 1 Resistor SMD 47 k 1% 805 Rohm Semiconductor MCR10EZHF4702 Yes Yes R83 1 Resistor SMD 15 k 1% 805 Rohm Semiconductor MCR10EZHF1502 Yes Yes R89 1 Resistor SMD 12 k 1% 805 Rohm Semiconductor MCR10EZHF1202 Yes Yes R91 1 NTC Thermistor B57235S509M 20% Disc − Radial Epcos B57235S509M Yes Yes R92 1 Resistor SMD 7.5 k 1% 805 Rohm Semiconductor MCR10EZHF2701 Yes Yes R93 1 Resistor SMD 200 k 1% 805 Rohm Semiconductor MCR10EZPF2003 Yes Yes R94 1 Resistor SMD 2.2 k 1% 805 Rohm Semiconductor MCR10EZHF2201 Yes Yes R95 1 Resistor SMD 9.1 k 1% 805 Rohm Semiconductor MCR10EZHF9101 Yes Yes R96 1 Resistor SMD 18 R 1% 805 Rohm Semiconductor MCR10EZPF18R0 Yes Yes R99 1 Resistor SMD 5.1 k 1% 805 Rohm Semiconductor MCR10EZHF5101 Yes Yes http://onsemi.com 38 AND8460/D Table 6. BILL OF MATERIALS FOR THE NCP4303 DEMO BOARD Designator Qty Description Value Tolerance Footprint Manufacturer Manufacturer Part Number Substitution Allowed Pb−Free SJ1 1 SMD Jumper 0R 5% 805 Rohm Semiconductor MCR10EZPJ000 Yes Yes SJ2 1 SMD Jumper NU − − − − Yes Yes TR1 1 Transformer − − − Pulse See AN for spec Yes Yes X1 2 Output Terminal Block Pitch 5 mm − 20.700M/2 IMO 20.700M/2 Yes Yes F1 − Cover 1 Cover, PCB Fuse Holder − − − Multicomp MCHTC−150M Yes Yes F1 − Fuse 1 Fuse, Medium Delay 4A − − Bussmann TDC 210−4A Yes Yes F1 − Holder 1 Fuse Holder − − SH22.5A Multicomp MCHTC−15M Yes Yes 80 PLUS is a registered trademark of ECOS Consulting. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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