AND8344/D Implementing an LCD TV Power Supply with the NCP1392B, NCP1606 and NCP1351B www.onsemi.com Overview APPLICATION NOTE The following reference document describes a built and tested, GreenPoint® solution for an LCD TV power supply. The reference design circuit consists of one single-sided 171 × 200 mm printed circuit board with a height of only 30 mm. The compact size allows the design to fit into the frame of an LCD TV. An overview of the entire circuit is provided in Figure 1. Careful consideration was given to optimizing the performance while minimizing total solution cost. EMI Filter 85V − 265Vac 12V/3A NCP1606 PFC Controller NCP1392 Resonant Converter + Half Bridge Driver 24V/6A Resonant Technology for Increased Efficiency and Lower EMI Cost Effective Critical Conduction Mode Power Factor Controller NCP1351 SMPS Regulator 12V/3A 24V/6A TL431 5V/4A Highly Integrated Current Mode SMPS Regulator 5V/2A(STB) TL431 Bias Output 5V/2A Start Standby EN or Figure 1. LCD TV Demo Board LCD Power Supply Requirements supply to be used for any region. Also, an auxiliary supply based on the NCP1351 is needed to supply 5 V to the microcontroller which must remain biased even in standby mode. Low power consumption in standby mode is a key requirement in today’s LCD TVs. Recent studies have indicated that in the average EU household, between 5% and 10% of its total yearly electricity consumption is due to the standby mode of consumer electronics equipment and other apparatus. TV sets are obviously one of the biggest contributors. As a result there are various voluntary and mandatory energy regulation standards that vary by country and region. In large flat panel displays (FPD) (> 32″), the power supply is generally internal and requires anywhere from 120 to 500 W depending on the size of the TV and the feature set. Several voltage rails are needed to supply the different blocks such as backlighting, audio amplification, tuner and, image signal processing etc. Because the input power is above 75 W, the application has to be compliant with the IEC1000−3−2 class D standard which places regulations on total harmonic distortion (THD). To meet this regulatory requirement, the NCP1606 active power factor correction front end is used. The PFC is designed to cope with universal mains (85 to 265 V ac, 47−63 Hz) to allow for one power © Semiconductor Components Industries, LLC, 2015 May, 2015 − Rev. 2 1 Publication Order Number: AND8344/D AND8344/D Architecture Overview According to the US Department of Energy’s (DOE) Energy Information Administration (EIA), by 2015 electronics products may account for 18% of total household electricity demand – this will exceed lighting and appliances as a percent of total residential electricity consumption. Part of this is linked to the fact that TVs are ‘on’ more hours per day. According to Nielsen Media Research (NMR), for the September 2004 – September 2005 viewing season, the average U.S. household was tuned into television an average of 8 hours and 11 minutes per day. And this does not take into account additional hours that a TV may be on due to the usage of peripheral devices such as game consoles and computers. As a result, effective November 30, 2008, a new version of the ENERGYSTAR® standard for TVs will go into effect that maintains the < 1 W standby power requirement and adds active mode power consumption based on screen size and format (normal or full High Definition). This standard is technology neutral and applies to all TV displays including LCD, Plasma, and rear projection. Active mode has been included because flat panel televisions being purchased by consumers can consume more than twice the active mode power of the smaller CRT televisions that they are replacing. Much of this increase in power consumption is simply attributable to the increased size of the products being sold now. One of the key differentiating factors of a flat TV over CRT TV is that the cabinet can be very thin. Unfortunately since the amount of power can be high, the power density (W/cm3) is much higher than CRT. Moreover since TVs are used in the living room, audible noise can be a problem, so the use of fans is limited. Finally due to the high density and close proximity of audio amplifiers, power supply and signal processing within the cabinet, excellent EMI performance is necessary. First, the use of active power factor correction in the front-end allows system optimization because the PFC output voltage is well regulated. The implementation of the active PFC front end is done using the NCP1606 controller. The SMPS stage uses a Half Bridge Resonant LLC topology since it improves efficiency, reduces EMI signature and provides better magnetic utilization compared to conventional topologies. The NCP1392 controller is used to implement the Half Bridge Resonant LLC converter. For the standby output circuit, a fly back topology driven by the NCP1351 has been chosen. In summary, the architecture selected for this reference design allows design optimization so that the desired performance is achieved without significantly increasing the component costs and circuit complexity. Demoboard Specification LCD TVs require various voltages to power different parts of the TV. The most power (24 V at 6 A) is used for backlighting. The 12 V rail is used for the audio amplifier and it is also used to power the signal processing board. These two rails are provided from the LLC power supply. Most of the drivers and processors in the LCD TV have their own DC/DC converters to convert voltage from the main SMPS to the appropriate voltage. These DC/DC converters and linear regulators are powered from the 5 V and 12 V rails. In this application, there are two 5 V rails. One is used for the standby power and the other 5 V rail is active only when the main LLC is on. The parameters required for this switched mode power supply (SMPS) are as follows: Requirement Min Max Unit Input Voltage (ac) 85 265 V Output Voltage 1 (dc) − 24 V Region Country Program Name Requirements for Televisions Demoboard Compliance Output Current 1 0 6 A Output Voltage 2 (dc) − 12 V China CSC 3W Yes Output Current 2 0 3 A Korea Energy Saving 3W Yes Output Voltage 3 (dc) − 5 V Output Current 3 0 2 A Output Voltage STBY (dc) − 5 V Output Current STBY 0 2 A Total Output Power 0 200 W Consumption for a 500 mW Output Load in STBY Mode − 1 W Consumption for a 100 mW Output Load in STBY Mode − 400 mW European Union EU Eco−Label 1W 9 W with a STB Yes European Union EU Code of Conduct 3 W with a STB Yes Europe GEEA 1W Yes US 1 Watt Executive Order/ 1W Yes ENERGY STAR The NCP1392 contains the following features which are ideal for this application: As a result high efficiency and a low EMI signature at a reasonable cost are required. Classical topologies are not ideal for meeting these needs: • Flyback: Transformer Usage is Far from Pptimal • Forward: the EMI Signature is Not Reduced to its Minimum Brown-Out (BO) Protection Input This pin has two functions. First, the BO permanently monitors the bulk voltage and ensures the SMPS works in the proper Vbulk range. The second function is activated if this pin is pulling up to 2 V which stops all output switching. www.onsemi.com 2 AND8344/D This is used to enter a skip cycle during no-load conditions or to stop pulses to protect the primary MOSFETs if there is a short on the output(s) or if the rectifier on the secondary side is damaged. oscillator is current-driven, additional regulation loops can easily be connected to the RT pin in parallel. The RT pin has a 3.5 V reference voltage. Therefore, a shunt regulator (e.g. TLV431) can be directly connected to the RT pin to create another regulation loop. 100 ms PFC Delay This timer ensures the main LLC SMPS will not start until the power factor correction (PFC) stage is fully stabilized. This is beneficial mainly in cases where the SMPS is connected to mains with 110 V ac. Without the delay, the PFC front end may not be able to supply the needed current if the LLC starts under full load and there is a short soft-start. High Side Driver The NCP1392 enables direct connection of the high side MOSFET due to the built-in high side driver (HSD). This “floating” driver accepts voltages up to 600 V and has robust dV/dt immunity. The HSD is powered from Vcc through a bootstrap diode and features under-voltage detection, which ensures the high side MOSFET will be turned on only if there is enough voltage to properly turn on the MOSFET. With this driver, it is not necessary to use a special transformer or optocoupler for driving the upper MOSFET. For more information and a detailed description of the NCP1392B, please refer to the data sheet. Fixed Dead Time (DT) The NCP1392 series features fixed dead time between outputs and is available in 300 ns, 600 ns and 1,100 ns versions. This provides the designer flexibility in choosing the version with the appropriate dead time to protect switches against cross-conduction. The length of the DT is chosen based on the total capacitance of MOSFETs used in the application. If the DT is short, there is not enough time to re-charge this capacitance and the opposite MOSFET is turned on before the source to drain voltage reaches 0 V. The result is poor efficiency and EMI. On the other hand, it is not good to choose a DT that is too long. During the dead time period, current is supplied by the resonant tank, but there is only a finite amount stored for use during the dead time period. Too long of a dead time will deplete all of the stored energy needed to supply the current. If this occurs, the current will reverse direction before the dead time ends. The result is “hard switching” which is very dangerous and the MOSFET can be damaged. Furthermore, the higher DT means lower frequency range. Based on these facts, for this application version B has been chosen with a dead time of 600 ns. Detailed Demoboard Description The schematic of the demoboard is shown in Figure 47. As mentioned above, the SMPS is composed of three blocks. The PFC front stage accepts input voltages from 85 Vac/60 Hz to 265 Vac/50 Hz and converts it to 385 V dc nominal. The main LLC SMPS converts the bulk voltage from 385 V to two dc voltages, 12 V/3 A and 24 V/6 A. A regulation loop is taken only from the 24 V output because regulation of this output is the most critical. To ensure that both output voltages are regulated, it is necessary to add another resistor divider and the whole loop will regulate at a percentage weight with respect to both output voltages. The third block is the standby SMPS which powers the control unit of the TV when the main SMPS is off by supplying a 5 V/2 A output. There is an additional 5 V/2 A output available when the LLC is active. NOTE: Built-In Oscillator (RT Pin) The NCP1392 includes a built-in oscillator driven by current flowing from the RT pin. Fmin is set with ±3% accuracy, and Fmax has an accuracy of ±15%. Because the Because the regulation loop is taken only from 24 V line, it is not possible to load the 12 V line when there is no load on the 24 V line. PFC Front Stage Figure 2. The EMI Filter www.onsemi.com 3 AND8344/D Figure 3. Schematic of the PFC Stage a compensation network. The transient response depends on the compensation network. Auxiliary winding W2 of the L2 coil provides information through resistor R15 to the PFC controller about demagnetization of the coil. Thanks to this monitoring, it is possible to turn on the switcher after full demagnetization of the coil. This enables the use of a diode with higher trr, and it is good from an EMI point of view. Diode D7 and resistor R30 together with W3 of the L2 help to lower on time if the input voltage reaches the peak value. For detailed information on how the PFC stage works and how to design it, please read Application Note AND8123/D. The NCP1606B boost PFC controller is used in this application. This controller operates in critical conduction mode. The printed circuit board (PCB) is compatible with some other ON Semiconductor PFC controllers (e.g. MC33262, NCP1601 or NCP1653). The input voltage passes through an EMI filter (Figure 2), which protects the distribution network against noise generated by the SMPS. The EMI filter is created by capacitors CY1, CY2, C44, C63 and current compensated chokes L9 and L12 (L10 and L11 are options for using chokes in a different package). Varistor R48 protects the SMPS against surges passed from the mains. Filtered ac voltage is rectified by a four-diode rectifier and connected to capacitor C14, which filters high frequency peaks created in the PFC stage (Figure 3). If MOSFET Q2 is turned on, energy is stored in coil L2. Once MOSFET Q2 is turned off, the energy stored in coil L2 is added to the rectified voltage on C14 and the bulk capacitors are charged through diode D4. This voltage is divided by resistors R7, R11, R18, R28, R51, R38, R46, and R47 and is connected to the FB pin of the PFC in order to set the regulation level. The current flowing through PFC coil L2 is sensed by R20 and ultimately the CS pin of the PFC controller using resistor divider R35 and R64. The IC monitors coil current during every switching cycle and if it exceeds the safety level, it immediately turns off the MOSFET. Resistor R37 and capacitors C26 and C27 create Standby Power Supply Figure 4. The SMPS Primary Side Schematic www.onsemi.com 4 AND8344/D An NCP1351B controller was chosen for the standby power supply. It is a current-mode pulse width modulation (PWM) controller, which works with a variable frequency and a quasi-fixed peak current. As the output load becomes lighter, the operating frequency and peak current diminish. This prevents mechanical resonance of the transformer and limits acoustic noise. The low operating frequency also increases efficiency by reducing switching losses. The rectified voltage is brought to transformer TR2 and switched by Q18. The NCP1351B drives the MOSFET through resistor R114. Resistor R122 is placed only for testing and evaluating of the gate drive signal. Resistors R33, R110, R109 and capacitor C66 create a high-voltage clamp that protect Q18 against high-voltage spikes generated during MOSFET turn off by the leakage inductance of the standby transformer. A parallel combination of capacitors C70 and C71 sets a maximum frequency beyond which no current flows into the FB. A parallel combination of R129 and R130 forms a negative current sense resistor, sensed through R131 and clamped by C72. C73 becomes a timing capacitor if a current loop to FB disappears. This capacitor is charged from an internal current source, and, once this capacitor reaches 5 V, the IC stops. D34 separates Vcc during start-up conditions to charge only that part necessary to start the standby power supply. Once the standby starts working properly, it is supplied from auxiliary winding W4 of the TR2 through D29, which rectifies voltage from W4 and charges C55. A start-up circuit is formed by D27, D28, R99, R100, R101 and R102, and the voltage for start-up is taken directly from the ac mains. The values of resistors R99 to R101 are selected to be small enough that capacitor C75 is charged in a reasonable time for 120 Vac mains, yet large enough for acceptable power dissipation given an input voltage of 265 Vac. Once capacitor C75 is charged to the level necessary to turn on the NCP1351B, the SMPS is powered from auxiliary winding W4 of the TR2. The circuit around Q17, R108, R113, R116, R127, and R128 is used to turn off the standby SMPS if the mains input is disconnected (e.g. main switch is turned off). If the mains voltage is at high line and the output consumption is very low, discharging the bulk through a small load takes a very long time and it is possible that an indicator LED would remain on too long and it would be difficult to determine whether the LCD TV is turned off or not. So, if the mains disappears, the voltage at the base of Q17 disappears as well. This means that Q17 turns off, the LATCH pin of the NCP1351B is pulled up through R108 and R116, and the output pulses stop. In case of a quick restoration of the mains or a brief transient drop, the voltage from LATCH is brought to base Q20 through R120. If the latch is pulled up, Q20 shorts the Vcc line and resets the internal latch logic inside the NCP1351B. NOTE: The Secondary Side: Figure 5. The SMPS Secondary Side Schematic Voltage from the transformer is rectified by diode D30 and filtered by the set of capacitors C58, C59, C60, C61, C62 and inductor L13. Part of this voltage is available for powering the control circuit and the remainder is switched by Q15 to the 5 V output when the main SMPS is activated and an output voltage of 12 V is presented. The level of the output voltage is set by resistor divider R125 and R136. The bias current for TL431B is set by resistor R124. Stability and speed of response for transients are set by resistor R121 and capacitors C76 and C79 on the secondary side. For the choice of appropriate devices and for setting the appropriate loop gain and phase margin, please see application note AND8327/D. The gain margin achieved with the devices used here is shown in Figure 6. Gain chart 30 180 120 20 60 10 0 0 Gain −10 −60 −20 −120 −30 0.1 0.2 0.3 0.5 The circuit coupling around Q17 and Q20 is not mandatory for proper function of SMPS. This is provided to illustrate how to address this functionality if it is required. 0.8 1.3 2.1 3.5 5.8 9.6 Frequency [kHz] Figure 6. Frequency Response of the Open Regulation Loop of the STBY www.onsemi.com 5 Phase [°] Gain [dB] Phase −180 16 AND8344/D Figure 7 shows the power consumption when only the standby stage is operating (LLC and PFC are disabled), with loads of 0.5 W, 0.1 W and no load. Consumption is below 1 W for a 0.5 W load and below 0.4 W for a 0.1 W load. The standby efficiency meets the requirements of today’s energy efficiency regulation. The SMPS is turned from standby mode to full power by a signal on the EN pin. This signal can be either negative or positive (the PCB is designed for this). In this configuration, SMPS is turned on by enabling the EN pin and turned off by grounding the pin. Transistor Q21 is turned on through resistor R123. Optocoupler OK2 is activated from +5 V STBY and through R96. Once the optocoupler is activated, a positive voltage from C56 is brought to diode D31 and to the base of Q13. This positive voltage turns on Q13 and provides bias to the main LLC and PFC circuit. Transistor Q14 and diode D32 provide voltage for the rest of the SMPS. In case the standby operates with no load, the rectified voltage on C55 is very small. An additional drop on the R104 diminishes the voltage even more and the voltage on the emitter of Q13 may be too low to reach the level of 13.1 Vmax at which the PFC stage starts. Thus, the PFC stage never starts operating. Because of negative current sense of the NCP1351B, it is not possible to connect voltage from C55 directly to capacitor C56 because the current charging this capacitor flows through R129 and R130 and is registered by NCP1351. Due to this fact, voltage regulation by Q14 and D32 is beneficial only when the SMPS starts with a no load condition on the secondary side. Another regulator is created by Q13 and D31 is necessary for regulating the voltage from the auxiliary winding of TR1. STBY Consumption 1000 Input power [mW] 900 500mW load 800 700 600 500 400 100mW load 300 200 No load 100 0 85 105 125 145 165 185 205 225 245 265 Input voltage [V] Figure 7. Standby Consumption vs. Line Voltage Main LLC Power Supply Figure 8. The LLC Primary Side Schematic www.onsemi.com 6 AND8344/D NOTE: The main LLC SMPS includes sub-circuits for various protection features. These can be removed if the given function is not required. Where: VB = Voltage on Base Q4 hFE = dc Current Gain of Q4 Vbulk = Nominal Bulk Voltage Rlower = serial-parallel combination R39, R47, R48 and R51 and is calculated by: The voltage used for the main LLC is taken from bulk capacitors C12 and C13 which are charged by the PFC stage. A power loop of the LLC is closed through Q1 and Q3, main transformer TR1, and resonant capacitor(s) C21 (and C2). The gates of the MOSFETs are protected by R10 and R21. The NCP1392 features a 600 V high-side drive, which allows connection of both transistors directly to the controller. Resistors R33 and R34 damp the gate charging, suppress overshoots on the gates, and control EMI noise. The energy required for controlling the high side MOSFET is taken from bootstrap capacitor C38, whose voltage floats on the bridge voltage. If Q3 is turned on, the HB pin is grounded and bootstrap capacitor C38 is charged through resistor R67 and high-voltage diode D14. The NCP1392 always turns on Mlower first after any restart of the IC to charge this bootstrap capacitor. For situations when the standby is not loaded and the main LLC must be operated at full load, it is important to self-power the LLC. Self-powering is ensured by winding W6 of transformer TR1. The current from W6 is limited by resistor R4, rectified by diode D1, and connected to C56. R lower + (eq. 2) Rupper = serial combination of resistors R7, R11, R15 and R28, which is calculated by: R upper + R7 ) R11 ) R15 ) R28 (eq. 3) IE = current from the emitter of Q4, which is calculated by: (eq. 4) V @ (R87 ) R88) (V E * V BO) @ (R53 ) R54) I E + BO ) R87 @ R88 R53 @ R54 Where: VBO = BO voltage of the NCP1392B, which is 1.0 V VE = voltage on the emitter of Q4, which is: V E + V B * V BE (eq. 5) Because the right side of Equation 1 can reach only a very low value and hFE depends on transistor Q4 (which according to the datasheet ranges from 250 to 600), this value can be set approximately to 0.4 mA for 385 Vbulk and linearly decreases with the voltage on the base to zero. This value has been measured in this application. Once the VB value is known, we can determine the resistors necessary to set Vbulk_ON and Vbulk_OFF. According to the datasheet, the equation for determining Rlower of the BO pin is as follows: Design of the Brown-Out Divider: The NCP1392 features a BO pin, which continuously senses bulk voltage to ensure sufficient voltage is available on the bulk capacitor for normal operation. To sense BO voltage it is necessary to use a resistor divider connected to Vbulk. If Vbulk range between 295 V and 375 V is required, the recommended total resistance of the BO divider is approximately 4.4 MW. If the SMPS is powered from 265 V ac, the power dissipation on this divider is almost 32 mW. This power loss contributes to increased losses in standby mode. Because there is a feedback divider for the PFC stage, it is possible to save the 32 mW by using an emitter follower based on Q4. Because the LLC controller sinks 18.2 mA from the BO pin when the Vbulk is lower than the set level, it is not possible to connect the BO pin directly to the PFC feedback divider. As soon as this is connected, the current sunk from the divider diminishes the voltage on the divider, so the circuit cannot regulate at the correct voltage level. The solution is to set the voltage that will be connected to the base of Q4. The level of this voltage is best kept higher because of the thermal dependence of the transistor’s VBE. In this application, 6.5 V is chosen as a nominal Vbulk. It is necessary as well to keep the emitter voltage above the voltage of D22 to prevent too high of negative voltage on the base-emitter junction of Q4: ǒ 1 1 ) 1 R47@R48 )R39 R51 R47)R48 R BO_lower + Vref BO @ V BO_bulk1 * V BO_bulk2 I BO @ (V BO_bulk2 * Vref BO) (eq. 6) And for Rupper: R BO_upper + R BO_lower @ V BO_bulk2 * Vref BO Vref BO (eq. 7) Where: VrefBO = 1.0 V (see Datasheet) IBO = 18.2 mA (see Datasheet) V BO_bulk + R lower @ V bulk * V BE R upper ) R lower (eq. 8) Vbulk is the voltage at which the LLC can start. This LLC should start at 375 V. If the values are put into Equation 8 then: (eq. 1) Ǔ このを8にすると、のようになります。 R lower @ R upper R lower I V B + V bulk * E @ R lower ) R upper h FE R lower ) R upper V BO_bulk1 + 47.465 @ 10 3 @ 375 * 0.55 2.74 @ 10 6 ) 47.465 @ 10 3 V BO_bulk1 ^ 5.84 V www.onsemi.com 7 (eq. 9) AND8344/D no FB signal is available. This frequency is set for cases when the LLC is not able to keep the output voltage at a nominal level. It is important to set this resistance at such a value as to avoid the fall of LLC into the zero current switching (ZCS) operating area. A maximum operating frequency is set by R93 and the resistance of OK1. The voltage at which the LLC stops pulsing is set at 295 V. Using this voltage in Equation 8 yields: V BO_bulk2 + 47.465 @ 10 3 @ 295 * 0.55 2.74 @ 10 6 ) 47.465 @ 10 3 V BO_bulk2 ^ 4.47 V (eq. 10) Using Equation 6, the value of the lower resistor is obtained: R BO_lower + 1 @ 5.84 * 4.47 18.2 @ 10 *6(4.47 * 1) R BO_lower ^ 21.69 kW Skip Mode: (eq. 11) Using Equation 7, the value of the upper resistor is obtained: R BO_upper + 21.69 @ 10 3 @ 5.84 * 1 1 R BO_upper ^ 75.27 kW (eq. 12) For RBO_lower, a parallel combination of resistors 24 kW and 220 kW is used and their total value is 21.69 kW. For RBO_upper, a parallel combination of resistors 82 kW and 910 kW is used which results in a resistance of 75.27 kW. As mentioned above, the BO pin has two functions. The first is Vbulk monitoring, if the voltage on this pin drops below 1 V, the NCP1392 stops pulsing after 20 ms. The other function is enable, if the voltage on this pin exceeds 2 V, the IC stops switching after 0.5 ms and restarts without any delay if the voltage drops back below 1.9 V (please see the NCP1392 data sheet for additional information on the functionality of this pin). This feature is used for skip and hiccup mode. The voltage to capacitor C46 is connected and stabilized by Zener diode D22 through resistor R60. This circuit is used because the BO pin does not accept Vcc voltage. The function of the skip and hiccup mode will be explained hereinafter. The Rt pin is the only pin used for setting the operating frequency of this IC. The soft start of this LLC is set by R83, which dictates the frequency at which soft start begins. Capacitor C51 dictates the duration of the soft start. A minimum operating frequency is set by resistor R82 when Figure 9. The Skip Mode Schematic Skip mode improves efficiency by skipping switching cycles during light loading in order to minimize switching losses. Skip mode is implemented via the BO pin. If the output power diminishes, the current flowing through optocoupler OK1 increases. The increased current creates a voltage drop on R93. Once this drop reaches the VBE of Q11, Q11 is turned on. Q6 is turned on through diode D25 and R86, the BO pin exceeds 2 V, and NCP1392 stops pulses immediately. When the output voltage diminishes, the voltage drop on R93 is lower, Q11 and Q6 are turned off, the BO pin drops below 1.9 V, and NCP1392 restores output pulses. The output voltage drop and primary current during a skip period are depicted in Figure 32 and Figure 33. NOTE: www.onsemi.com 8 The skip cycle is an option. If a minimum load for LLC is defined, it is not necessary to implement this function. AND8344/D Output Short Protection: Figure 10. The Output Short Protection Schematic NCP1392B immediately stops output pulses. Once C33 is charged and the flow of current through the EB junction of Q5 stops, Q5 as well as Q8 are turned off. The collector of Q8 is freed and is pulled up by R52. The capacitor C33 is then discharged through D15 and R52. Because the collector of Q7 is not grounded, diodes D18 and D19 are reverse polarized. Thus, the soft start capacitor C51 is not grounded and Q6 is turned off as well. This means that the voltage of the BO pin can drop below 1.9 V and the controller starts working with a regular soft start. Please see Figure 41. This feature protects against shorts on the output, shorts on the output diode and secondary winding failure. This event is detected on the primary side through the charge pump created by D12, D13, C24 and R25. Voltage from this pump is further divided by R50 and R77 and filtered on C43. Once voltage on C43 reaches VBE of Q7, Q7 is turned on and the current from Vcc starts to flow through junction EB of Q5 and R58 and starts to charge C33. Due to the current flowing through junction EB of Q5, Q5 is turned on and a positive voltage is driven to the base of Q8 through R71. By turning on Q8, the collector of Q7 is grounded even if the voltage on the base of Q7 is already low. If the collector of Q7 is grounded, soft start capacitor C51 is discharged through D18 and transistor Q6 is turned on through diode D19 and R86. Transistor Q6 pulls the BO pin over 2 V, and the NOTE: www.onsemi.com 9 The output short protection is optional. The short resistance can be achieved by using a pair of diodes D3 and D8. In this case only the primary current is limited, the secondary current remains high until the short circuit is removed. AND8344/D Over-Current Protection: Figure 11. The Over-Current Protection Schematic C53 is charged through Q12 and R94. Once the voltage on C53 after division reaches the level necessary to turn on transistor Q10, the collector of Q10 is grounded, and C53 is discharged through Q10. Thereafter, the same happens as was described above (i.e. the situation of the short [see Figure 40]). If the applied over-current on the output disappears before charging C53 to the level necessary to turn on Q10, the LLC continues in normal operation and C53 is discharged through R91 and R95. This situation occurs, for example, during transients on the output (see Figure 38). If the over-current (even during transients) is present for a long time, C53 does not have enough time to discharge and its voltage reaches critical level, thus causing the output voltage to be stopped (see Figure 39). The output over power is detected by the same charge pump used for detection of output shorts, the divider made by R29 and R75 and filtered on C42. Once the voltage on TLV431 (IC2) reaches its reference level of 1.25 V, TLV431 starts to conduct from the cathode to ground and increases current from the RT pin of the NCP1392B through D17 and R72. The increased current means higher frequency and thus a lower output power. The response speed of this current loop depends on the value of capacitor C32. In case the LLC starts with a shorted output, the current loop controls regulation and a very large current flows through the secondary winding and diodes, which can be damaged. To avoid this situation, there is a circuit around Q10 and Q12. If the current loop starts to regulate, the voltage on the cathode of TLV431 is lower than Vcc. In this situation, current starts to flow through the EB junction of Q12 and through resistor R89, turning on the transistor. Capacitor NOTE: www.onsemi.com 10 The use of the OCP is optional. If the circuit is not used, the overload of the secondary side is not monitored. AND8344/D Secondary Side: Figure 12. The LLC Secondary Side Schematic Phase [°] Gain [dB] Gain chart 180 60 150 50 120 40 90 30 Phase 60 20 30 10 0 0 Gain −30 −10 −60 −20 −90 −30 −120 −40 −150 −50 −60 −180 0.1 0.2 0.3 0.5 0.8 1.3 2.2 3.6 6.1 10.2 17 Frequency [kHz] The main LLC has two outputs, 24 V/6 A and 12 V/3 A. The regulation loop is taken only from the 24 V line, but the PCB is designed to accommodate a percentage weight of both voltages if desired. In the default configuration, the accuracy of the 12 V line is set only by the turns ratio of the secondary windings. Alternate current from secondary windings W2 and W3 of TR1 is rectified by double diode D5 and filtered by the set of capacitors C4, C5, C6, C7, C8, C10, and L1 and connected to the output terminal. The voltage on diode D5 is snubbed by RC segment R1, R9, C1 and C9 to suppress overshoot on the diode. The output voltage is divided by R44 and the parallel combination of R84 and R85. IC4 is biased by resistor R42. Resistor R41 and capacitors C27 and C40 comprise the compensation network. To learn how to choose these devices and how to arrange this circuit, please see application note AND8327/D. The Bode plot in this configuration is shown in Figure 13. Figure 13. Frequency Response of the Open Regulation Loop of the LLC The 12 V line is accomplished by rectifying alternate current from W4 and W5 windings of TR1 by double diode D9. This diode is snubbed by R13, C15, R23 and C22. www.onsemi.com 11 AND8344/D Gain chart The rectified voltage is filtered by C17, C18, C19, C20, C21 and L6 and is connected to the output of the 12 V terminal. Gain Transformer and LLC Tank: For a detailed description on how to design the LLC transformer and resonant tank, please see application notes AND8257/D and AND8255/D. AND8311/D, The transformer used in this application is manufactured by Jepuls, model no. BCK3501−078. The parameters of this transformer are as follow: Primary Winding: 34 Turns Secondary Winding 24 V: 2 × 4 Turns Secondary Winding 12 V: 2 × 2 Turns Aux Winding: 3 Turns Primary Inductance: Lmag = 670 mH Leakage Inductance: Lleak =105 mH 2 @ (V out ) V f) 2 @ (24 ) 0.6) + ^ 0.128 (eq. 14) 385 V in_nom G max + 2 @ (V out ) V f) 2 @ (24 ) 0.6) + ^ 0.167 (eq. 15) 295 V in_min + 1 + 2 @ p @ ǸL leak @ C res + 100 Frequency [kHz] 1000 Gain 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0 Vmin 10 56.5 100 Frequency [kHz] Vnom Vmax 127 1000 Figure 15. Behavior of the Resonant Tank for 10% Load For only 10% of the nominal load, see Figure 15. As one can see, although Vbulk drops to 295 V (voltage set by the BO divider), there is still some gain margin necessary for tolerances of the devices used and so the LLC cannot fall into ZCS. As is seen in Figure 30 and Figure 31, the operating frequency measured by the oscilloscope is 84.5 kHz, which is very close to the frequency calculated in Equation 16. Also notice that ZVS conditions are ensured for both MOSFETs. Because the operating frequency is slightly smaller than calculated, the primary current seen in Figure 30 and Figure 31 is slightly distorted. This frequency changes over time due the ripple of the PFC front stage. (eq. 16) The minimum resonant frequency can be calculated as follows: 1 + 2 @ p @ Ǹ(L leak ) L mag) @ C res 50.8 85.5 113 Gain chart 1 ^ 85.5 kHz 2 @ p @ Ǹ105 @ 10 *6 @ 33 @ 10 *9 f min + Vmax 1.80 1.60 The resonant frequency that best keeps this LLC in operation can be calculated as follows: f res + Vnom Figure 14. Behavior of the Resonant Tank for Full Load 2 @ (V out ) V f) 2 @ (24 ) 0.6) + ^ 0.116 (eq. 13) 425 V in_max G nom + Vmin 10 Accuracy of the primary and leakage inductance: 5% Let’s review this transformer. Necessary gain for our application is: G min + 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 (eq. 17) 1 ^ 2 @ p @ Ǹ(105 @ 10 *6 ) 670 @ 10 *6) @ 33 @ 10 *9 ^ 31.5 kHz PCB Design The PCB layout of the LLC’s primary side is not very critical because switching of the main MOSFETs happens only under ZVS conditions and the influence of PCB parasitic inductances on the operating frequency is negligible. More critical is the secondary side of the LLC. It is recommended that both halves of the path from the secondary winding be made the same length because a difference in path leakages means a different resonant It is very important to keep the operating frequency always above the peak gain. This peak depends on the output load as it is seen on Figure 14 and Figure 15. If the LLC operating frequency were to drop below this peak, Q1 or Q3 is turned on when the opposite transistor’s body diode conducts. This short, but very high current can damage them. A simulation tool is used to see how the resonant tank will operate with this transformer. The results are shown in Figure 14. www.onsemi.com 12 AND8344/D Conclusion frequency for each half of the period. It is recommended to keep power signals as short as possible in the PFC and the STBY stages. This SMPS is designed on a single layer PCB with several wire jumpers. To test efficiency and EMI please follow the steps detailed in test procedure available on the ON Semiconductor web site. The tests show that the demoboard meets all of the requirements for a typical LCD TV. Additional measurements are shown below for further information on the operation of the design. This demoboard shows only one of many possible implementations of the NCP1392 resonant controller and is not intended as final design for end customers. The main goal of this document is to illustrate a typical application where these controller would be used and illustrate some functions that can be implemented with external sub-circuits. Many options are included on the PCB, so it is easy to update an application according to specific requests. The following are are a series of scope plots that may be helpful in understanding the operation of the SMPS under different conditions. Thanks References Results ON Semiconductor thanks the companies: Jepuls − http://www.jepuls.cn/En Epcos − http://www.epcos.com Koshin − http://www.koshin.com.hk Pulse − http://www.pulseeng.com Wurth − http://www.we−online.com Coilcraft − http://www.coilcraft.com for providing the samples used on this demoboard. [1] [2] [3] [4] [5] [6] [7] [8] Data Sheet NCP1392B/D Data Sheet NCP1606B/D Data Sheet NCP1351/D Application Note AND8123/D Application Note AND8255/D Application Note AND8257/D Application Note AND8327/D Bo Yang − Topology Investigation for Front-End DC−DC Power Conversion for Distributed Power System [9] M. B. Borage, S. R. Tiwari and S. Kotaiah − Design Optimization for an LCL − Type Series Resonant Converter Figure 17. STBY primary current and drain voltage for 20 W load, nominal Vbulk. SMPS operates at 60 kHz. Figure 16. Detail of the drain current and voltage of the STBY SMPS for 20 W load and nominal Vbulk. An 800 V MOSFET is used. The max drain voltage for this figure is 600 V, so the transistor is safe. www.onsemi.com 13 AND8344/D Figure 18. Nominal Vbulk, no load. The frequency dropped to approximately 1.7 kHz, and primary current was reduced to 700 mA. Figure 19. Nominal Vbulk, 20 W load, detail of the output ripple Figure 20. Nominal Vbulk, no load, output ripple Figure 21. Nominal Vbulk, transient respond to change load from 4 A to 0.4 A, 50% duty cycle, 10 Hz frequency. Measured overshoot is 190 mV. Figure 22. Nominal Vbulk, transient respond to change load from 4 A to 0.4 A, 50% duty cycle, 10 Hz frequency. Measured drop is 190 mV Figure 23. SMPS in STBY mode, 265 VAC, 10 W load. Primary current and drain voltage www.onsemi.com 14 AND8344/D Figure 24. SMPS in STBY mode, 85 VAC, 10 W load. Primary current and drain voltage Figure 25. SMPS in STBY mode, 265 VAC, no load. Primary current and drain voltage, switching frequency of 500 Hz Figure 26. SMPS in STBY mode, 85 VAC, no load. Primary current and drain voltage, switching frequency of 2 kHz Figure 27. PFC coil current, drain voltage for 265 VAC measured at peak of the sinusoidal waveform, nominal load on the outputs Figure 28. PFC coil current, drain voltage for 230 VAC measured at peak of the sinusoidal waveform, nominal load on the outputs Figure 29. PFC coil current, drain voltage for 85 VAC measured at peak of the sinusoidal waveform, nominal load on the outputs www.onsemi.com 15 AND8344/D Figure 30. LLC primary current and bridge voltage for nominal load on the outputs Figure 31. LLC primary current, bridge voltage and output ripple (measured on 24 V line) for nominal load Figure 32. LLC skip mode. Primary current and output voltage’s ripple for no load on the outputs Figure 33. LLC skip mode. Primary current and output voltage’s ripple for 100 mA on the 24 V line output Figure 34. LLC transient. Respond to change on transient load from 0.75 A to 7.5 A on 24 V line, 10 Hz, 50% duty cycle Figure 35. LLC transient. Respond to change on transient load from 7.5 A to 0.75 A on 24 V line, 10 Hz, 50% duty cycle www.onsemi.com 16 AND8344/D Figure 36. LLC, maximum current on the primary winding if output is shorted Figure 37. LLC, maximum current on the primary winding if secondary winding of the transformer is shorted Figure 38. LLC short overload, primary current, output voltage and C53 voltage Figure 39. LLC long overload, primary current, output voltage and C53 voltage Figure 40. LLC shorting of the output, primary current, output voltage and C53 voltage. LLC periodically tried to restart since short was held. Once short disappears, output voltage is restored. Figure 41. LLC shorting of the output, primary current, output voltage and C33 voltage www.onsemi.com 17 AND8344/D Figure 42. LLC soft start to no load on the outputs Figure 43. LLC soft start to nominal load Efficiency [%] Efficiency 90 88 86 84 82 80 78 76 74 72 70 Vin=230Vac Vin=115Vac 20 40 60 80 100 120 140 Output Power [W] 160 180 200 Figure 44. Efficiency of Entire Demoboard Figure 46. Conducted EMI Signature of the Board at Full Load and 110 VAC Input Figure 45. Conducted EMI Signature of the Board at Full Load and 230 VAC Input www.onsemi.com 18 AND8344/D Figure 47. Schematic of the SMPS www.onsemi.com 19 AND8344/D Figure 48. Bottom Side of the PCB www.onsemi.com 20 AND8344/D Figure 49. Bottom Labels www.onsemi.com 21 AND8344/D Figure 50. Top Labels www.onsemi.com 22 AND8344/D Figure 51. Photo of the Demoboard with Temperatures Measured for 230 Vac and 110 Vac in Bracket (Ambient Temperature 265C, Full Load, Vertical Position) www.onsemi.com 23 AND8344/D Figure 52. Photo of the Demoboard with Heatsinks Removed www.onsemi.com 24 AND8344/D Figure 53. Photo of the Demoboard, Bottom Side www.onsemi.com 25 AND8344/D www.onsemi.com 26 AND8344/D www.onsemi.com 27 AND8344/D ENERGY STAR and the ENERGY STAR mark are registered U.S. marks. GreenPoint is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 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