AND8461/D Design of a 65 W Adapter Utilizing the NCP1237 PWM Controller http://onsemi.com APPLICATION NOTE Introduction Description of the Design Solution When designing adapters, the important defining regulations for efficiency and no load power requirements are the ENERGY STAR® specifications. With the release of the EPS 2.0 standard, the light load input power consumption and the standby power consumption have became more important, reflecting more accurately the actual usage of a laptop adapter which spends a considerable amount of its time with no-load or a minimal load (laptop in sleep mode) attached. When focusing on the light load efficiency of adapter design, the key losses need to be identified. Switching losses play a major role in determining the light load efficiency, and are directly linked to the control methodology. These losses are caused by the energy stored in the sum of all capacitances at the drain node (MOSFET output capacitance, stray capacitance of the transformer and other parasitic capacitances on PCB) together with the gate charge losses associated with driving the MOSFET. These are proportional to the switching frequency, hence, reducing the switching frequency reduces the losses and improves the efficiency. One of the best methods to achieve optimal balance between transformer design and light load efficiency is to have the switching frequency vary as a function of load. This is implemented in the NCP1237/38 family of PWM controllers as a frequency foldback function, thereby lowering the frequency at lighter loads. The solution was implemented utilizing flyback topology, giving the advantage of a dense power design. The design operates in both CCM (Continuous Conduction Mode) and DCM (Discontinuous Conduction Mode), allowing it to accept a wide universal input voltage range. The CCM operation provides desired full load performance with good efficiency and low ripple of primary current. The DCM operation permits an increase of efficiency under the light load conditions, by decreasing the switching losses. The device switches at 65 kHz which represents a good trade-off between switching losses and magnetics size. For meeting the design requirements, the NCP1237 fixed frequency controller was selected. This device is housed in a SOIC 7 lead that includes multiple features including input ac line sensing. The electrical schematic of the adapter board appears on Figure 1. The adapter consists of several important sections. The first is an input EMI filter to reduce the conducted EMI to the ac line at the input of the adapter. The EMI filter is formed by common-mode inductor L1, differential-mode inductor L2 and capacitors CX1−CX4. The varistor R12 is used protect the adapter against the line overvoltage peaks and NTC R11 is used to limit the bulk capacitor surge current. The resistors RD1, RD2 and RD3 are used for discharging the X capacitors while the adapter unplugged from the power line. The next block is the rectifier with bulk capacitor. It is important to note that the HV pin of the controller is connected to the ac side of the rectifier to decrease average power consumed by high voltage sensing circuitry. The main power stage of the flyback converter utilizes the NDF06N60ZG MOSFET from ON Semiconductor along with a custom designed transformer TR1, described later. Secondary rectification is provided by a low drop Schottky diode MBRF20H150 from ON Semiconductor. A simple RC snubber across the secondary rectifier damps any high frequency ringing caused the unclamped leakage inductance at secondary side of the transformer. 65 W ac-dc Adapter Board Specifications The adapter was designed for the following performance ratings. Output Power 65 W Output Voltage 19 V dc Output Current 3.42 A Minimum Input Voltage 88 V Maximum Input Voltage 265 V Average Efficiency (as per ENERGY STAR 2.0 guidelines) > 85% No-load Input Power © Semiconductor Components Industries, LLC, 2014 October, 2014 − Rev. 1 < 150 mW 1 Publication Order Number: AND8461/D AND8461/D The programmable reference TL431 provides the output voltage regulation. The TL431 output is coupled via the optocoupler to the controller a NCP1237B 65 kHz version. The last stage of the adapter is the output filter consisting of primary filter capacitors COUT1 and COUT2 and secondary filter made up of L3 and COUT3. The circuit is described in detail next, starting with the controller. Features of NCP1237/38/87/88 Family Usage of the current mode PWM controllers from NCP1237/38/87/88 family brings an advantage in decreasing the switching frequency under light load conditions. This feature is called frequency foldback and significantly helps to reduce the switching losses. Other features include: • Current-mode Control: Cycle by cycle primary current sensing helps to prevent any significant overcurrent conditions that would cause transformer core saturation and result in power supply failure. • Dynamic Self-supply: This ensures the voltage supply for the IC in applications where the output voltage varies significantly during operation, e.g. during startup of the power supply or overload conditions. The DSS also supplies the IC during a latched state and when switching operation is halted. The dynamic self-supply operates by controlling the charging of the capacitor at VCC pin via a built-in high voltage current source. To prevent any damage or overheating of the controller in case of short in VCC circuitry, the high voltage startup current is limited when the VCC is below 0.6 V. • High Voltage Sensing: The device allows direct high-voltage sensing up to 500 V to enable features such as brown-out protection and input OVP without using extra pins. • Brown-out and Line Overvoltage Protection: If the peak voltage at the HV pin VHV is higher than 112 V (typical – see VHV(start) spec in the datasheet) and if the VCC is high enough, the device will start operating. The device runs and produces the DRV pulses if the HV pin voltage is in the range of VHV(stop) (brownout protection stop level) and VHV(OV1) (HV overvoltage protection threshold). There is a blanking filter, (with duration of 250 ms) for the HV overvoltage protection to blank the short peaks at the HV input, for example during surge test. Similarly, for allowing the converter to ride through a line drop-out, there is a 61 ms (typ) timer before the brown-out protection is activated. Figure 1. Electrical Schematic of the Adapter with the NCP1237B65 http://onsemi.com 2 AND8461/D • Timer Based Overcurrent and 2nd Level • • • • • Skip Mode with Soft-skip Feature: This burst mode is Over-current Protections: The devices NCP1237/87 offer a transient (2nd level) overcurrent protection which is activated when the sensed voltage at CS pin stays above the transient overcurrent protection threshold of 0.5 V (typ) for a time longer than the transient peak power timer duration time (typ 156 ms). It allows using the NCP1237/87 with the peak power protection in the printer adapters which can deliver 2 times higher peak power than the maximum output power from the thermal loading point of view. The whole family of controllers NCP1237/38/87/88 offers the over-current protection which is activated when the voltage at CS pin is above an internal threshold of 0.7 V (typ) for a time longer than over current fault timer duration time (typ 78 ms). Current Stop Protection: A special additional current stop protection senses the voltage at the current sensing pin. If this voltage is higher than 150% of the maximum internal current set point, then the protection fault mode is immediately activated. This feature protects application against the winding short-circuit or the shorts at the output of the application. Overpower Compensation: The primary peak current value varies with the value of the input voltage. The reason is the propagation delay between the internal current set point detection and the power MOSFET switch off and dependence of the primary current slope on the input voltage. To eliminate this phenomenon, the peak voltage at HV pin is sensed and converted into a current flowing out of the CS pin. By the external resistor ROPP a voltage offset to Vsense voltage is created providing the overpower compensation as a result. Built-in Internal Slope Compensation: To avoid the sub harmonic oscillations during the CCM operation with the duty ratio D higher than 50%, internal slope compensation is applied. Latch Input: The LATCH pin feature allows the additional external OVP and OTP protections. If this pin is between 0.8 V and 2.5 V (when not connected, it is at 1.2 V), the output drive pulses are active. An external NTC can be used to pull it below 0.8 V for OTP and a Zener diode to the bias voltage can be used to detect output OTP condition and shut down the pulses. A decoupling capacitor C1 can be used to filter an induced noise to node where the latch pin is connected. A precharge current INTC(SSTART) is applied to the C1 during the soft-start period to charge the decoupling capacitor and avoid false triggering of the OTP protection. Maximum recommended value of C1 is 325 nF. It is important to note that during soft-start period the OTP is not activated. used under the no load conditions or light load conditions to increase the total efficiency and no load input power. The Soft-skip feature softens the edges of the bursts of pulses in skip mode to decrease the level of possible acoustic noise. Design of the Power Stage The basic electrical schematic of the power stage is shown on Figure 2. Figure 2. Power Stage Schematic A starting point for design is to estimate the input power based on the output power and the desired full load efficiency. P in + P out h (eq. 1) The maximum input average current, Iin,avg , is calculated next from the input power and the minimum average voltage at the bulk capacitor Vbulk,avg,min . The value of Vbulk,avg,min drives the choice of bulk capacitor based on the rectified peak of the lowest line voltage (Vpeak ). The lower value of Vbulk,avg,min leads to higher currents and puts more burden on the power stage design. Higher value of Vbulk,avg,min requires larger bulk capacitance. I in,avg + P in (eq. 2) V bulk,avg,min One of the ways the bulk capacitor value Cbulk can be calculated is by assuming constant current discharge of the bulk capacitor and is given by the following formula: C bulk + ƪ ǒ I in,avg DV bulk 1 1 @ 1 * @ cos −1 1 * p 2 @ f line DV bulk V peak Ǔƫ (eq. 3) Where, DV bulk * V peak * V min (eq. 4) The typical waveforms of the bulk capacitor ripple and the rectifier input current are depicted in Figure 3. http://onsemi.com 3 AND8461/D If kC is too high, then Vclamp is high too and the voltage peak at drain node is high as well, but the leakage inductance reset time is fast. If kC is too low, the leakage inductance reset is longer and more energy is dissipated. The transformer turns ratio can be calculated as in following equation (the VDSmax derating factor used in the equation is 0.85, it may vary based on internal design guidelines). DVbulk Rectified input voltage with bulk capacitor Vbulk,avg,min V bulk (t) V peak Vmin 0 t t2 t1 k C @ ǒV out ) V f,diodeǓ I ACin (t) N+ IACin ,MAX 0 t T/2 The transformer turns ratio N is defined as: NO sinusoidal input current N+ T Figure 3. Bulk Capacitor Ripple and Rectifier Input Current Vr + D max(DCM) + Vr Vbulk Vr t Figure 4. Drain Voltage Waveform of Q1 When the switching device Q1 is switched on its drain to source voltage is close to 0 V. When Q1 is switched off, the peak voltage VDS,peak between the drain and source of Q1 appears. VDS,peak consists of bulk voltage Vbulk , reflected voltage Vr, and leakage inductance spike voltage Vleak . However, in order to limit this voltage, a clamp circuit is applied that limits the VDS,peak value to sum of Vbulk and Vclamp (plus any overshoot that may appear due to slow reaction of the clamping circuit – typically 20 V for off-line applications). In order for the flyback circuit to function, Vclamp > Vr condition has to be satisfied. The ratio kC , is defined as: kC + V clamp Vr (eq. 9) V r ) V bulk,min V out V bulk,min @ Ǹ 2 @ L prim @ F sw R load,min (eq. 10) Iprim(t) IL,avg Ipeak DI VDS,peak Vclamp Vleak t on Tsw (eq. 8) N The most important design step is to choose the mode of operation DCM or CCM. The CCM mode converter has an advantage in lower conduction losses and lower ac ripple at all components. The DCM mode converter has advantage in smaller primary inductance of the transformer, natural commutation of the secondary rectifier and no presence of the right half plane zero. It means that the design of the feedback loop compensation is simpler using the DCM. In this application, at low line and full load, CCM operation is chosen, but the converter is allowed to go into DCM at higher line and lighter load conditions. t rec toff (eq. 7) N prim V out ) V f,diode D max(CCM) + Vds(t) tleak N sec Based on the transformer turns ratio, the reflected voltage Vr (Equation 8) and the maximum duty ratio Dmax (Equation 9 for CCM, Equation 10 for DCM) can be calculated. The bulk voltage waveform is depicted at the low line condition. Vpeak is the peak value of the bulk capacitor ripple, Vmin is the minimum value of the bulk capacitor ripple and the Vbulk,min is the average value of the bulk capacitor voltage under the low line conditions. The drain voltage waveform during flyback converter operation is shown in Figure 4. VDSmax (eq. 6) 0.85 @ V DSmax * 20 V * V bulk,max IIN,avg toff ton Tsw ton Ivalley Rectified input voltage without bulk capacitor t Figure 5. Primary Current Flowing Though Q1 and Transformer Primary Winding Figure 5 depicts the current in the primary of the transformer (as well as in the power switch Q1) for a CCM flyback converter. An imaginary average value of the shared (eq. 5) Vr http://onsemi.com 4 AND8461/D transformer current reflected to primary winding as IL,avg can be calculated as: I L,avg + I in,avg selection or design of the transformer for flyback converter. The quantity which describes the coupling is the coupling coefficient k. The coupling coefficient k plays a role in transfer function of the transformer by the following formula. (eq. 11) D max Then the relative ripple in the primary winding dIr can be selected. The relative ripple in the primary winding dIr is defined by following formula. DI v sec(t) + k @ (eq. 22) DI + I peak * I valley (eq. 14) L prim,leak + ǒ1 * k 2Ǔ @ L prim (eq. 23) Ǔ 2 (eq. 15) L sec,leak + ǒ1 * k 2Ǔ @ L sec (eq. 24) Ǔ (eq. 16) ǒ dI r ǒ dI r I valley + I L,avg @ 1 * 2 Energy of the leakage magnetic field in the core is physically represented by the current in transformer winding. When the primary switch turns off the current in the Lprim,leak would need a path to flow and it is required to reset this leakage inductance. In simplest (low power, low cost) solutions the energy is dissipated via transient voltage suppressor (TVS) or RCD clamp, which creates additional losses, described by following formula. Knowing the primary current ripple DI, the inductance of transformer primary winding Lprim can be designed using Equation 17. Since these calculations are for full power design, the typical switching frequency should be used even if the frequency is folded back during light load. L prim + V bulk,min @ D max P loss(prim,leak) + (eq. 17) F sw @ DI Ǹ ǒ D max @ I peak 2 * I peak @ DI ) I sec,peak + DI sec + ǒ Ǔ DI 2 3 I peak R DS(on) v (eq. 18) 2 ǒ1 * D maxǓ @ I sec,peak * I sec,peak @ DI sec ) (eq. 19) (eq. 20) Ǔ DI sec 2 3 (eq. 25) P out 40 @ I prim,rms 2 (eq. 26) Other important parameters for the Q1 selection are the maximum primary peak current Ipeak , maximum drain to source voltage VDSmax , the turn-on time ton and turn-off time toff . Next important parameters for the power switch selection are the total gate and drain capacitances which play a role in additional gate charge switching losses and the turn-on losses at drain node. The following formula describes the turn-on losses at drain node of the power switch. N DI N 1 @ L prim,leak @ I peak 2 @ F sw 2 To decrease this type of losses, the Lprim,leak can be decreased by proper transformer selection. Choosing the flyback controller with frequency foldback is another way to decrease the switching losses under the light load conditions. The power switch Q1 is selected by the practical recommendation to have maximum conduction losses in the switching device at 2.5% of the maximum output power. This practical recommendation fulfills low parasitic capacitance and cost effectiveness requirements. Following formula describes this recommendation Once the primary inductance Lprim is designed, the primary transformer can be selected. This can be either a custom design or an off-the-shelf component that closely matches the key specifications derived here. It is important to know the currents through the transformer winding in either case. Following formulas are useful for the primary rms current Iprim,rms , secondary peak current Isec,peak , ripple of the current in secondary winding DIsec and secondary rms current Isec,rms calculations. Ǹ @ v prim(t) (eq. 13) I L,avg I peak + I L,avg @ 1 ) + L prim DI + dI r @ I L,avg (eq. 12) For CCM operation, dIr is chosen in the range of 0.5 to 1. The primary current ripple DI, the peak of the primary current Ipeak and the valley of the primary current Ivalley can be calculated using following formulae: I sec,rms + L sec The coupling coefficient k represents the physical reality that not all the magnetic flux is shared between the primary and secondary windings of the transformer. Some unshared magnetic flux exists on either side − this flux is called leakage flux. The behavior of a real transformer can by described by G model. In the G model, the leakage flux is modeled by leakage inductance. The primary and secondary leakage inductances are given by: dI r + I prim,rms + Ǹ (eq. 21) P loss(switching) + It is important to keep the coupling between the primary and secondary windings as tight as possible during the http://onsemi.com 5 1 @ C DRAIN @ V DRAIN(turn*on) 2 @ F sw 2 (eq. 27) AND8461/D The switching losses also depend on the square of the turn-off voltage on the drain node. Lowering this voltage reduces the losses. The actual value of CDRAIN is non-linear and decreases with the voltage, hence the actual switching losses are lower than predicted by the above equation. The sense resistor is designed for the maximum peak current requirement. The voltage drop across the current sensing resistor should reach the maximum internal current set point VILIM (0.7 V in this case) at slightly above the maximum peak current Ipeak . As shown in the equation below, there is a 10% margin for transformer primary inductance Lprim tolerance and other parameters’ production tolerances to allow whole adapter deliver maximum power under the low line full load conditions. R sense + V ILIM Figure 6. Simplified Schematic of Application Setting the Compensation Networks (eq. 28) 1.1 @ I peak The slope compensation is internally set in the NCP1237 family, but in rare cases, additional slope compensation is needed to prevent subharmonic oscillations in CCM mode operating above 50% duty cycle. See the Reference 3 for the detailed description and modeling of ramp compensation techniques. Without the overpower compensation, the peak current Ipeak,max consists of the components given by the internal current setpoint VILIMIT and the effect of the propagation delay tPROP, between the peak current detection and switching off the power switch. The second component strongly depends on the bulk voltage Vbulk . The power dissipation in the sense resistor is given by: P sense + I prim,rms 2 @ R sense (eq. 29) The secondary rectifier is selected next. The nominal voltage rating for this diode is given by: PIV + V bulk,max @ N ) V out (eq. 30) In reality, there will be additional stress due to parasitic ringing that can be addressed by snubbers. The diode average current is the maximum output dc current Iout . The selected diode has to have a low forward drop to achieve high efficiency and fast and soft recovery for low radiated EMI. It is important to check if the selected diode can withstand the secondary peak current Isec,peak . The output capacitor design is dictated by the output voltage ripple specification. While there are two contributors to this ripple, the capacitive and the resistive element of the capacitor, in most designs, the resistive element (represented by the ESR of the capacitance) dominates by an order of magnitude. The required ESR for a given output ripple is given by: ESR v V out,ripple I peak,max + For selection of output capacitors, it is often cheaper to use more capacitors in parallel to reach the required ESR value than to use a single low ESR capacitor. The capacitance rms current ICout,rms is given by: I Cout,rms + ǸI sec,rms 2 * I out 2 (eq. 32) Finally, the contribution of the capacitive element to the output ripple needs to be verified using following formula: C out uu I out @ D max V out,ripple @ F sw R sense ) V bulk @ t PROP (eq. 34) LP By implementing the overpower compensation, built in the NCP1237/38/87/88 family, the increase of the primary peak current value is compensated by additional voltage offset depending on Vbulk . This offset is created by the internal high voltage sensing circuitry. The internal system is characterized by two parameters: the transconductance gOPP from HV pin voltage to CS pin output current and minimum voltage Voff . The overpower compensation is provided only if the bulk voltage, present on HV pin, is higher than Voff . An external dedicated resistor ROPP is used to set the amount of over power compensation. There is a voltage offset created by the resistor ROPP added to Vsense creating the overpower compensation as a result. The current sourced out of the CS pin is in the direct proportion to the bulk voltage present on the HV pin of the device. Following equation describes the primary peak current value in described system. (eq. 31) I sec,peak V ILIMIT I peak,max + V ILIMIT R sense ) V bulk @ ǒ t PROP (eq. 33) ) V off @ g OPP @ Figure 6 provides the simplified schematic of the application. http://onsemi.com 6 R OPP R sense LP * g OPP @ R OPP Ǔ R sense (eq. 35) AND8461/D The over power compensating resistor can be designed by following formula, designed to zero out the Vbulk contribution from the above equation. R OPP + t PROP @ R sense P clamp + E clamp @ F sw + (eq. 36) L p @ g OPP The RCD clamp works by absorbing the leakage inductance energy into the RCD clamp once the drain voltage exceeds the clamp capacitor voltage. The use of a relatively large capacitor keeps the voltage constant over a switching cycle. The resistor of the RCD clamp always dissipates power. Even with very little load on the converter, the capacitor can be charged up to the voltage reflected from the secondary of the converter Vr. As the load is increased, more energy will flow into the capacitor and the voltage will rise by an additional amount, Vleak , above the ideal square wave flyback voltage. In typical designs, the value of ratio kC is chosen to be 1.5 to obtain fast and proper reset of the leakage inductance (see Equation 5 for the kC definition) In this case, the dissipation is equal to 3 times the stored energy in the leakage inductance. This is a conservative estimate, based on the assumption that all the leakage energy flows into the TVS. It does not account for lossy discharge of the inductor, for stray capacitance, and for losses in the clamping diode. In reality, the design will have less loss in the clamp circuit than anticipated due to these effects. The resistor is the element that is crucial in determining the peak voltage Vclamp and it should be selected using the following equation: Main need of the overpower compensation is for stabilizing the peak current. It works very well in the DCM mode of operation, because the output power Pout depends on the Ipeak value. P out + 1 @ h @ L prim @ F sw @ I peak 2 2 (eq. 37) In CCM, the Ivalley plays a role by following formula. Ivalley decreases the maximum output deliverable power if the Ipeak is kept constant. P out + 1 @ h @ L prim @ F sw @ ǒI peak 2 * I valley 2 Ǔ 2 (eq. 38) The interpretation of this formula is that in the CCM it is not possible to keep a flat characteristic of the maximum output power over a wide range of input voltage with this simple compensating system. The overpower compensation affects the 2nd level over current protection as well. The protection activation limit is shifted by the offset voltage present across overpower compensating resistor ROPP. I tran + V CStran R sense * ǒV bulk * V offǓ @ g OPP @ R OPP R sense 1 @ L leak @ I peak 2 @ F sw @ 2 V clamp (eq. 40) @ V clamp * V r (eq. 39) If the application works in CCM in the range of output power which activates the 2nd level over current protection, the protection activation limit is shifted by the effect of Ivalley as well. It is important to note that the VCS(tran) parameter is not affected, but the 2nd level over current protection output power level is. Use the ON Semiconductor website http://onsemi.com to download the spreadsheet to design the feedback loop compensation. Follow the link: http://www.onsemi.com/ pub/Collateral/FLYBACK DWS.XLS.ZIP R clamp + 2 @ V leak @ V clamp L leak @ I peak 2 @ F sw (eq. 41) The capacitor in the RCD clamp Cclamp needs to be large enough to keep a relatively constant voltage while absorbing the leakage energy. Apart from this consideration, its value is not critical, and will not affect the peak voltage when the snubber is working properly. For efficiency optimization in frequency foldback, the lowest switching frequency needs to be considered. Snubber Networks Design C clamp u A transient voltage suppressor (TVS) can be used for the clamping of the drain voltage excursion when the power switch Q1 is turned off. Select the required TVS based on the Vclamp voltage and check the power dissipation Pclamp as per the equation below. This solution has an advantage during the light load condition. The TVS doesn’t discharge the clamping capacitor in the clamp and the converter does not recharge it from voltage lower than the reflected voltage. This solution allows reaching better efficiency at light load conditions, but has a bad radiated EMI signature due excessive ringing after the transformer leakage inductance reset. This excessive ringing is caused by the residual energy in the clamping circuitry. V clamp V ripple @ R clamp @ F sw (eq. 42) The power dissipation in the resistor element is given by: P clamp + V clamp 2 R clamp (eq. 43) The recommended diode for the RCD clamp is 1N4007. Its long recovery time naturally damps the ringing caused by residual energy stored in leakage inductance after its reset. But there is a need to pay attention to usage of the 1N4007 in CCM under high duty ratio conditions. There is a possibility of cross-conduction that can damage the 1N4007 due to the long reverse recovery time. The 1N4007 will be destroyed at first and subsequently the whole application will fail. http://onsemi.com 7 AND8461/D The Rclamp resistor value in RCD clamp needs to be optimized for the no load consumption and losses in slow clamping diode D2. The optimization lies in measuring the clamping voltage across the clamping capacitor Cclamp under the full load conditions and increasing the Rclamp resistor value, if the Vclamp is too low. There is a difference in ringing (and subsequently in radiated EMI) depending on usage of TVS clamp or the RCD clamp with the “slow” 1N4007. Figures 7 and 8 show the difference in ringing voltages between the two implementations, under the same input voltage and load conditions. The ringing peak to peak voltage is 226 V in case of use the TVS. This high amplitude of ringing is decreased by the usage of RCD clamp, where the ringing peak-to-peak voltage is only 106 V. This approach significantly reduces the EMI noise in frequency band from 1 to 10 MHz. The excessive ringing using the TVS was discussed before and it is caused by the residual energy in clamping circuitry, no presence of resistive damping element and the fast turning off time of the TVS. It is important to note that the measurement was performed with the 160 V TVS P6KE160ARLG from ON Semiconductor and the RCD clamp was originally designed for clamping voltage Vclamp = 115 V. This difference is observable as a higher drain to source peak voltage VDS,peak = 485V when the TVS is used in clamping circuitry compared to drain to source peak voltage of 440V in case of the RCD clamp usage. Figure 8. Ringing at Drain Node when the Drain Voltage is Clamped by RCD Clamp at Full Load (3.5 A) and 230 V/50 Hz Input The RC snubber across the secondary rectifying diode helps to damp the ringing. The transformer secondary leakage inductance may couple with the capacitance Cd of the output rectifier diode in reverse direction to cause ringing when the diode turns off. The transformer secondary leakage inductance Lsec,leak and the parasitic capacitance Cd of the rectifier determine this resonant frequency. The ringing may generate significant radiated and conducted EMI noise. There is typically very little loss in this resonant circuit so the network will cause many cycles of ringing after the spike. The ringing can therefore affect the current sense signal used by the controller in a flyback configuration. The overshoot caused by this ringing may exceed the diode voltage rating and cause damage to the diode. The used RC snubber, however, will absorb energy during each voltage transition and can reduce efficiency. It is recommended to design the Rsnubber the same as the characteristic impedance of the ringing circuitry to damp the oscillations. R snubber + Ǹ L sec,leak (eq. 44) Cd The RC time constant of the snubber should be small compared to the switching period but long compared to the voltage rise time. The snubber capacitance Csnubber must be larger than the parasitic resonance capacitance, but small enough to minimize dissipation in the snubber resistor. The snubber capacitance is generally chosen to be at least 3 to 4 times the value of the parasitic resonant capacitor. Figure 7. Ringing at Drain Node when the Drain Voltage is Clamped by TVS at Full Load (3.5 A) and 230 V/50 Hz Input C snubber [ 3 ³ 4 @ C d http://onsemi.com 8 (eq. 45) AND8461/D It is very important to pay attention to the parasitics in the components used in the snubber since these may render the snubber ineffective. It is a tricky thing to obtain the parasitic capacitance Cd of the secondary rectifier, because it is reverse voltage dependant, nonlinear and can differ from part to part. Hence, the formula above can be treated as the 1st iteration of the design and further optimization can be done empirically for the best damping of the ringing. voltage was chosen 90 V, which does not correspond with the bulk capacitor design, but ensures an advance in the increasing of the power factor under low line conditions and high level of the output loading. Practical Example of the Adapter Design The relative primary current ripple was chosen dIr = 0.62, than: D max + I L,avg + The above theoretical approach to design is applied to the design of a 65 W adapter. The maximum output dc current Iout will be: I out + P out V out + 65 + 3.42 A 19 P out h + ƪ ǒ C bulk + 0.85 100 1 1 @ 1 * @ cos −1 1 * p 2 @ 50 100 124 ƪ ǒ L prim + Ǔƫ (eq. 49) The amount of ripple at bulk capacitor was selected at a high value of 100 V to obtain better input power factor and cheaper bulk capacitor. The value of 47 mF/450 V was chosen. The transformer ratio and reflected voltage is: N+ Vr + 1.5 @ (19 ) 0.6) 0.85 @ 600 * 20 * 375 V out ) V f,diode N + 0.2557 19 ) 0.6 + + 76.65 V 0.2557 V clamp + k c @ V r + 1.5 @ 76.65 + 115 V N aux + V CC ) V f,VCC Vr (eq. 55) dI r ǒ dI r 2 (eq. 56) Ǔ + 2.42 A Ǔ + 1.85 @ ǒ1 ) 0.62 2 (eq. 57) 0.62 Ǔ+ Ǔ + 1.85 @ ǒ1 * 2 2 Ǔ 0.62 + 1.28 A 2 (eq. 58) V bulk,min @ D max F sw @ DI + 90 @ 0.46 65 @ 10 3 @ 1.15 + 553 mH (eq. 59) The converter has been designed for the minimum voltage of 90 V at bulk capacitor. If the voltage across the bulk capacitor drops below the 90 V, the maximum output power cannot be delivered as the peak current limit may be crossed. On the other hand, the advantage of this solution lies in decreasing of instantaneous input power of converter with decreasing of the instantaneous value of input voltage. It is the typical behavior of the power factor correction stages. The behavior as PFC for the low input line and high load condition was reached by the selection of the low value of the bulk capacitor. This solution is a cost effective as well. The energy for the output is provided from the output capacitor tank, while the Vbulk voltage is low and the converter power stage is not able to provide the required power level. Ǔƫ C bulk + 47.75 mF (eq. 54) Knowing the current ripple the basic parameters of flyback transformer can be designed. Using the maximum input power approach the bulk capacitor value is: I in,avg DV bulk 1 1 @ 1 * @ cos −1 1 * p 2 @ f line DV bulk V peak ǒ ǒ (eq. 48) C bulk + 76.65 + 0.46 76.65 ) 90 0.85 + 1.85 A 0.46 + 1.85 @ 1 * The average input current calculation is based on the estimation of the minimum average voltage across the bulk capacitor Vbulk,avg ,min 90 V. 76.5 I in,avg + + + 0.85 A 90 V bulk,avg,min D max + I valley + I L,avg @ 1 ) (eq. 47) P in I in,avg I peak + I L,avg @ 1 ) (eq. 46) 65 + 76.5 W 0.85 + V r ) V bulk,min DI + dI r @ I L,avg + 0.62 @ 1.85 + 1.15 A The maximum input power and average input current are (assuming a full load efficiency of 85%): P in + Vr I prim,rms + (eq. 50) Ǹ ǒ 0.46 @ 2.42 2 * 2.42 @ 1.15 ) I prim,rms + 1.271 A (eq. 51) I sec,peak + (eq. 52) DI sec + 13.8 ) 0.6 + + 0.1879 (eq. 53) 76.65 DI sec,rms + Using results from previous calculation the maximum duty ratio and the average value of shared transformer current reflected to primary winding is calculated in Equations 54 and 55. The design point for minimum bulk I peak N + 9 2.42 + 9.46 A 0.2557 ǒ (1 * 0.46) @ 9.46 2 * 9.46 @ 4.50 ) DI sec,rms + 5.38 A http://onsemi.com (eq. 60) 1.15 DI + + 4.50 A 0.2557 N Ǹ Ǔ 1.15 2 3 (eq. 61) (eq. 62) Ǔ 4.50 2 3 (eq. 63) AND8461/D When the 67 W overpower compensating resistor is used the peak current value Ipeak and the 2nd level over power protection threshold Itran are perfectly flat with the input voltage Vin as shown in Figure 9. A custom transformer (HA3776−AL) was prepared by Coilcraft, which fulfils the calculated requirements. The primary inductance of this transformer is 560 mH and the leakage inductance observed from the primary side of this transformer was measured 5.1 mH. The secondary leakage inductance was measured 210 nH. P out 40 @ I prim,rms 2 + 65 40 @ 1.271 (eq. 64) R DS(on) v 1.01 W The MOSFET chosen was the NDF06N60Z with VDSmax = 600 V and RDS(on) = 0.98 W as optimum type for high efficiency at light loads. R sense + V ILIM 1.1 @ I peak + 0.7 1.1 @ 2.42 A + 262 mW (eq. 65) I sec,peak + 0.200 + 21.1 mW 9.46 1.5 1.0 (eq. 67) 160 + Ǹ5.38 2 * 3.42 2 + 4.15 A 120 0.200 @ 65 @ 10 3 (eq. 68) t PROP @ R sense L p @ g OPP + 200 Vin (V) 250 300 350 400 Pmax 100 + 121 mF (eq. 69) The choice for output capacitor was KOSHIN make 1000 mF/35 V KZH type (KZH−35V102MI6) with impedance of 18 mW at 100 kHz and maximum ripple current 2.77 A at 100 kHz. The output capacitor tank consists of two of these capacitors in parallel. The overpower compensation resistor ROPP can be designed by Equation 36. R OPP + 150 Pmax and Ptran vs. Line Input Voltage 140 Pmax (W), Ptran (W) C out w 3.42 @ 0.46 100 Because the application is running in CCM mode, the effect of valley current Ivalley appears. This behavior is described by Equation 38. The characteristics of maximum output power and transient level output power are not flat and rising as shown in Figure 10. The maximum ESR of the output capacitor tank must be lower than 20 mW for the requirement of 200 mV output voltage ripple. I Cout,rms 50 Figure 9. The Primary Peak Current is Independent on the Bulk Voltage using the Resistor 67 W (eq. 66) V out,ripple Itran 2.0 0.0 0 PIV + V bulk,max @ N ) V out + 375 @ 0.2557 ) 19 ESR v 2.5 0.5 The sense resistor was chosen to be 235 mW which is created from two resistors 0.47 W in parallel. Secondary rectification is provided by a low cost, low drop Schottky diode MBRF20H150. The maximum reverse voltage across the diode is 115 V. PIV + 115 V Ipeak,max 3.0 2 Ipeak,max (A), Itran (A) R DS(on) v Ipeak,max and Itran vs. Line Input Voltage 3.5 80 @ 10 −9 @ 0.235 Ptran 80 60 40 20 0 0 50 100 150 200 Vin (V) 250 300 350 400 Figure 10. The Maximum Output Power is Rising if there is Used the Resistor 67 W + 67 W 560 @ 10 −6 @ 0.5 @ 10 −6 (eq. 70) This relationship is valid for the DCM mode, for CCM, a higher value has to be used. http://onsemi.com 10 AND8461/D For better over power compensation, the designed value must be increased to decrease the peak current Ipeak with the increasing input voltage. The final resistor value used was 680 W which gives a good overpower compensation, but the peak current value and Ipeak,max and the 2nd level over power protection threshold Itran decreases with increase of the input voltage Vin . R clamp + 2 @ V leak @ V clamp L leak @ I peak 2 @ F sw + 2 @ (115 * 76.65) @ 115 5.1 @ 10 −6 @ 2.42 2 @ 65 @ 10 3 R clamp + 4543 W C clamp u (eq. 71) V clamp V ripple @ R clamp @ F sw + 115 10 @ 4543 @ 25 @ 10 3 Ipeak,max and Itran vs. Line Input Voltage C clamp + 101 nF 3.5 Ipeak,max Ipeak,max (A), Itran (A) 3.0 Note that the clamp capacitor is designed for lowest switching frequency under the frequency foldback. Because a slow and soft diode 1N4007 was used in RCD clamp, some power was lost in the diode and the components with calculated values behave like preload. After the empirical optimization the values were set to Rclamp = 165 kW and Cclamp = 5.6 nF. The optimization lies in setting the proper clamp voltage Vclamp at full load conditions. The clamping capacitor is set under the light load conditions for it not to be fully discharged. 2.5 Itran 2.0 1.5 1.0 0.5 0.0 0 50 100 150 200 Vin (V) 250 300 350 R snubber + 400 Figure 11. The Primary Peak Current is Decreasing with the Bulk Voltage Increase using the Resistor 680 W Ptran 120 Pmax (W), Ptran (W) Pmax 40 20 50 100 150 200 Vin (V) Cd + 210 @ 10 Ǹ550 @ 10 −9 −12 + 19.5 W (eq. 73) The efficiency and no-load input power consumption were measured by the YOKOGAWA WT210 wattmeter. However, a significant error appeared during the no-load input power measurement due to high input reactive power of the input EMC filter (5−8 VAR dependent on the ac line voltage). This effect caused an error from 50% to 100% at read value of no load input power. To overcome this issue, no load consumption was measured by the dc method as a dc current between the ac rectifier and the bulk capacitor. The measurement was done 2 minutes after switching on the power supply to eliminate the influence of the bulk capacitor polarization current. The consumption of the X capacitor discharge resistors RD1, RD2 and RD3 was added numerically to measured values. For the dc measurement 162.6 V was set as a peak value corresponding to 115 V line voltage and 325.3 V as a peak value for 230 V line voltage. The connected ammeter and whole application should be floating to avoid any additional ground currents. It is recommended to use battery supplied ammeter or classical electromechanical dc ammeter system. 60 0 0 L sec,leak Performance of the Designed 65 W Notebook Adapter 100 80 Ǹ The diode capacitance in reverse direction was measured 550 pF at 10 V of reverse voltage at frequency of 1 MHz. Based on this measurement and calculation the RC snubber elements were chosen at 1.2 nF and 15 W after the final optimization. Pmax and Ptran vs. Line Input Voltage 140 (eq. 72) 250 300 350 400 Figure 12. The Maximum Output Power is Quite Well Compensated in CCM Mode in Range 150 V to 375 V The second level overpower compensation timer can be activated by the reaching the VCS(tran) limit, because there exists an excessive bulk capacitor ripple under the low line conditions. This behavior can be improved by selection of bulk capacitor with higher capacitance value. The components of RCD clamping network are designed as follows: http://onsemi.com 11 AND8461/D Table 1. EFFICIENCY VERSUS OUTPUT POWER AND INPUT LINE VOLTAGE Notebook adapter load regulation 18.65 Vin = 115 Vac / 60 Hz 18.64 Pout (W) Pin (W) Efficiency (%) 100.7 65.44 77.15 84.82 75.1 48.80 56.71 86.04 50.3 32.66 37.95 86.07 25.5 16.55 19.09 86.69 10.1 6.53 7.70 84.82 4.9 3.20 3.81 83.93 1.5 0.98 1.27 76.99 Vout @ 230V/50Hz 18.63 Vout (V) Pout/Poutmax (%) 18.62 Vout @ 115V/60Hz 18.61 18.60 0.0 Pout (W) Pin (W) Efficiency (%) 100.7 65.48 76.61 86.60 75.1 48.81 56.82 85.91 1.0 1.5 2.0 2.5 3.0 3.5 Iout (A) Vin = 230 Vac / 50 Hz Pout/Poutmax (%) 0.5 Figure 14. Load Regulation for Low and High Input line Notebook adapter line regulation 32.67 38.68 84.47 25.5 16.56 19.76 83.78 18.64 10.1 6.53 8.08 80.82 18.62 4.9 3.19 4.07 78.46 1.5 0.97 1.38 70.66 Vout [V] 50.3 18.66 18.60 18.58 Table 2. AVERAGE EFFICIENCY AND NO LOAD INPUT POWER Input Line 115 Vac / 60 Hz 230 Vac / 50 Hz Average Efficiency (%) 85.9 85.2 No Load Input Power (W) 67.5 94.2 18.56 18.54 90 110 130 Notebook adapter efficiency Efficiency 85.0% 80.0% 75.0% 70.0% 65.0% 30.0% 40.0% 50.0% 60.0% 70.0% 80.0% 90.0% 100.0% Pout/Poutmax Efficiency @ 115V/60Hz 210 230 250 270 290 Vout @ Iout 3.0 A Vout @ Iout 3.2A Vout @ Iout 3.5A It is interesting to observe the “waves” in the efficiency curves in range from 5% to 40% of loading. These waves are caused by different turning on voltages at drain node, if the controller switches in the valley of the drain voltage in the DCM mode the efficiency of the adapter is higher and if the controller switches in the peak the total efficiency decreases. Following figures demonstrate the operation of the converter under different operating conditions and highlight various features such as transition from CCM to DCM, frequency foldback, pulse skipping, transient load response, stability in CCM, frequency jitter, overload protection etc. under both 115 V and 230 V input conditions as appropriate. 90.0% 20.0% 190 Figure 15. Line Regulation for High Output Loads. The Output Voltage Drops for Low Input Line Voltage due the Activation of 2nd Level Overcurrent Protection. See Figure 12. 95.0% 10.0% 170 VinAC [V] Vout @ Iout 2.5 A 60.0% 0.0% 150 Efficiency @ 230V/50Hz Figure 13. Efficiency vs Output Power and Input Line Voltage http://onsemi.com 12 AND8461/D Figure 16. CCM Operation at Full Load (3.5 A) and 115 V/60 Hz Figure 17. Ripple at Bulk Capacitor at Full Load (3.5 A) and 115 V/60 Hz Figure 18. No Subharmonic Oscillations Appear under Full Load (3.5 A) and CCM Operation, with D > 50%, 110 V/45 Hz Figure 19. The DCM Mode Starts at 1.5 A of Load Current at 115 V/60 Hz Input Figure 20. The Frequency Foldback Mode Starts at 1.3 A of Load Current at 115 V/60 Hz Input Figure 21. The Lowest Frequency at 0.25 A of Load Current at 115 V/60 Hz Input – Frequency Foldback is Finished http://onsemi.com 13 AND8461/D Figure 22. The Skip Mode at 0.23 mA of Load Current at 115 V/60 Hz Input Figure 23. CCM Operation at Full Load (3.5 A) and 230 V/50 Hz Input Figure 24. The DCM Mode Starts at 2.3 A of Load Current at 230 V/50 Hz Input Figure 25. The Frequency Foldback Mode Starts at 1.3 A of Load Current at 230 V/50 Hz Input Figure 26. The Lowest Frequency at 0.23 A of Load Current at 230 V/50 Hz Input – Frequency Foldback is Finished Figure 27. The Load Transient Step from 20% of Load to 100% of Load at 115 V/60 Hz Input http://onsemi.com 14 AND8461/D Figure 28. The Load Transient Step from 100% of Load to 20% of Load at 115 V/60 Hz Input Figure 29. The Overcurrent Protection Timer Duration is 83 ms when the Adapter was Overloaded to 5.5 A at 115 V/60 Hz Input Figure 30. The Transient Protection Timer Duration is 161 ms when the Adapter was Overloaded to 4.0 A at 115 V/60 Hz Input Figure 31. Adapter Start Up at 115 V/60 Hz Input and 1 A Output Current Load Figure 32. Brown Out Protection Reaction when the rms ac Input Voltage Steps Down from 80 V to 74 V under 1 A Output Current Loading Figure 33. The Soft Start at 115 V/60 Hz Input with 3.5 A Output Current Loading http://onsemi.com 15 AND8461/D Results Summary The family of controllers NCP1237/38/87/88 allows building of cost effective, easy-to-design and low no load input power consumption power supplies. The 2nd level overcurrent protection feature offers the advantage of designing power supplies whose peak output power can be almost 2 times higher than the maximum continuous output power. For example it allows the design of cheap transformers, but at peak power loading condition, the efficiency will decrease due the conduction losses of flyback stage transformer. The designed wide input range adapter fulfils the requirement of having no load input power lower than 100 mW over the wide input voltage range. While the complete design of the adapter must be oriented to gain the low no load input power, the controller facilitates this result by frequency foldback feature. The frequency foldback starts at load current lower than 1.3 A (34% of the maximum power) in this design. The frequency foldback finishes at 0.23 A (6% of the maximum power ) in case of high line condition (230 V/50 Hz) or at 0.25 A in case of low line condition (115 V/60 Hz). The controller enters the skip mode feature if the loading current of the adapter is lower than 0.21 A in case of high line condition (230 V/50 Hz) or 0.18 A in case of low line condition (115 V/60 Hz). This loading level is approximately 5.5% of the maximum output power. Measured efficiency at 1.5% of output power is higher than 70%. The obtained average efficiency is 85.9% for the low line condition (115 V/60 Hz) and 85.2% at high line conditions (230 V/50 Hz) for this adapter design. There is still room for the efficiency optimization e.g. by reducing losses across the secondary rectifying diode, the total Q1 losses or reducing the losses by different design of the transformer. The goal of this design is to show the low no load input power solution which is cost effective as well. Figure 34. Frequency Deviation of the Frequency Jittering Figure 35. Ripple at Bulk Capacitor at 88 V/50 Hz Input and 3 A Continuous Output Loading Current. See the Full Duty Cycle Operation and Lower Peak current Thanks I would like to thank the COILCRAFT Company for provided samples, custom design of the flyback transformer used in this board and the support. I would also like to thank the EPCOS Company for providing the samples of the input EMI filters. Caution This demo board is intended for demonstration and evaluation purposes only and not for the end customer. Figure 36. Detail of the Output Voltage Ripple and Voltage across Secondary Winding of Transformer at 115 V/60 Hz Input with 3.5 A Output Current Loading (the ringing is caused by the secondary diode reverse recovery) http://onsemi.com 16 AND8461/D Figure 37. Photograph of the Designed Prototype (Real Dimensions are 143 x 57.6 mm) Pb L1 Czech Design Center 2 1 2 1 NCP1238B65NBGEVB Figure 38. Component Placement on the Top Side (Top View) http://onsemi.com 17 AND8461/D R14 R17 C8 C3 D10 R25 R24 R6 R2 C11 R5 R4 R3 R26 C2 D12 IC1 R1 D6 C9 C4 C1 R15 RD3 D7 D9 R23 Figure 39. Component Placement on the Bottom Side (Bottom View) Figure 40. Bottom Side (Bottom View) http://onsemi.com 18 RD1 RD2 AND8461/D Table 3. BILL OF MATERIALS FOR THE NCP1237 DEMO BOARD Designator Qty Description Value Tolerance Footprint Manufacturer Manufacturer Part Number C1, C2 2 Ceramic Capacitor 100nF 10% 1206 Kemet C1206C104K5RAC C3 1 Ceramic Capacitor 33 nF 10% 1206 Kemet C1206C333K5RAC C4, C11 2 Ceramic Capacitor 1.0 nF 10% 1206 Kemet C1206C102K5RAC C5 1 Ceramic Capacitor 1.2 nF/630 V 5% Radial TDK Corporation FK26C0G2J122J C6 1 Electrolytic Capacitor 47 mF/50 V 20% Radial Koshin KLH−050V470ME110 C7 1 Ceramic Capacitor 5.6 nF/500 V 10% Disk − Radial Panasonic ECK−D2H562KBE C8, C9 0 Ceramic Capacitor NU − 1206 − − CB1 1 Electrolytic Capacitor 47 mF/450 V 20% Radial United Chemi−Con EKXG451ELL470MM25S COUT1, COUT2 2 Electrolytic Capacitor 1000 mF/35 V 20% Radial Koshin KZH−035V102MH250 COUT3 1 Electrolytic Capacitor 220 mF/35 V 20% Radial Koshin KZH−035V221MG125 CX1, CX2 2 Foil Capacitor 330 nF/X2 10% Radial Epcos B32922C3334K CY1, CX3, CX4 3 Ceramic Capacitor 2.2 nF/X1/Y1 20% Disc − Radial Murata DE1E3KX222MA5B D1 1 Dual Schottky Diode MBRF20H150 − TO−220 ON Semiconductor MBRF20H150CTG D2, D3, D4, D5, D8, D11 6 Diode 1N4007 − DO41−10B ON Semiconductor 1N4007G D6, D12 2 Diode SMA MRA4007 − SMA ON Semiconductor MRA4007T3G D7, D10 2 Diode SMD MMSD4143 − SOD123 ON Semiconductor MMSD4148T3G D9 2 Zener diode MMSZ15 5% SOD123 ON Semiconductor MMSZ15T3G F1 1 Fuse 1.25 A 1.2 A − Radial Bel Fuse Inc RST 1.25 HS1, HS2 2 Heatsink SK 104 B − SK 104 B Fischer Elektronik SK 104 B IC1 1 SMPS Controller NCP1237B65 − SOIC−08 ON Semiconductor NCP1237BD65R2G L1 1 EMI filter 2 x 22 mH 1 A − − Epcos B82732W2102B30 L2 1 Inductor 47 mH 10% DR0810 Coilcraft DR0810−473L L3 1 Inductor 10 mH 10% DR0810 Coilcraft DR0810−103L LED1 0 Indicating LED NU − LED 3 mm − − NTC 1 Sensing NTC Thermistor 330 kW 5% Disc − Radial Vishay NTCLE100E3334JB0 OK1 1 Optocoupler PC817 − 4−DIP Sharp PC817X2J000F Q1 1 N channel MOS FET NDF06N60ZG − TO−220 ON Semiconductor NDF10N60ZG R1 1 Resistor SMD 680 W 1% 1206 Rohm MCR18EZPF6800 R2 1 Resistor SMD 22 W 1% 1206 Rohm MCR18EZHF22R0 R3 1 Resistor SMD 2.2 kW 1% 1206 Rohm MCR18EZHF2201 R4 1 Resistor SMD 3.9 kW 1% 1206 Rohm MCR18EZHF3901 R5 1 Resistor SMD 6.2 kW 1% 1206 Rohm MCR18EZHF6201 R6 1 Resistor SMD 8.2 kW 1% 1206 Rohm MCR18EZHF8201 R7, R13 2 Resistor Through Hole 330 kW 1% 207 Vishay HVR2500003303FR500 http://onsemi.com 19 AND8461/D Table 3. BILL OF MATERIALS FOR THE NCP1237 DEMO BOARD Designator Qty Description Value Tolerance Footprint Manufacturer Manufacturer Part Number R8 1 Resistor Through Hole 15 W 1% 207 Vishay CMF5015R000FHEB R9, R10 2 Resistor Through Hole 0.47 W 1% 207 Vishay PAC100004707FA1000 R11 1 Surge protecting NTC B57235S509M 20% Disc − Radial Epcos B57235S509M R12 1 Varistor 275 V − Disc − Radial Vishay VDRS05C175BSE R14 1 Resistor SMD 10 kW 1% 1206 Vishay MCR18EZHF1002 R15 1 Resistor SMD 33 kW 1% 1206 Vishay MCR18EZHF3302 R17 0 Resistor SMD NU − 1206 − − R18 1 Resistor Through Hole 5.1 kW 1% 207 Vishay SFR2500005101FR500 R22 1 Resistor Through Hole 2.2 W 1% 207 Vishay MBA02040C2208FRP00 R23, R26 2 Resistor SMD 2.2 W 1% 1206 Rohm MCR18EZHFL2R20 R24, R25 2 Resistor SMD 1.0 kW 1% 1206 Rohm MCR18EZHF1001 R27 1 Resistor Through Hole, High Voltage 4.7 MW 5% Axial Lead Welwyn VRW37−4M7JI RD1, RD2, RD3 3 Resistor SMD 1.0 MW 1% 1206 Rohm MCR18EZHF1004 TR1 1 Transformer HA3776−AL − HA3776−AL Coilcraft HA3776−AL WAGO1 1 Terminal Block, 3 Way CTB5000/3 − W237−113 Cadem El. CTB5000/3 References [4] Application note AN1679/D, (onsemi.com) [5] Application note AND8393/D, (onsemi.com) [6] Application note AND8154/D, (onsemi.com) [1] NCP1237A/B datasheet, (onsemi.com) [2] Christophe P. Basso: Switch−Mode Power Supplies, SPICE Simulations and Practical Designs, McGraw−Hill, new York, 2008 [3] Dr. Ray Ridley: A New Continuous−Time Model for Current−Mode Control, (www.ridleyengineering.com/cmode.htm) ENERGY STAR and the ENERGY STAR mark are registered U.S. marks. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 20 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative AND8461/D

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