mc33365 - High Voltage Switching Regulator

MC33365
High Voltage Switching
Regulator
The MC33365 is a monolithic high voltage switching regulator that
is specifically designed to operate from a rectified 240 Vac line source.
This integrated circuit features an on−chip 700 V/1.0 A SENSEFETt
power switch, 450 V active off−line startup FET, duty cycle controlled
oscillator, current limiting comparator with a programmable threshold
and leading edge blanking, latching pulse width modulator for double
pulse suppression, high gain error amplifier, and a trimmed internal
bandgap reference. Protective features include cycle−by−cycle current
limiting, input undervoltage lockout with hysteresis, bulk capacitor
voltage sensing, and thermal shutdown. This device is available in a
16−lead dual−in−line package.
• On−Chip 700 V, 1.0 A SENSEFET Power Switch
• Rectified 240 Vac Line Source Operation
• On−Chip 450 V Active Off−Line Startup FET
• Latching PWM for Double Pulse Suppression
• Cycle−By−Cycle Current Limiting
• Input Undervoltage Lockout with Hysteresis
• Bulk Capacitor Voltage Comparator
• Trimmed Internal Bandgap Reference
• Internal Thermal Shutdown
http://onsemi.com
MARKING
DIAGRAM
16
PDIP−16
P SUFFIX
CASE 648E
16
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
Startup Input
1
VCC
3
AC Input
Startup Input
MC33365P
AWLYYWW
16
4
13
5
12
RT
6
11
CT
7
10
Regulator Output
8
9
1
Gnd
Gnd
Regulator
Output
Startup
Mirror
VCC
Reg
3
8
6
BOK
BOK
RT
CT
DC Output
UVLO
PWM Latch
Osc
7
Driver
S
Q
11
16
Ipk
Power Switch
Drain
LEB
Compensation
Thermal
BOK
Voltage Feedback
Input
Compensation
(Top View)
R
PWM
Power Switch
Drain
ORDERING INFORMATION
Device
Package
Shipping
MC33365P
PDIP−16
25 Units/Rail
9
EA
Gnd
4, 5, 12, 13
10
Voltage
Feedback
Input
Figure 1. Simplified Application
© Semiconductor Components Industries, LLC, 2010
December, 2010− Rev. 5
1
Publication Order Number:
MC33365/D
MC33365
MAXIMUM RATINGS
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Rating
Power Switch (Pin 16)
Drain Voltage
Drain Current
Symbol
Value
Unit
VDS
IDS
700
1.0
V
A
Startup Input Voltage (Pin 1, Note 1)
Pin 3 = Gnd
Pin 3 ≤ 1000 μF to ground
Vin
Power Supply Voltage (Pin 3)
VCC
40
V
Input Voltage Range
Voltage Feedback Input (Pin 10)
Compensation (Pin 9)
Bulk OK Input (Pin 11)
RT (Pin 6)
CT (Pin 7)
VIR
−1.0 to Vreg
V
Thermal Characteristics
P Suffix, Dual−In−Line Case 648E
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
V
400
500
°C/W
RθJA
RθJC
80
15
Operating Junction Temperature
TJ
−25 to +125
°C
Storage Temperature
Tstg
−55 to +150
°C
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 μF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies, unless otherwise noted.)
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Symbol
Min
Typ
Max
Unit
Output Voltage (IO = 0 mA, TJ = 25°C)
Vreg
5.5
6.5
7.5
V
Line Regulation (VCC = 20 V to 40 V)
Regline
−
30
500
mV
Load Regulation (IO = 0 mA to 10 mA)
Regload
−
44
200
mV
Vreg
5.3
−
8.0
V
Characteristic
REGULATOR (Pin 8)
Total Output Variation over Line, Load, and Temperature
OSCILLATOR (Pin 7)
Frequency
CT = 390 pF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
CT = 2.0 nF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
fOSC
kHz
260
255
285
−
310
315
60
59
67.5
−
75
76
ΔfOSC/ΔV
−
0.1
2.0
kHz
VFB
2.52
2.6
2.68
V
Line Regulation (VCC = 20 V to 40 V, TJ = 25°C)
Regline
−
0.6
5.0
mV
Input Bias Current (VFB = 2.6 V, TJ = 0 − 125°C)
IIB
−
20
500
nA
Open Loop Voltage Gain (TJ = 25°C)
AVOL
70
82
94
dB
Gain Bandwidth Product (f = 100 kHz, TJ = 25°C)
GBW
0.85
1.0
1.15
MHz
Output Voltage Swing
High State (ISource = 100 μA, VFB < 2.0 V)
Low State (ISink = 100 μA, VFB > 3.0 V)
VOH
VOL
4.0
−
5.3
0.2
−
0.35
Frequency Change with Voltage (VCC = 20 V to 40 V)
ERROR AMPLIFIER (Pins 9, 10)
Voltage Feedback Input Threshold
V
1. Maximum power dissipation limits must be observed.
http://onsemi.com
2
MC33365
ELECTRICAL CHARACTERISTICS (continued) (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin
8 = 1.0 μF, for typical values
TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies, unless otherwise noted.)
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Characteristic
Symbol
Min
Typ
Max
Unit
Input Threshold Voltage
Vth
1.18
1.25
1.32
V
Input Bias Current (VBK < Vth, TJ = 0 − 125°C)
IIB
−
100
500
nA
Source Current (Turn on after VBK > Vth, TJ = 25°C − 125°C)
ISC
39
−
53
μA
DC(max)
DC(min)
48
−
50
0
52
0
−
−
15
−
17
39
−
0.2
100
BULK OK (Pin 11)
PWM COMPARATOR (Pins 7, 9)
Duty Cycle
Maximum (VFB = 0 V)
Minimum (VFB = 2.7 V)
%
POWER SWITCH (Pin 16)
Drain−Source On−State Resistance (ID = 200 mA)
TJ = 25°C
TJ = −25°C to +125°C
RDS(on)
Drain−Source Off−State Leakage Current
VDS = 650 V
ID(off)
Ω
μA
Rise Time
tr
−
50
−
ns
Fall Time
tf
−
50
−
ns
Ilim
0.5
0.72
0.9
A
−
−
2.0
2.0
4.0
4.0
OVERCURRENT COMPARATOR (Pin 16)
Current Limit Threshold (RT = 10 k)
STARTUP CONTROL (Pin 1)
Peak Startup Current (Vin = 400 V) (Note 2)
VCC = 0 V
VCC = (Vth(on) − 0.2 V)
Istart
mA
Off−State Leakage Current (Vin = 50 V, VCC = 20 V)
ID(off)
−
40
200
μA
Vth(on)
11
15.2
18
V
VCC(min)
7.5
9.5
11.5
V
−
−
0.25
3.2
0.5
5.0
UNDERVOLTAGE LOCKOUT (Pin 3)
Startup Threshold (VCC Increasing)
Minimum Operating Voltage After Turn−On
TOTAL DEVICE (Pin 3)
Power Supply Current
Startup (VCC = 10 V, Pin 1 Open)
Operating
ICC
mA
f OSC , OSCILLATOR FREQUENCY (Hz)
1.0 M
CT = 100 pF
I PK, POWER SWITCH PEAK DRAIN CURRENT (A)
2. The device can only guarantee to start up at high temperature below +115°C.
VCC = 20 V
TA = 25°C
500 k C = 200 pF
T
200 k CT = 500 pF
100 k CT = 1.0 nF
50 k
20 k
CT = 2.0 nF
CT = 5.0 nF
CT = 10 nF
10 k
7.0
10
15
20
30
50
70
RT, TIMING RESISTOR (kΩ)
1.0
0.8
VCC = 20 V
CT = 1.0 μF
TA = 25°C
0.6
0.4
0.3
0.2
0.15
0.1
7.0
Inductor supply voltage and inductance value are
adjusted so that Ipk turn-off is achieved at 5.0 μs.
10
15
20
30
40
50
RT, TIMING RESISTOR (kΩ)
Figure 3. Power Switch Peak Drain Current
versus Timing Resistor
Figure 2. Oscillator Frequency
versus Timing Resistor
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3
70
Dmax, MAXIMUM OUTPUT DUTY CYCLE (%)
MC33365
VCC = 20 V
TA = 25°C
0.5
0.3
0.2
0.15
0.1
10
15
20
50
30
50
40
RC/RT Ratio
Charge Resistor
Pin 6 to Vreg
30
1.0
2.0
3.0
5.0
7.0
RT, TIMING RESISTOR (kΩ)
TIMING RESISTOR RATIO
Figure 4. Oscillator Charge/Discharge
Current versus Timing Resistor
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor Ratio
100
VCC = 20 V
VO = 1.0 to 4.0 V
RL = 5.0 MΩ
CL = 2.0 pF
TA = 25°C
80
Gain
60
0
30
60
Phase
40
90
20
120
0
150
-20
10
VCC = 20 V
CT = 2.0 nF
TA = 25°C
RD/RT Ratio
Discharge Resistor
Pin 6 to Gnd
60
70
θ, EXCESS PHASE (DEGREES)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
0.08
7.0
70
100
1.0 k
10 k
100 k
180
10 M
1.0 M
Vsat , OUTPUT SATURATION VOLTAGE (V)
I chg /I dscg , OSCILLATOR
CHARGE/DISCHARGE CURRENT (mA)
0.8
0
Source Saturation
(Load to Ground)
-1.0
2.0
Sink Saturation
(Load to Vref)
VCC = 20 V
TA = 25°C
1.0
Gnd
0
0
0.2
0.4
0.6
0.8
IO, OUTPUT LOAD CURRENT (mA)
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 7. Error Amp Output Saturation
Voltage versus Load Current
1.75 V
VCC = 20 V
AV = -1.0
CL = 10 pF
TA = 25°C
3.00 V
20 mV/DIV
1.80 V
Vref
-2.0
f, FREQUENCY (Hz)
VCC = 20 V
AV = -1.0
CL = 10 pF
TA = 25°C
1.75 V
0.50 V
1.70 V
1.0 μs/DIV
1.0 μs/DIV
Figure 8. Error Amplifier Small Signal
Transient Response
Figure 9. Error Amplifier Large Signal
Transient Response
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4
10
1.0
0
2.0
-20
I pk , PEAK STARTUP CURRENT (mA)
VCC = 20 V
RT = 10 k
CPin 8 = 1.0 μF
TA = 25°C
-40
-60
-80
VPin 1 = 400 V
TA = 25°C
1.0
Pulse tested with an on-time of 20 μs to 300 μs
at < 1.0% duty cycle. The on-time is adjusted at
Pin 1 for a maximum peak current out of Pin 3.
0
0
4.0
8.0
12
16
0
20
8.0
10
12
Figure 11. Peak Startup Current
versus Power Supply Voltage
24
16
8.0
Pulse tested at 5.0 ms with < 1.0% duty cycle
so that TJ is as close to TA as possible.
-25
0
25
50
75
100
125
14
160
VCC = 20 V
TA = 25°C
120
80
40
0
1.0
150
COSS measured at 1.0 MHz with 50 mVpp.
10
100
1000
TA, AMBIENT TEMPERATURE (°C)
VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 12. Power Switch Drain−Source
On−Resistance versus Temperature
Figure 13. Power Switch
Drain−Source Capacitance versus Voltage
3.2
100
Rθ JA , THERMAL RESISTANCE
JUNCTION-TO-AIR (° C/W)
CT = 390 pF
I CC, SUPPLY CURRENT (mA)
6.0
Figure 10. Regulator Output Voltage
Change versus Source Current
ID = 200 mA
CT = 2.0 nF
2.4
1.6
RT = 10 k
Pin 1 = Open
Pin 4, 5, 10, 11,
12, 13 = Gnd
TA = 25°C
0.8
0
4.0
VCC, POWER SUPPLY VOLTAGE (V)
32
0
-50
2.0
Ireg, REGULATOR SOURCE CURRENT (mA)
COSS, DRAIN-SOURCE CAPACITANCE (pF)
R DS(on), DRAIN-SOURCE ON-RESISTANCE (Ω )
Δ V reg, REGULATOR VOLTAGE CHANGE (mV
MC33365
0
10
20
30
L = 12.7 mm of 2.0 oz. copper.
Refer to Figure 15.
10
1.0
0.01
40
0.1
1.0
10
VCC, SUPPLY VOLTAGE (V)
t, TIME (s)
Figure 14. Supply Current versus Supply Voltage
Figure 15. P Suffix Transient Thermal
Resistance
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5
100
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
R θ JA, THERMAL RESISTANCE
JUNCTION-TO-AIR (° C/W)
100
Printed circuit board heatsink example
80
L
RθJA
60
2.0 oz
Copper
L
3.0 mm
Graphs represent symmetrical layout
40
4.0
3.0
2.0
PD(max) for TA = 70°C
20
0
5.0
0
10
20
1.0
30
40
0
50
P D , MAXIMUM POWER DISSIPATION (W)
MC33365
L, LENGTH OF COPPER (mm)
Figure 16. P Suffix (DIP−16) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
PIN FUNCTION DESCRIPTION
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Pin
Function
Description
1
Startup Input
This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the
drain of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and
charges an external capacitor that connects from the VCC pin to ground.
2
−
3
VCC
This is the positive supply voltage input. During startup, power is supplied to this input from
Pin 1. When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is
supplied from an auxiliary transformer winding.
4, 5, 12, 13
Gnd
These pins are the control circuit grounds. They are part of the IC lead frame and provide a
thermal path from the die to the printed circuit board.
6
RT
Resistor RT connects from this pin to ground. The value selected will program the Current Limit
Comparator threshold and affect the Oscillator frequency.
7
CT
Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor
RT, programs the Oscillator frequency.
8
Regulator Output
9
Compensation
10
Voltage Feedback
Input
11
BOK
14, 15
−
16
Power Switch Drain
This pin has been omitted for increased spacing between the rectified ac line voltage on Pin 1
and the VCC potential on Pin 3.
This 6.5 V output is available for biasing external circuitry. It requires an external bypass
capacitor of at least 1.0 μF for stability.
This pin is the Error Amplifier output and is made available for loop compensation. It can be used
as an input to directly control the PWM Comparator.
This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter
output.
This is the non−inverting input of the bulk capacitor voltage comparator. It has an input threshold
voltage of 1.25V. This pin is connected through a resistor divider to the bulk capacitor line
voltage.
These pins have been omitted for increased spacing between the high voltages present on the
Power Switch Drain, and the ground potential on Pins 12 and 13.
This pin is designed to directly drive the converter transformer and is capable of switching a
maximum of 700 V and 1.0 A.
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6
MC33365
AC Input
Startup Input
Startup
Control
Current
Mirror
Regulator Output
6.5 V
8
Band Gap
Regulator
I
VCC
3
UVLO
2.25 I
14.5 V/
9.5 V
6
RT
CT
1
DC Output
BOK
11
4I
1.25 V
Oscillator
7
16
PWM Latch
Power Switch
Drain
Driver
S
Q
R
PWM
Comparator
Leading Edge
Blanking
8.1
Thermal
Shutdown
Current Limit
Comparator
Compensation
405
9
270 μA
Gnd
Error
Amplifier
2.6 V
10
Voltage
Feedback Input
4, 5, 12, 13
Figure 17. Representative Block Diagram
2.6 V
Capacitor CT
0.6 V
Compensation
Oscillator
Output
PWM
Comparator
Output
PWM Latch
Q Output
Current Limit
Propagation
Delay
Power Switch
Gate Drive
Current
Limit
Threshold
Leading Edge
Blanking Input
(Power Switch
Drain Current)
Normal PWM Operating Range
Figure 18. Timing Diagram
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7
Output Overload
MC33365
OPERATING DESCRIPTION
Introduction
The formula for the charge/discharge current along with
the oscillator frequency are given below. The frequency
formula is a first order approximation and is accurate for CT
values greater than 500 pF. For smaller values of CT, refer to
Figure 2. Note that resistor RT also programs the Current
Limit Comparator threshold.
The MC33365 represents a new higher level of integration
by providing all the active high voltage power, control, and
protection circuitry required for implementation of a
flyback or forward converter on a single monolithic chip.
This device is designed for direct operation from a rectified
240 Vac line source and requires a minimum number of
external components to implement a complete converter. A
description of each of the functional blocks is given below,
and the representative block and timing diagrams are shown
in Figures 17 and 18.
Ichgńdscg + 5.4
RT
The pulse width modulator consists of a comparator with
the oscillator ramp voltage applied to the non−inverting
input, while the error amplifier output is applied into the
inverting input. The Oscillator applies a set pulse to the
PWM Latch while CT is discharging, and upon reaching the
valley voltage, Power Switch conduction is initiated. When
CT charges to a voltage that exceeds the error amplifier
output, the PWM Latch is reset, thus terminating Power
Switch conduction for the duration of the oscillator ramp−up
period. This PWM Comparator/Latch combination
prevents multiple output pulses during a given oscillator
clock cycle. The timing diagram shown in Figure 18
illustrates the Power Switch duty cycle behavior versus the
Compensation voltage.
The oscillator frequency is controlled by the values
selected for the timing components RT and CT. Resistor RT
programs the oscillator charge/discharge current via the
Current Mirror 4 I output, Figure 4. Capacitor CT is charged
and discharged by an equal magnitude internal current
source and sink. This generates a symmetrical 50 percent
duty cycle waveform at Pin 7, with a peak and valley
threshold of 2.6 V and 0.6 V respectively. During the
discharge of CT, the oscillator generates an internal blanking
pulse that holds the inverting input of the AND gate Driver
high. This causes the Power Switch gate drive to be held in
a low state, thus producing a well controlled amount of
output deadtime. The amount of deadtime is relatively
constant with respect to the oscillator frequency when
operating below 1.0 MHz. The maximum Power Switch
duty cycle at Pin 16 can be modified from the internal 50%
limit by providing an additional charge or discharge current
path to CT, Figure 19. In order to increase the maximum duty
cycle, a discharge current resistor RD is connected from
Pin 7 to ground. To decrease the maximum duty cycle, a
charge current resistor RC is connected from Pin 7 to the
Regulator Output. Figure 5 shows an obtainable range of
maximum output duty cycle versus the ratio of either RC or
RD with respect to RT.
1.0
Current Limit Comparator and Power Switch
The MC33365 uses cycle−by−cycle current limiting as a
means of protecting the output power switch from
overstress. Each on−cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch current buildup during conduction, and upon sensing
an overcurrent condition, immediately turning off the switch
for the duration of the oscillator ramp−up period.
The Power Switch is constructed as a SENSEFET
allowing a virtually lossless method of monitoring the drain
current. It consists of a total of 1462 cells, of which 36 are
connected to a 8.1 Ω ground−referenced sense resistor. The
Current Sense Comparator detects if the voltage across the
sense resistor exceeds the reference level that is present at
the inverting input. If exceeded, the comparator quickly
resets the PWM Latch, thus protecting the Power Switch.
The current limit reference level is generated by the 2.25 I
output of the Current Mirror. This current causes a reference
voltage to appear across the 405 Ω resistor. This voltage
level, as well as the Oscillator charge/discharge current are
both set by resistor RT. Therefore when selecting the values
for RT and CT, RT must be chosen first to set the Power
Switch peak drain current, while CT is chosen second to set
the desired Oscillator frequency. A graph of the Power
Switch peak drain current versus RT is shown in Figure 3
with the related formula below.
Current
Mirror
8
2.25 I
I
RC
Current
Limit
Reference
6
RT
4I
RD
CT
7
Oscillator
Ichgńdscg
4CT
PWM Comparator and Latch
Oscillator and Current Mirror
Regulator Output
f[
Blanking
Pulse
PWM
Comparator
I
Figure 19. Maximum Duty Cycle Modification
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8
pk
+ 8.8
ǒ Ǔ
R
T − 1.077
1000
MC33365
The Power Switch is designed to directly drive the converter
transformer and is capable of switching a maximum of
700 V and 1.0 A. Proper device voltage snubbing and
heatsinking are required for reliable operation.
A Leading Edge Blanking circuit was placed in the current
sensing signal path. This circuit prevents a premature reset
of the PWM Latch. The premature reset is generated each
time the Power Switch is driven into conduction. It appears
as a narrow voltage spike across the current sense resistor,
and is due to the MOSFET gate to source capacitance,
transformer interwinding capacitance, and output rectifier
recovery time. The Leading Edge Blanking circuit has a
dynamic behavior in that it masks the current signal until the
Power Switch turn−on transition is completed. The current
limit propagation delay time is typically 262 ns. This time is
measured from when an overcurrent appears at the Power
Switch drain, to the beginning of turn−off.
VBULK
Vref
RUpper
BOK
11
Undervoltage Lockout
An Undervoltage Lockout comparator has been
incorporated to guarantee that the integrated circuit has
sufficient voltage to be fully functional before the output
stage is enabled. The UVLO comparator monitors the VCC
voltage at Pin 3 and when it exceeds 14.5 V, the reset signal
is removed from the PWM Latch allowing operation of the
Power Switch. To prevent erratic switching as the threshold
is crossed, 5.0 V of hysteresis is provided.
Startup Control
An internal Startup Control circuit with a high voltage
enhancement mode MOSFET is included within the
MC33365. This circuitry allows for increased converter
efficiency by eliminating the external startup resistor, and its
associated power dissipation, commonly used in most
off−line converters that utilize a UC3842 type of controller.
Rectified ac line voltage is applied to the Startup Input,
Pin 1. This causes the MOSFET to enhance and supply
internal bias as well as charge current to the VCC bypass
capacitor that connects from Pin 3 to ground. When VCC
reaches the UVLO upper threshold of 15.2 V, the IC
commences operation and the startup MOSFET is turned
off. Operating bias is now derived from the auxiliary
transformer winding, and all of the device power is
efficiently converted down from the rectified ac line.
The startup MOSFET will provide a steady current of
1.7 mA, Figure 11, as VCC increases or shorted to ground.
The startup MOSFET is rated at a maximum of 400 V with
VCC shorted to ground, and 500 V when charging a VCC
capacitor of 1000 μF or less.
Bulk Capacitor Voltage Comparator
In order to avoid output voltage bouncing during
electricity brownout condition, a Bulk Capacitor Voltage
Comparator with programmable hysteresis is included in
this device. The non−inverting input, pin 11, is connected to
the voltage divider comprised of RUpper and RLower as
shown in Figure 20 monitoring the bulk capacitor voltage
level. The inverting input is connected to a threshold voltage
of 1.25 V internally. As bulk capacitor voltage drops below
the pre−programmed level, (Pin 11 drops below 1.25 V), a
reset signal will be generated via internal protection logic to
the PWM Latch so turning off the Power Switch
immediately. An internal current source controlled by the
state of the comparator provides a means to program the
voltage hysteresis. The following equation shows the
relationship between VBULK levels and the voltage divider
network resistors.
25
[ VBulk_H * VBulk_L ]
RLower +
VBulk_H * 1.25
Protection Logic
Figure 20. Bulk OK Functional Operation
An fully compensated Error Amplifier with access to the
inverting input and output is provided for primary side
voltage sensing, Figure 17. It features a typical dc voltage
gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with
78 degrees of phase margin, Figure 6. The noninverting
input is internally biased at 2.6 V ±3.1% and is not pinned
out. The Error Amplifier output is pinned out for external
loop compensation and as a means for directly driving the
PWM Comparator. The output was designed with a limited
sink current capability of 270 μA, allowing it to be easily
overridden with a pull−up resistor. This is desirable in
applications that require secondary side voltage sensing.
[ VBulk_H * VBulk_L ]
1.25 V
RLower
Error Amplifier
RUpper + 20
50 mA
Regulator
A low current 6.5 V regulated output is available for
biasing the Error Amplifier and any additional control
system circuitry. It is capable of up to 10 mA and has
in K Ohm
in K Ohm
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9
MC33365
The MC33365 is contained in a heatsinkable plastic
dual−in−line package in which the die is mounted on a
special heat tab copper alloy lead frame. This tab consists of
the four center ground pins that are specifically designed to
improve thermal conduction from the die to the circuit
board. Figure 16 shows a simple and effective method of
utilizing the printed circuit board medium as a heat
dissipater by soldering these pins to an adequate area of
copper foil. This permits the use of standard layout and
mounting practices while having the ability to halve the
junction to air thermal resistance. The examples are for a
symmetrical layout on a single−sided board with two ounce
per square foot of copper.
short−circuit protection. This output requires an external
bypass capacitor of at least 1.0 μF for stability.
Thermal Shutdown and Package
Internal thermal circuitry is provided to protect the Power
Switch in the event that the maximum junction temperature
is exceeded. When activated, typically at 150°C, the Latch
is forced into a ‘reset’ state, disabling the Power Switch. The
Latch is allowed to ‘set’ when the Power Switch temperature
falls below 140°C. This feature is provided to prevent
catastrophic failures from accidental device overheating. It
is not intended to be used as a substitute for proper
heatsinking.
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10
MC33365
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
CASE 648E−01
ISSUE O
−A−
R
16
M
9
L
−B−
1
8
P
J
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
P
R
S
−T−
SEATING
PLANE
S
G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION A AND B DOES NOT INCLUDE MOLD
PROTRUSION.
5. MOLD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.25 (0.010).
6. ROUNDED CORNER OPTIONAL.
K
H
D 13 PL
0.25 (0.010)
M
T B
S
A
INCHES
MIN
MAX
0.740
0.760
0.245
0.260
0.145
0.175
0.015
0.021
0.050
0.070
0.100 BSC
0.050 BSC
0.008
0.015
0.120
0.140
0.295
0.305
0_
10 _
0.200 BSC
0.300 BSC
0.015
0.035
MILLIMETERS
MIN
MAX
18.80
19.30
6.23
6.60
3.69
4.44
0.39
0.53
1.27
1.77
2.54 BSC
1.27 BSC
0.21
0.38
3.05
3.55
7.50
7.74
0_
10 _
5.08 BSC
7.62 BSC
0.39
0.88
S
SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC33365/D