NCP336 D

NCP336, NCP337
3 A Ultra-Small Controlled
Load Switch with
Auto-Discharge Path
Description
http://onsemi.com
The NCP336 and NCP337 are very low Ron MOSFET controlled
by external logic pin, allowing optimization of battery life, and
portable device autonomy.
Indeed, thanks to a current consumption optimization with PMOS
structure, leakage currents are eliminated by isolating connected IC on
the battery when not used.
Output discharge path is also embedded to eliminate residual
voltages on the output rail for the NCP337 part only.
Proposed in a wide input voltage range from 1.2 V to 5.5 V, in a
small 1 x 1.5 mm WLCSP6, pitch 0.5 mm.
WLCSP6
FC SUFFIX
CASE 567FH
PIN CONNECTIONS
1
2
A
OUT
IN
B
OUT
IN
C
GND
EN
Features
•
•
•
•
•
•
•
1.2 V − 5.5 V Operating Range
21 mW P MOSFET at 4.5 V
DC Current up to 3 A
Output Auto−Discharge
Active High EN Pin
WLCSP6 1 x 1.5 mm
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
(Top View)
Applications
•
•
•
•
•
Mobile Phones
Tablets
Digital Cameras
GPS
Portable Devices
VCC
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
V+
LS
NCP336 or NCP337
C2
1μF
ENy
IN
IN
EN
OUT
OUT
GND
A2
B2
or
LDO
A1
B1
Platform IC’n
100n
C1
SMPS
DCDC Converter
ENx
0
LS
Platform IC’n+1
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 2
1
Publication Order Number:
NCP336/D
NCP336, NCP337
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
Pin Number
Type
Description
IN
A2, B2
POWER
Load−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND
as close as possible to the IC.
GND
C1
POWER
Ground connection.
EN
C2
INPUT
OUT
A1, B1
OUTPUT
Enable input, logic high turns on power switch.
Load−switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as
possible to the IC is recommended.
Figure 2. Block Diagram
http://onsemi.com
2
NCP336, NCP337
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VEN, VIN, VOUT
−0.3 to + 7.0
V
VIN, VOUT
0 to + 7.0
V
TJ
−40 to + 125
°C
Storage Temperature Range
TSTG
−40 to + 150
°C
Moisture Sensitivity (Note 2)
MSL
Level 1
IN, OUT, EN, Pins: (Note 1)
From IN to OUT Pins: Input/Output (Note 1)
Maximum Junction Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. OPERATING CONDITIONS
1.
2.
3.
4.
Symbol
Parameter
VIN
Operational Power Supply
VEN
Conditions
Max
Unit
1.2
5.5
V
Enable Voltage
0
5.5
TA
Ambient Temperature Range
−40
25
+85
°C
TJ
Junction Temperature Range
−40
25
+125
°C
CIN
Decoupling input capacitor
1
mF
COUT
Decoupling output capacitor
1
mF
RqJA
Thermal Resistance Junction to Air
IOUT
Maximum DC current
PD
Power Dissipation Rating (Note 4)
WLCSP package (Note 3)
Typ
100
°C/W
3
A
TA ≤ 25°C
WLCSP package
0.66
W
TA = 85°C
WLCSP package
0.26
W
According to JEDEC standard JESD22−A108.
Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
The RqJA is dependent of the PCB heat dissipation and thermal via.
The maximum power dissipation (PD) is given by the following formula:
PD +
Min
T JMAX * T A
R qJA
http://onsemi.com
3
NCP336, NCP337
Table 4. ELECTRICAL CHARACTERISTIC Min & Max Limits apply for TA between −40°C to +85°C for VIN between 1.2 V to 5.5 V
(Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 5 V (Unless otherwise noted).
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
mW
POWER SWITCH
RDSON
Static drain−source
on−state resistance
Rdis
Output discharge path
VIH
High−level input voltage
VIL
Low−level input voltage
Rpd
EN pull down resistor
Vin = 5.5 V
I = 1 A (Note 5)
20
22
Vin = 4.5 V
I = 500 mA (Note 5)
21
25
Vin = 3.3 V
I = 500 mA (Note 5)
23
28
Vin = 2.5 V
I = 500 mA (Note 5)
28
35
Vin = 1.8 V
I = 250 mA (Note 5)
40
45
Vin = 1.2 V
TA = 25°C, I = 200 mA
95
120
70
90
EN = low
W
V
0.9
0.5
5
MW
QUIESCENT CURRENT
Istd
Standby current
Vin = 4.2 V
EN = low, No load
1
mA
Iq
Quiescent current
Vin = 4.2 V
EN = high, No load
1
mA
TEN
Enable time
RL = 25 W, Cout = 1 mF
323
TR
Output rise time
Vin = 3.6 V
(Note 6)
RL = 25 W, Cout = 1 mF
810
TON
ON time (TEN + TR)
RL = 25 W, Cout = 1 mF
1130
TF
Output fall time
NCP337. RL = 25 W, Cout = 1 mF
42
TIMINGS
5. Guaranteed by design and characterization
6. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground
TIMINGS
Vin
EN
Vout
TEN
TR
TDIS
TON
TOFF
Figure 3. Enable, Rise and Fall Time
http://onsemi.com
4
TF
ms
NCP336, NCP337
TYPICAL CHARACTERISTICS
Figure 4. Rdson (mW) vs. Vin (V)
Figure 5. Rdson (mW) vs. Iload (A)
Figure 6. Rdson (mW) vs. Temperature (5C) at 100 mA
Figure 7. Rdson (mW) vs. Temperature (5C) at 3 A
http://onsemi.com
5
NCP336, NCP337
TYPICAL CHARACTERISTICS
Figure 8. Standby (mA) and Leakage Current (mA)
vs. Vin (V)
Figure 9. Standby Current (mA) vs.
Temperature (5C)
Figure 10. Leakage Current (mA) vs.
Temperature (5C)
Figure 11. Quiescent Current (mA) vs.
Temperature (5C)
http://onsemi.com
6
NCP336, NCP337
Figure 12. Enable Time and Rise Time
Figure 13. Disable Time and Fall Time
FUNCTIONAL DESCRIPTION
Overview
Auto Discharge
The NCP337 is a high side P channel MOSFET power
distribution switch designed to isolate ICs connected on the
battery in order to save energy. The part can be turned on,
with a wide range of battery from 1.2 V to 5.5 V.
NMOS FET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
The auto−discharge is activated when EN pin is set to low
level (disable state).
The discharge path (Pull down NMOS) stays activated as
long as EN pin is set at low level and Vin > 1.2 V.
In order to limit the current across the internal discharge
Nmosfet, the typical value is set at 70 W.
Enable Input
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing P MOS switch off.
The IN/OUT path is activated with a minimum of Vin of
1.2 V and EN forced to high level.
Cin and Cout Capacitors
IN and OUT, 1 mF, at least, capacitors must be placed as
close as possible the part to for stability improvement.
http://onsemi.com
7
NCP336, NCP337
APPLICATION INFORMATION
• TJ = PD x RqJA + TA
Power Dissipation
Main contributor in term of junction temperature is the
power dissipation of the power MOSFET. Assuming this,
the power dissipation and the junction temperature in
normal mode can be calculated with the following
equations:
• PD = RDS(on) x (IOUT)2
PD = Power dissipation (W)
RDS(on) = Power MOSFET on resistance (W)
IOUT = Output current (A)
TJ = Junction temperature (°C)
RqJA = Package thermal resistance (°C/W)
TA = Ambient temperature (°C)
PCB Recommendations
The NCP337 integrates an up to 3 A rated PMOS FET, and
the PCB design rules must be respected to properly evacuate
the heat out of the silicon. By increasing PCB area,
especially around IN and OUT pins, the RqJA of the package
can be decreased, allowing higher power dissipation.
Figure 14. Routing Example: 2 oz, 4 layers with vias across 2 internal inners.
Example of application definition.
T J * T A + R qJA
P D + R qJA
R DS(on)
I
At 3 A, 25°C ambient temperature, RDS(on) 20 mW @ Vin
5 V, the junction temperature will be:
2
TJ + TA ) Rq
TJ: junction temperature.
TA: ambient temperature.
Rq = Thermal resistance between IC and air, through PCB.
RDS(on): intrinsic resistance of the IC Mosfet.
I: load DC current.
3 2)
P D + 25 ) (0.024
100 + 43 oC
Taking into account of Rq obtain with:
• 2 oz, 4 layers: 60°C/W.
At 3 A, 65°C ambient temperature, RDS(on) 24 mW @ Vin
5 V, the junction temperature will be:
Taking into account of Rq obtain with:
• 1 oz, 2 layers: 100°C/W.
TJ + TA ) Rq
P D + 65 ) (0.024
3 2)
60 + 78 oC
ORDERING INFORMATION
Device
Marking
Option
Package
Shipping†
NCP337FCT2G
AC
Auto discharge
WLCSP 1 x 1.5 mm
3000 Tape / Reel
NCP336FCT2G
AF
Without Autodischarge
WLCSP 1 x 1.5 mm
3000 Tape / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
8
NCP336, NCP337
PACKAGE DIMENSIONS
WLCSP6, 1.00x1.50
CASE 567FH
ISSUE O
ÈÈ
ÈÈ
D
PIN A1
REFERENCE
2X
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
E
DIM
A
A1
A2
b
D
E
e
0.05 C
2X
0.05 C
TOP VIEW
A2
MILLIMETERS
MIN
MAX
0.54
0.63
0.22
0.28
0.33 REF
0.29
0.34
1.00 BSC
1.50 BSC
0.50 BSC
0.05 C
A
RECOMMENDED
SOLDERING FOOTPRINT*
0.05 C
NOTE 3
A1
SIDE VIEW
C
SEATING
PLANE
A1
PACKAGE
OUTLINE
eD/2
6X
eD
b
0.05 C A B
eE
C
0.50
PITCH
0.03 C
B
A
6X
0.50
PITCH
0.25
DIMENSIONS: MILLIMETERS
1 2 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP336/D