ZL70101 Medical Implantable RF Transceiver Short Form Data Sheet Features Ordering Information 402-405 MHz (10 MICS channels) and 433-434 MHz (2 ISM channels) ZL70101LDG1A • High data rate (800/400/200 kbps raw data rate) • High performance MAC with automatic error handling and flow control, typ < 1.5x10-10 BER. • Very few external components (3 pcs + antenna matching) • Extremely low power consumption (5 mA, continuous TX / RX, 1 mA low power mode) • Ultra low power wakeup circuit (250 nA) • Standards compatible (MICS, FCC, IEC) 48 pin QFN*, for base stations** (trays, bake and drypack) die, implantable grade (trays and drypack) 48 pin QFN*, for evaluation only** (not available in volume) ZL70101UBJ ZL70101LDG1 - * Pb Free Matte Tin ** Not for implantable use Description The ZL70101 is a high performance half duplex RF communications link for medical implantable applications. Applications • Implantable Devices e.g., Pacemakers, ICD’s, Neurostimulators, Implantable Insulin Pumps, Bladder Control Devices, implantable physiological monitors • Body area network, short range device applications using the 433 MHz ISM band. The system is very flexible and supports several low power wakeup options. Extremely low power is achievable using the 2.45 GHz ISM Band Wakeupreceiver option. The high level of integration includes a Media Access Controller, providing complete control of the device along with coding and decoding of RF messages. A standard SPI interface provides for easy access by the application. Zarlink MICS Transceiver - ZL70101 XTAL1 XTAL2 24 MHz 400 MHz Transceiver ADC analog Inputs (TESTIO [4:1] pins) 4 Media Access Controller To ADC Mux PLL RS Encoder Whitening Power Amplifier Message Storage tx_data RF 400 MHz TX RF_TX CRC Generation Mixer TX IF Modulator + tx_clk TX Control Peak Detectors 5 Analog Inputs 4 MATCH1 MATCH2 5bit ADC 3 DataBus RSSI Control Mixer Linear Amplifier RF_RX RF 400 MHz RX ADC RX RS Decode Clock Recovery CRC Decode Message Storage 2 Test Mode Control Regulator 1.9 - 2.0V ULP Osc RF 2.45 GHz RX Input Pin Pull-down Control Bypass of on-chip Crystal Oscillator Control Regulator 1.9 - 2.0V Wake-Up Control Select IMD or Base Transceiver Wakeup IMD Select one or two regulators VSSD VDDA Decoupling Capacitors 68nF VDDIO Battery or Other Supply VSUP VSSA 2 Analog Test TESTIO[6:5] RX_245 SPI Interface Correlator RX IF Filter and FM Detector 2.45 GHz Wake-Up Receiver Programmable IO IRQ RX Control rx_data PO[4:0] PI[2:0] SPI_CS_B SPI_CLK SPI_SDI SPI_SDO Interface SPI Matching nework VDDD • December 2009 68nF Figure 1 - ZL70101 Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2007-2009, Zarlink Semiconductor Inc. All Rights Reserved. MODE[1:0] PDCTR XO_BYPASS L IBS WU_EN VREG_MODE ZL70101 1.0 ZL70101 Functional Description 1.1 General Short Form Data Sheet The ZL70101 is an ultra low power, high bandwidth RF link for medical implantable applications. It operates in the MICS (Medical Implant Communication Service) at 402-405 MHz. It uses a Reed-Solomon coding scheme together with CRC error detection to achieve an extremely reliable link. For data-blocks, a maximum BER (Bit Error Rate) of less than 1.5x10-10 is provided assuming a raw radio channel quality of 10-3 BER. An even higher quality of 2x10-14 BER is available using housekeeping messages, a facility fully described in the ZL70101 Design Manual. 1.2 Basic Operation and Modes The ZL70101 transceiver is intended for operation in both an implant and base station. These systems have different requirements especially with regard to power consumption. Therefore, the ZL70101 transceiver has defined two fundamental startup modes of operation: • Implantable Medical Device (IMD) Mode • Base Mode When configured as an IMD, the transceiver is usually asleep and in a very low current state. The IMD may be woken up to initiate communications by using a 2.45 GHz link or directly by the IMD processor via the WU_EN pin. This flexibility leads to the following options for waking up an IMD transceiver for communication. • IMD transceiver woken up by specially coded 2.45 GHz wakeup message using an ultra low power sniffing method. • IMD transceiver woken up to sniff 400 MHz link. The ZL70101 supports such a mode of operation although the 2.45 GHz wakeup system has lower power consumption. • IMD transceiver woken to send an emergency message in which case no clear channel assessment by the Basestation is required. • IMD transceiver woken up by a low frequency inductive link (as typically used in pacemakers/ICDs) or some alternative mechanism. 2 Zarlink Semiconductor Inc. ZL70101 2.0 Short Form Data Sheet Example Configurations 68 nF VD D A2 To VSUP (m ain supply) VSSD VSSD VDD D VREG_M ODE VSSD 1 VSU P VD DIO R X_245A SPI_SDI VSSA_W AKE_LN A ZL70101 (Bare Die) M ATCH 1 VSSA _M ATC H M ATCH 2 VSSA_G EN1 PO4 VSSD 7 SPI_SDO SPI_C LK R F_TX VSSD 2 R F_R X VSSD 3 SPI_C S_B VSSA_R F_LNA VSSD VSSD TESTIO4 TESTIO3 TESTIO2 TESTIO1 XTAL2 IRQ XTAL1 VSSA_RF_XO VSSA_GEN4 VSSA_GEN3 CLF_REF CLF2 CLF1 VSSD TESTIO[6] VSSD 8 TESTIO[5] W U_EN NC VSSA_RF_VCO VSSA_GEN 2 VSSD Application Interface PD C TRL* VSSA_R F_PA Exam ple of m atching network for a patch antenna . See the D esign M anual for design guidance . MODE1* MODE0* PI2* VSSD6 PI1* PI0* PO3 VSSD4 PO2 PO1 VSSD10 PO0 VSSD5 IBS* XO_BYPASS VSSA VSSD9 VSSD C 1, note 3 VD DA (internal regulator) VDDA1 The ZL70101 Transceiver device is configurable as an implant transceiver or as a base station transceiver. Typical configurations are shown in the following diagrams. Two different configurations for implants are shown, the first is optimized for few external components and the second is optimized for highest performance. 24 M H z Note 1: *Inputs connected via internal pull -dow n to ground . U pper side pins do not need to be bonded out Note 2: Two supply voltages are required , VSU P (the m ain supply , 2.1-3.5V ) and VDD IO (the digital IO voltage w hich m ay be 1.5V to VSU P ). VDD A is an on -chip derived regulated supply created by a voltage regulator connected to the VDD A 1 and VD DA 2 pads. VD DA requires a 68 nF decoupling capacitor and a connection betw een VD D D and VDD A 2. VREG _M ODE is bonded to VD D IO in this exam ple (only the VD DA voltage regulator enabled ). N ote 3: C 1 is an optional D C blocking capacitor . Figure 2 - ZL70101 Transceiver Configured for an Implant - Minimum External Components 3 Zarlink Semiconductor Inc. VDDA2 To VSUP (main supply) VREG_MODE VSUP SPI_SDI ZL70101 (Bare Die) MATCH1 VSSA_MATCH MATCH2 VSSA_GEN1 PO4 VSSD7 SPI_SDO SPI_CLK RF_TX VSSD2 VSSA_RF_PA Application Interface PDCTRL* RF_RX VSSD3 VSSA_RF_LNA SPI_CS_B VSSD VSSD TESTIO4 TESTIO3 TESTIO2 TESTIO1 XTAL2 IRQ XTAL1 VSSA_RF_XO VSSA_GEN4 VSSA_GEN3 CLF_REF CLF2 CLF1 TESTIO[6] VSSD8 TESTIO[5] WU_EN NC VSSA_RF_VCO VSSA_GEN2 VSSD 68 nF VDDIO VSSA_WAKE_LNA VSSD VDDD (internal regulator) VSSD1 RX_245A Example of matching network for a patch antenna using Match1 and Match2 tuning capacitors. VSSD VSSD VDDD VSSA C1, note 3 MODE1* MODE0* PI2* VSSD6 PI1* PI0* PO3 Short Form Data Sheet VSSD4 PO2 PO1 VSSD10 PO0 VSSD5 IBS* 68 nF XO_BYPASS VSSD9 VSSD VDDA (internal regulator) VDDA1 ZL70101 24 MHz Note 1: *Inputs connected via internal pull -down to ground. Upper side pins do not need to be bonded out Note 2: Two supply voltages are required VSUP (the main supply,2.1-3.5V) and VDDIO (the digital IO voltage which may be 1.5V to VSUP) VDDA and VDDD are both on -chip derived regulated supplies . VDDA and VDDD require two separate 68 nF decoupling capacitors . VREG _MODE is bonded to GND in this example (both analog and digital voltage regulators enabled ). Note 3: C1 is an optional DC blocking capacitor . Note 4: The matching network is using the on -chip tuning capacitor arrays to GND (VSSA_MATCH) available on the Match 1 and Match2 pads. Figure 3 - ZL70101 Transceiver Configured for an Implant - Optimal Performance 4 Zarlink Semiconductor Inc. ZL70101 2.45 GHz Transmitter Short Form Data Sheet TX245 To Application Interface (optional) TX_MODE 68nF To VSUP (main supply) MODE1* PI2* MODE0* PI1* PI0* PO3 VSSD PO2 PO1 PO0 IBS* VSSA VDDA (internal regulator) XO_BYPASS To VDDIO VSSD VDDD (internal regulator) VDDA VDDD VSUP VDDIO 68nF VSSA SPI_SDI RX_245A ZL70101 QFN48 MATCH1 VSSA_MATCH MATCH2 PDCTRL* VSSD WU_EN TESTIO4 TESTIO3 TESTIO2 TESTIO1 XTAL2 IRQ XTAL1 VSSA_RF_LNA VSSA_RF_XO RF_RX CLF_REF Matching network dependent on antenna VSSD SPI_CS_B CLF1 SAW SPI_CLK RF_TX TESTIO[5] LNA VSSA_RF_PA VSSA_RF_VCO LPF TESTIO[6] Switch SPI_SDO TCXO (Note1) ADC BPF To Processor RSSI External RSSI / Note 2 Note 1: For Basestation, a TCXO is recommended (in which case XO_BYPASS is tied high) Note 2: External RSSI Detector System is recommended. Connection to be done either to MICS chip after RSSI or direct to application Note 3: Two supply voltages are required VSUP (the main supply,2.1-3.5V) and VDDIO (the digital IO voltage which may be 1.5V to VSUP) VDDA and VDDD are both on -chip derived regulated supplies. VDDA and VDDD require two separate 68 nF decoupling capacitors. VREG_MODE is bonded to GND inside the QFN package in this example (both analog and digital voltage regulators enabled ). Figure 4 - ZL70101 Transceiver Configured for a Base Station 5 Zarlink Semiconductor Inc. Application Interface ZL70101 3.0 Mechanical Characteristics 3.1 48 pin QFN Package Short Form Data Sheet Metal ground post should be grounded Figure 5 - 48 pin QFN Dimensions 6 Zarlink Semiconductor Inc. ZL70101 4.0 Short Form Data Sheet Electrical Characteristics Absolute Maximum ratings - Voltages are with respect to ground (VSS) unless otherwise stated. Parameter Symbol Min. Max. Unit Notes 1 Supply voltage VSUP 0 3.6 V 2 Input voltage (Digital IO) VDDIO 0 VSUP Vpeak rel. to VSS 3 Unpowered Storage temperature Tstg -40 +125 °C Recommended Operating Conditions - Note1 Parameter Symbol Min. Typ. Max. Unit 4 Supply voltage VSUP 2.1 3.5 V 5 Input voltage (Digital IO) VDDIO 1.5 VSUP V 6 Operating temperature Top 0 55 °C Notes Note 2 Note 1: This table lists the external conditions under which the chip shall operate according to the specifications. Note 2: Note that VDDIO must never be higher than VSUP even during system startup. 7 Zarlink Semiconductor Inc. ZL70101 5.0 Additional Information 5.1 Quality Short Form Data Sheet Zarlink’s QA procedures are based on MIL-PRF-38535 and MIL-STD 833. ZL70101 can be delivered either as dies (ZL70101UBJ) or in a QFN package (ZL70101LDG1A), see ordering information on Page 1 for further details. The dies are suitable for implantable application but can also be used for non-implantable applications and base station applications. The QFN devices are only for non-implantable applications and base station applications. The same chip is used for bare die and in the QFN packaged device. The QFN package and the assembly process are not qualified for implantable applications. The QFN devices can therefore not be used in implantable applications. 5.2 Technical Documentation A Full Data sheet and a Design Manual are available for ZL70101. Please contact Zarlink for more information. 8 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE