PLDM7

PLDM7 Series TTL Logic 3-Bit Programmable Delay Modules
Electrical Specifications at 25OC
Error ref.
3-Bit TTL
Delay per
to 000
Part Number Step (ns)
(ns)
PLDM7-1
1.0 ± .4
± .50
PLDM7-1.2
1.2 ± .4
± .60
PLDM7-1.25
1.25 ± .5
± .70
PLDM7-1.3
1.3 ± .5
± .70
PLDM7-1.5
1.5 ± .5
± .70
PLDM7-1.8
1.8 ± .6
± .80
PLDM7-1.9
1.9 ± .7
± .80
PLDM7-2
2.0 ± .7
± .80
PLDM7-2.5
2.5 ± .7
± .90
PLDM7-2.6
2.6 ± .7
± .90
PLDM7-3
3.0 ± .7
± 1.0
PLDM7-5
5.0 ± 1.0
± 1.5
PLDM7-8
8.0 ± 1.2
± 2.5
PLDM7-10
10.0 ± 1.5
± 3.0
Initial
Delay (ns)
000
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)
000
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
001
1.0
1.2
1.3
1.3
1.5
1.8
1.9
2.0
2.5
2.6
3.0
5.0
8.0
10.0
010
2.0
2.4
2.5
2.6
3.0
3.6
3.8
4.0
5.0
5.2
6.0
10.0
16.0
20.0
011
3.0
3.6
3.8
3.9
4.5
5.4
5.7
6.0
7.5
7.8
9.0
15.0
24.0
30.0
100
4.0
4.8
5.0
5.2
6.0
7.2
7.6
8.0
10.0
10.4
12.0
20.0
32.0
40.0
101
5.0
6.0
6.3
6.5
7.5
9.0
9.5
10.0
12.5
13.0
15.0
25.0
40.0
50.0
110
6.0
7.2
7.5
7.8
9.0
10.8
11.4
12.0
15.0
15.6
18.0
30.0
48.0
60.0
111
7.0
8.4
8.8
9.1
10.5
12.6
13.3
14.0
17.5
18.2
21.0
35.0
56.0
70.0
PLDM4 Series FAST Logic 3-Bit Programmable Delay Modules
Electrical Specifications at 25OC
Error ref.
3-Bit FAST
Delay per
to 000
Part Number Step (ns)
(ns)
PLDM4-0.5
0.5 ± .25
± .30
PLDM4-0.7
0.7 ± .30
± .40
PLDM4-0.8
0.8 ± .30
± .50
PLDM4-1
1.0 ± .4
± .50
PLDM4-1.2
1.2 ± .4
± .60
PLDM4-1.25
1.25 ± .5
± .70
PLDM4-1.3
1.3 ± .5
± .70
PLDM4-1.5
1.5 ± .5
± .70
PLDM4-1.8
1.8 ± .6
± .80
PLDM4-2
2.0 ± .7
± .80
PLDM4-2.5
2.5 ± .7
± .90
PLDM4-2.6
2.6 ± .7
± .90
PLDM4-3
3.0 ± .7
± 1.0
Initial
Delay (ns)
000
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)
000
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
001
0.5
0.7
0.8
1.0
1.2
1.25
1.3
1.5
1.8
2.0
2.5
2.6
3.0
010
1.0
1.4
1.6
2.0
2.4
2.50
2.6
3.0
3.6
4.0
5.0
5.2
6.0
011
1.5
2.1
2.4
3.0
3.6
3.75
3.9
4.5
5.4
6.0
7.5
7.8
9.0
CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays
referenced to Initial Delay, Setting "0000." For example the setting "111" delay of
PLDM7-10 is 70.0 ± 3.0ns ref. to "000," and 77.0 ± 4.0ns referenced to the input.
100
2.0
2.8
3.2
4.0
4.8
5.00
5.2
6.0
7.2
8.0
10.0
10.4
12.0
P1
P2
P3
16
11
10
9
3-Bit Programmable
Delay Line
.020
(0.51)
TYP.
.100
(2.54)
TYP.
.050
(1.27)
TYP.
Specifications subject to change without notice.
Rhombus
Industries Inc.
Output
Buffer
4
5
7
8
IN
OUT
E
GND
INPUT FAN-IN: Input, pin 4, is loaded by the internal passive
network and 8 gate inputs (74S/74F type). The source driving Pin
4 should be 74S/74F type or equivalent, and should not be used
to drive any load other than the delay line input.
.260 .300
(6.60) (7.62)
TYP. MAX.
.120
(3.05)
MIN.
111
3.5
4.9
5.6
7.0
8.4
8.75
9.1
10.5
12.6
14.0
17.5
18.2
21.0
FAST / TTL 3-Bit 16-Pin Schematic
Dimensions in Inches (mm)
.400
(10.16)
MAX.
110
3.0
4.2
4.8
6.0
7.2
7.50
7.8
9.0
10.8
12.0
15.0
15.6
18.0
Vcc
ENABLE input (Pin 7) is active low. Output will be disabled ( low) when " E " is high.
.810
(20.57)
MAX.
101
2.5
3.5
4.0
5.0
6.0
6.25
6.5
7.5
9.0
10.0
12.5
13.0
15.0
GENERAL: For Operating Specifications and Test Conditions, see
Tables I and VI on page 5 of this catalog. Delays specified for the
Leading Edge. Buffered input and output.
.010
(0.25)
TYP.
Operating Temp. Range ...................................... 0OC to +70OC
Temperature Coefficient ........................... < 500ppm/OC typical
Minimum Input Pulse Width ............................ 40% max. Delay
Supply Current, ICC ............................. 60 mA typ., 80 mA max
.300
(7.62)
For other values & Custom Designs, contact factory.
24
PLDM 4/98
15801 Chemical Lane, Huntington Beach, CA 92649-1595
Tel: (714) 898-0960 • Fax: (714) 896-0971
FAST / TTL Buffered I/O 4-Bit Programmable Delay Modules
PLDM7 Series TTL Logic 3-Bit Programmable Delay Modules
Electrical Specifications at 25OC
Electrical Specifications at 25OC
FAST / TTL Buffered I/O 4-Bit Programmable Delay Modules
Electrical Specifications at 25OC
PLDM4 Series FAST Logic 3-Bit Programmable Delay Modules
Electrical Specifications at 25OC
CUMULATIVETOLERANCES: "Error" Tolerance is for
Programmed Delays Referenced to Initial Delay, Setting "0000."
For example, the setting "1111" delay of PLDM15-1 is 15.0 ± 1.0
referenced to "0000," and 30.0 ± 2.0 referenced to the input.
FAST / TTL 4-Bit Schematic
Vcc
32
ENABLE input (Pin 7) is active low. Output will be disabled ( low) when " E " is high.
P1
.400
(10.16)
MAX.
16
11
3-Bit Programmable
.120
(3.05)
MIN.
.100
(2.54)
TYP.
Rhombus
Industries Inc.
.050
(1.27)
TYP.
Rhom bus
Industries Inc.
10
P3
.010
(0.25)
TYP.
P2
19
P3
18
P4
17
Output
Buffer
13
15
16
OUT
E
GND
ENABLE input (Pin 15) is active low.
Output will be disabled (remain low)
when " E " is high.
.400
(10.16)
MAX.
9
.295
(7.49)
MAX
7
8
E
GND
.030
(0.76)
TYP.
.050
(1.27)
TYP.
PLDM 4/98
15801 Chemical Lane, Huntington Beach, CA 92649-1595
Tel: (714) 898-0960 • Fax: (714) 896-0971
.020
(0.51)
TYP.
.600
(15.24)
.120
(3.05)
MIN.
.100
(2.54)
TYP.
.010
(0.25)
TYP.
.300
(7.62)
.300
(7.62)
.600
(15.24)
Dimensions
in Inches (mm)
GENERAL: ForOperating Specifications and Test Conditions, see
Tables I and VI on page 5 of this catalog. Delays specified for the
Leading Edge. Buffered input and output.
For other values & Custom Designs, contact factory.
24
24
4-Bit Programmable
Delay Line
7
GND
Buffer
5
OUT
OperatingTemp. Range ............................. 0OC to +70OC
Temperature Coefficient ..................... < 500ppm/ OC typical
Minimum Input Pulse Width ...................... 40% max. Delay
Supply Current, I CC ....................... 60 mA typ., 80 mA max
.300
(7.62)
Vcc
26
3
Output
4
IN
INPUT FAN-IN: Input, pin 4, is loaded by the internal passive
network and 8 gate inputs (74S/74F type). The source driving Pin
4 should be 74S/74F type or equivalent, and should not be used
to drive any load other than the delay line input.
.260 .300
(6.60)(7.62)
TYP. MAX.
.020
(0.51)
TYP.
Specifica tions subject to changewithout notice.
P2
IN
1.650
(41.91)
MAX
FAST / TTL 3-Bit 16-PinSchematic
Vcc
Delay Line
Dimensions in Inches (mm)
.810
(20.57)
MAX.
P1
Input
Buffer
GENERAL: ForOperating Specifications and Test Conditions, see
Tables I and VI on page 5 of this catalog. Delays specified for the
Leading Edge. Buffered input and output.
Electrical Specifications at 25OC
Initial
4-Bit FAST
Delay Error ref.
Referenced to "0000" - Delay (ns) per Program Setting (P4*P3*P2*P1)
Part
per Step to 0000 Delay (ns)
Number
(ns)
(ns)
0000
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
PLDM8-0.5
0.5 ± .25
± 0.8
8±1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
6.0
6.5
7.0
7.5
PLDM8-1
1.0 ± 0.5
± 1.0
8±1
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0
PLDM8-1.5
1.5 ± 0.6
± 1.5
8±1
0.0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 18.0 19.5 21.0 22.5
PLDM8-2
2.0 ± 0.7
± 1.5
8±1
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0
PLDM8-2.5
2.5 ± 0.7
± 1.5
8±1
0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 37.5
PLDM8-3
3.0 ± 0.7
± 2.0
8±1
0.0 3.0 6.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0 33.0 36.0 39.0 42.0 45.0
PLDM8-3.5
3.5 ± 0.7
± 2.5
8±1
0.0 3.5 7.0 10.5 14.0 17.5 21.0 24.5 28.0 31.5 35.0 38.5 42.0 45.5 49.0 52.5
PLDM8-4
4.0 ± 0.8
± 3.0
8±1
0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 36.0 40.0 44.0 48.0 52.0 56.0 60.0
PLDM8-4.5
4.5 ± 0.8
± 3.0
8±1
0.0 4.5 9.0 13.5 18.0 22.5 27.0 31.5 36.0 40.5 45.0 49.5 54.0 58.5 63.0 67.5
PLDM8-5
5.0 ± 1.0
± 3.0
8±1
0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 70.0 75.0
PLDM8-10
10 ± 1.5
± 5.0
8±1
0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100. 110.0 120.0 130.0 140.0 150.0
OperatingTemp. Range .............................. 0OC to +70OC
Temperature Coefficient ..................... < 500ppm/ OC typical
Minimum Input Pulse Width ...................... 40% max. Delay
Supply Current, I CC ...................... 90 mA typ., 105 mA max
CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays
referenced to Initial Delay, Setting "0000." For example the setting "111" delay of
PLDM7-10 is 70.0 ± 3.0ns ref. to "000," and 77.0 ± 4.0ns referenced to the input.
3
7
32
26
.800
(20.32)
Specifica tions subject to cha ngewithout notice.
Rhombus
Industries Inc.
13
16
.300
(7.62)
19 18 17
24
.500
(12.70)
For other values & Custom Designs, contact factory.
25
PLDM 1/98
15801 Chemical Lane, Huntington Beach, CA 92649-1595
Tel: (714) 898-0960 • Fax: (714) 896-0971
Electrical Specifications at 25OC
Initial
4-Bit TTL
Delay Error ref.
Referenced to "0000" - Delay (ns) per Program Setting (P4*P3*P2*P1)
Part
per Step to 0000 Delay (ns)
Number
(ns)
(ns)
0000
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
PLDM15-1
1.0 ± 0.5
± 1.0
15 ± 1
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0
PLDM15-2
2.0 ± 0.7
± 1.5
15 ± 1
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0
PLDM15-5
5.0 ± 1.0
± 3.0
15 ± 1
0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 70.0 75.0
PLDM15-10 10 ± 1.5
± 5.0
15 ± 1
0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100. 110.0 120.0 130.0 140.0 150.0
CUMULATIVE TOLERANCES: "Error" Tolerance is for
Programmed Delays Referenced to Initial Delay, Setting "0000."
For example, the setting "1111" delay of PLDM15-1 is 15.0 ± 1.0
referenced to "0000," and 30.0 ± 2.0 referenced to the input.
FAST / TTL 4-Bit Schematic
Vcc
P1
Vcc
P2
P3
P4
32
26
24
19
18
17
Input
Buffer
GENERAL: For Operating Specifications and Test Conditions, see
Tables I and VI on page 5 of this catalog. Delays specified for the
Leading Edge. Buffered input and output.
Operating Temp. Range ...................................... 0OC to +70OC
Temperature Coefficient ........................... < 500ppm/OC typical
Minimum Input Pulse Width ............................ 40% max. Delay
Supply Current, ICC ............................. 90 mA typ., 105 mA max
4-Bit Programmable
Delay Line
Output
Buffer
3
7
13
15
16
IN
GND
OUT
E
GND
ENABLE input (Pin 15) is active low.
Output will be disabled (remain low)
when " E " is high.
.400
(10.16)
MAX.
1.650
(41.91)
MAX
.295
(7.49)
MAX
.030
(0.76)
TYP.
.050
(1.27)
TYP.
.020
(0.51)
TYP.
.600
(15.24)
.120
(3.05)
MIN.
.100
(2.54)
TYP.
.600
(15.24)
.010
(0.25)
TYP.
.300
(7.62)
.300
(7.62)
Dimensions
in Inches (mm)
3
7
26
32
.800
(20.32)
Specifications subject to change without notice.
Rhombus
Industries Inc.
13
24
16
.300
(7.62)
19 18 17
.500
(12.70)
For other values & Custom Designs, contact factory.
25
PLDM 1/98
15801 Chemical Lane, Huntington Beach, CA 92649-1595
Tel: (714) 898-0960 • Fax: (714) 896-0971