MITSUBISHI <Dig./Ana.INTERFACE> Ytion. nge. R A f N i ica o cha P MoIt a finasl asrpeescubject t I L R E his is n c limit etri ce:T Noti e param m So M62023L,P,FP SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP PIN CONFIGURATION (TOP VIEW) GENERAL DESCRIPTION The M62023L/P/FP is a system reset IC that controls the memory backup function of an SRAM and an embedded RAM of a microcontroller. The IC outputs reset signals (RES/RES) to a microcontroller at power-down and power failure. It also shifts the power supply to RAMs from main to backup, outputs a signal (CS) that invokes standby mode, and alters RAMs to backup circuit mode. 8 CS 7 RES 6 GND 5 RES FEATURES 4 Ct • Built-in switch for selection between main power supply and backup power supply to RAMs • Small difference between input and output voltages (IOUT=80mA, VIN=3V) : 0.15V typ • Detection voltage (power supply monitor voltage) : 2.57V typ • Chip select signal output (CS) • Two channels of reset outputs (RES/RES) • Power on reset circuit APPLICATION Power supply control systems for memory of microcontroller systems in electronic equipment such as OA equipment, industrial equipment, and home-use electronic appliances and SRAM boards with built-in backup function that require switching between external power supply and battery. 3 VIN 2 VBAT 1 VOUT Outline 8P5 (L) VOUT 1 8 CS VBAT 2 7 RES VIN 3 6 GND Ct 4 5 RES Outline 8P4 (P) 8P2S-A (FP) BLOCK DIAGRAM SW VIN 3 1 VOUT R1 D1 Com RESET CIRCUIT R2 2 VBAT 8 CS 1.24V DELAY CIRCUIT RES 7 4 Ct RES 5 6 GND ( 1 / 4) 1997.5.30- rev MITSUBISHI <Dig./Ana.INTERFACE> Ytion. nge. R A f N i ica o cha P MoIt a finasl asrpeescubject t I L R E his is n c limit etri ce:T Noti e param m So M62023L,P,FP SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted) Symbol VIN IOUT Pd K Topr Tstg Parameter Input voltage Output current Power dissipation Thermal derating Operating temperature Storage temperature Conditions Ta ≥ 25°C Ratings 7 100 800(L)/625(P)/440(FP) 8(L)/6.25(P)/4.4(FP) -20 to +75 -40 to +125 Unit V mA mW mW/°C °C °C ELECTRICAL CHARACTERISTICS (Ta=25°C, unless otherwise noted) Symbol Parameter VS ∆VS Detection voltage Hysteresis voltage ICC Circuit current VDROP VOH(Ct) VOL(Ct) Difference between input and output voltages Ct output voltage (high level) Ct output voltage (low level) VOH(RES) RES output voltage (high level) VOL(RES) RES output voltage (low level) VOH(RES) RES output voltage (high level) VOL(RES) RES output voltage (low level) VOH(CS) CS output voltage (high level) VOL(CS) CS output voltage (low level) IR VF tpd td Backup Di leak current Backup Di forward direction voltage Delay time Response time VOPL(RES) RES limit voltage of operation Test Conditions VIN (At charge from H L) ∆VS=VSH-VSL VIN=2V IOUT=0mA VIN=3V IOUT=50mA VIN=3V IOUT=80mA VIN=3V (Note 1) VIN=2V (Note 1) VIN=2V (Note 1) (Note 1) VIN=3V Isink=1mA VIN=3V (Note 1) (Note 1) VIN=2V Isink=1mA VIN=2V (Note 2) VIN=0V, VBAT=3V (Note 2) (Note 1) VIN=3V Isink=1mA VIN=3V VBAT=3V VIN=0V IF=10µA VIN=0V 3V, Ct=4.7µF VIN=3V 2V (Note 3) Limits Min Typ Max 2.44 50 2.57 100 1.5 6.5 0.1 0.15 2.4 0.02 2.0 0.02 0.04 3.0 0.02 0.04 1.6 2.47 0.07 0.08 2.70 200 3.0 10 0.2 0.3 2.0 1.5 2.5 1.3 2.40 10 0.54 27 5.0 0.65 0.1 0.2 Unit V mV mA V V V V V V 0.2 V V 0.3 ±0.5 ±0.5 0.6 55 25.0 V µA V ms µs V Note 1. Regarding conditions to measure VOH and VOL, voltage values are generated by internal resistance only and no external resistor is used. 2. These values are produced inserting an external resistor, RCS=1MΩ, between the CS pin and GND. 3. With no external resistor (10KΩ internal resistance only) ( 2 / 4) 1997.5.30- rev MITSUBISHI <Dig./Ana.INTERFACE> Ytion. nge. R A f N i ica o cha P MoIt a finasl asrpeescubject t I L R E his is n c limit etri ce:T Noti e param m So M62023L,P,FP SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP EXPLANATION OF TERMINALS Pin No. Symbol 1 VOUT 2 VBAT 3 VIN 4 Ct 5 RES 6 GND 7 RES 8 CS Name Function VIN and VBAT are controlled by means of an internal switch and output through VOUT. Power supply output The pin is capable of outputting up to 100 mA. Use it as VDD of CMOS RAM and the like. Backup power supply Backup power supply is connected to this pin. input If a lithium battery is used, insert a resistor in series for safety purposes. Power supply input +3V input pin. Connect to a logic power supply. Delay capacitor A delay capacitor is connected to this pin. By connecting a capacitor, it is connection pin possible to delay each output. Connect to the positive reset input of a microcontroller. The pin is capable of Positive reset output flowing 1mA sink current. Ground Reference for all signals Connect to the negative reset input of a microcontroller. The pin is capable of Negative reset output flowing 1mA sink current. Connect to the chip select of RAM. The CS output is at low level in normal state thereby letting RAM be active. Under failure or backup condition, the CS Chip select output output is set to high level, then RAM enters standby state disabling read/write function. The pin is capable of flowing a 1mA sink current. APPLICATION EXAMPLE M62023 +3V (MAIN POWER SUPPLY) VIN VOUT SW 3 1 R1 CIN D1 Com RESET CIRCUIT VDD VBAT BATTERY 2 R2 MCU or CPU 7 5 RES COUT VDD CS 8 1.24V RES 3V DELAY CIRCUIT 4 CMOS RAM Ct Ct GND 6 Capacitance to be connected: CIN: 10µF; COUT: 4.7µF; Ct: 4.7µF ( 3 / 4) 1997.5.30- rev MITSUBISHI <Dig./Ana.INTERFACE> Ytion. nge. R A f N i ica o cha P MoIt a finasl asrpeescubject t I L R E his is n c limit etri ce:T Noti e param m So M62023L,P,FP SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP TIMING CHART tpd tpd 3V VSH VSL VIN ∆VS 0V V1 VOUT V2 CS V3 V2 V3 VOL(CS) 3V VIN(VSL) RES VOL(RES) VOH(RES) VIN(VSL) RES VOL(RES) Input voltage In normal operation In failure (instantaneous drop) RES RES CS In backup state Input voltage : 3V Input voltage : 3V 2V Each output varies if the input voltage drops to VSL or under Input voltage : 2V 3V Input voltage : 0V If the input voltage goes higher Backup voltage : 3V than VSL by 100mV, each output varies after delay produced by the delay circuit With SW Tr. set to ON, a voltage (VIN-VDROP) is output SW Tr. is turned OFF. A voltage (VIN-VEB) is output by the diode between E and B of SW Tr. SW Tr. is turned ON after delay VBAT-VF and a voltage (VIN-VDROP) is output The output level is VOL(RES) with a logic low As the state shifts from a logic low to logic high, the output level becomes approximately equal to the input voltage A logic high is maintained, and then shifts to a logic low The output level is VOH(RES) with a logic high As the state shifts from a logic high to logic low, the output level becomes VOL(RES) A logic low is maintained, and then shifts to a logic high The output level is VOL(CS) with a logic low As the state shifts from a logic low to logic high, the output level becomes the voltage VIN-VEB A logic high is maintained, and then shifts to a logic low Output pin VOUT Restoration from failure (instantaneous drop) V1=VIN-VDROP V2=VIN-VEB(SW Tr.) V3=VBAT-VF ( 4 / 4) The output is a logic high and the output level is VBAT-VF 1997.5.30- rev