IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPT857D DESCRIPTION: FEATURES: The CSPT857D is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. A CMOS Enable/Disable pin is available for low power disable. When the input frequency falls below approximately 20MHz, the device will enter power down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are tristated, resulting in a current consumption of less than 200µA. The CSPT857D requires no external components and has been optimised for very low I/O phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPT857D, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPT857D is available in Commercial Temperature Range (0°C to +70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering Information for details. • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications requiring improved output crosspoint voltage • Operating frequency: 60MHz to 220MHz • Very low skew: – <100ps for PC1600 - PC2700 – <75ps for PC3200 • Very low jitter: – <75ps for PC1600 - PC2700 – <50ps for PC3200 • 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700 • 2.6V AVDD and 2.6V VDDQ for PC3200 • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56pin VFBGA packages APPLICATIONS: • Meets or exceeds JEDEC standard JESD 82-1A for registered DDR clock driver • Meets proposed DDR1-400 specification • For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333), PC3200 (DDR400) • Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859, SSTVF16859, SSTVN16859, DDR1 register, provides complete solution for DDR1 DIMMs The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES OCTOBER 2003 1 c 2003 Integrated Device Technology, Inc. DSC-6835/3 IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FUNCTIONAL BLOCK DIAGRAM PWRDWN AVDD TEST MODE LOGIC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 CLK CLK Y5 PLL FBIN Y6 FBIN Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT 2 IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS 6 Y5 Y6 GND Y7 PWR DWN 5 Y5 Y6 GND Y7 VDDQ FBIN FBOUT GND FBIN VDDQ FBOUT Y8 Y9 Y8 Y9 4 GND VDDQ NC NC NC NC VDDQ GND 3 GND VDDQ NC NC NC NC VDDQ GND 2 Y0 Y1 GND Y2 VDDQ CLK AVDD GND Y3 Y4 1 Y0 Y1 GND Y2 VDDQ CLK VDDQ AGND Y3 Y4 A B C D E F J K H G VFBGA TOP VIEW 56 BALL VFBGA PACKAGE LAYOUT 0.65mm 6 5 TOP VIEW 4 3 2 1 A B C D E F G H J K A B C D E F G H J K 1 2 3 4 5 6 3 IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 40 39 38 37 36 35 34 33 32 Y6 Y6 VDDQ Y5 Y5 Y0 Y0 VDDQ Y1 Y1 PIN CONFIGURATIONS 31 GND 1 48 GND Y0 2 47 Y5 Y0 3 46 Y5 GND 1 30 Y7 VDDQ 4 45 VDDQ Y2 2 29 Y7 Y1 5 44 Y6 Y2 3 28 VDDQ Y1 6 43 Y6 VDDQ 4 27 PWRDWN GND 7 42 GND CLK 5 26 FBIN GND 8 41 GND CLK 6 25 FBIN Y2 9 7 24 VDDQ 40 Y7 VDDQ Y2 10 AVDD 8 23 VDDQ 39 Y7 AGND 9 22 FBOUT VDDQ 11 38 VDDQ 10 21 FBOUT VDDQ 12 37 PWRDWN CLK 13 36 FBIN CLK 14 35 FBIN VDDQ 15 34 VDDQ AVDD 16 33 FBOUT AGND 17 32 FBOUT GND 18 31 GND Y3 19 30 Y8 Y3 20 29 Y8 VDDQ 21 28 VDDQ Y4 22 27 Y9 Y4 23 26 Y9 GND 24 25 GND 19 20 Y8 18 Y8 17 VDDQ 16 Y9 15 Y9 14 Y4 13 Y4 12 VDDQ Y3 11 Y3 GND GND VFQFPN TOP VIEW ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Max Unit VDDQ, AVDD VI(2) Supply Voltage Range Input Voltage Range –0.5 to +3.6 –0.5 to VDDQ + 0.5 V V VO(2) Voltage range applied to any output in the high or low state –0.5 to VDDQ + 0.5 V IIK (VI <0) Input Clamp Current –50 mA IOK (VO <0 or Output Clamp Current ±50 mA Continuous Output Current ±50 mA ±100 mA – 65 to +150 °C VO > VDDQ) IO (VO =0 to VDDQ) VDDQ or GND Continuous Current TSTG Storage Temperature Range TSSOP/ TVSOP TOP VIEW CAPACITANCE(1) Parameter Description Min. Typ. Max. Unit CIN Input Capacitance 2.5 — 3.5 pF -0.25 — 0.25 pF — 14 — pF VI = VDDQ or GND NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. CI(∆) Delta Input Capacitance VI = VDDQ or GND CL Load Capacitance NOTE: 1. Unused inputs must be held high or low to prevent them from floating. 4 IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RECOMMENDED OPERATING CONDITIONS Symbol Parameter AVDD Supply Voltage VDDQ I/O Supply Voltage TA Min. Typ. Max. Unit VDDQ – 0.12 VDDQ 2.7 V V PC1600-PC2700 2.3 2.5 2.7 PC3200 2.5 2.6 2.7 -40 +85 Operating Free-Air Temperature PIN DESCRIPTION (TSSOP/TVSOP) Pin Name Pin Number Description AGND 17 Ground for analog supply AVDD 16 Analog supply CLK, CLK 13, 14 Differential clock input FBIN, FBIN 35, 36 Feedback differential clock input FBOUT, FBOUT 32, 33 Feedback differential clock output GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 PWRDWN 37 Ground Output enable for Y and Y VDDQ 4, 11, 12, 15, 21, 28, 34, 38, 45 Y[0:9] 3, 5, 10, 20, 22, 27, 29, 39, 44, 46 Buffered output of input clock, CLK I/O supply Y[0:9] 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 Buffered output of input clock, CLK PIN DESCRIPTION (VFBGA) Pin Name Pin Number Description AGND H1 Ground for analog supply AVDD G2 Analog supply CLK, CLK F1, F2 Differential clock input FBIN, FBIN F5, F6 Feedback differential clock input FBOUT, FBOUT H6, G5 Feedback differential clock output GND A3, A4, C1, C2, C5, C6, H2, H5, K3, K4 PWRDWN E6 Ground VDDQ B3, B4, E1, E2, E5, G1, G6, J3, J4 Y[0:9] A1, A6, B2, B5, D1, D6, J2, J5, K1, K6 Buffered output of input clock, CLK Y[0:9] A2, A5, B1, B6, D2, D5, J1, J6, K2, K5 Buffered output of input clock, CLK Output enable for Y and Y I/O supply PIN DESCRIPTION (VFQFPN) Pin Name Pin Number Description AGND 9 Ground for analog supply AV DD 8 Analog supply CLK, CLK 5, 6 Differential clock input FBIN, FBIN 25, 26 Feedback differential clock input FBOUT, FBOUT 21, 22 Feedback differential clock output GND 1, 10 PWRDWN 27 Ground VDDQ 4, 7, 13, 18, 23, 24, 28, 33, 38 Y[0:9] 3, 12, 14, 17, 19, 29, 32, 34, 37, 39 Buffered output of input clock, CLK Y[0:9] 2, 11, 15, 16, 20, 30, 31, 35, 36, 40 Buffered output of input clock, CLK Output enable for Y and Y I/O supply 5 °C IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FUNCTION TABLE(1) INPUTS AVDD PWRDWN GND GND X X OUTPUTS CLK CLK Y Y FBOUT FBOUT PLL H L H H H L L H H L H Bypassed/OFF L H L Bypassed/OFF L L H Z Z Z Z OFF L H L Z Z Z Z OFF Nominal(2) H L H L H L H ON Nominal(2) H H L H L H L ON Nominal(2,3) X <20MHz <20MHz Z Z Z Z OFF NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level Z = High-Impedance OFF-State X = Don't Care 2. AVDD nominal is 2.5V for PC1600, PC2100, and PC2700. AVDD nominal is 2.6V for PC3200. 3. Additional feature that senses when the clock input is less than approximately 20MHz and places the part in sleep mode. Reciever inputs and PLL are turned off and outputs = tristate. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC1600 PC2700 Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C; Industrial: TA = -40°C to +85°C Symbol Parameter Conditions Min. Typ. Max. Unit Input Clamp Voltage (All Inputs) VDDQ = 2.3V, II = -18mA – 1.2 V VIL (dc) Static Input LOW Voltage PWRDWN – 0.3 0.7 V VIH (dc) Static Input HIGH Voltage PWRDWN 1.7 VDDQ + 0.3 VIL (ac) Dynamic Input LOW Voltage CLK, CLK, FBIN, FBIN VIH (ac) Dynamic Input HIGH Voltage CLK, CLK, FBIN, FBIN 1.7 VDDQ Output LOW Voltage AVDD/VDDQ = Min., IOL = 100µA 0.1 AVDD/VDDQ = Min., IOL = 12mA 0.6 VIK VOL VOH Output HIGH Voltage VIX Input Differential Cross Voltage AVDD/VDDQ = Min., IOH = -100µA AVDD/VDDQ = Min., IOH = -12mA VID(DC) (1) DC Input Differential Voltage VID(AC) (1) AC Input Differential Voltage IIN 0.7 VDDQ – 0.1 V V V 1.7 VDDQ/2 – 0.2 VDDQ/2 + 0.2 V 0.36 VDDQ + 0.6 V 0.7 VDDQ + 0.6 V ±10 µA Input Current VDDQ = 2.7V, VI = 0V to 2.7V IDDPD Power-Down Current on VDDQ and AVDD AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L 100 200 µA IDDQ Dynamic Power Supply Current on VDDQ AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF 320 360 mA AVDD/VDDQ = Max., CLK = 170MHz, 120Ω/14pF 250 300 IADD Dynamic Power Supply Current on AVDD AVDD/VDDQ = Max., CLK = 170MHz NOTE: 1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK. 6 12 mA IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC3200 Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C; Industrial: TA = -40°C to +85°C Symbol Parameter Conditions Min. Typ. Max. Unit Input Clamp Voltage (All Inputs) VDDQ = 2.5V, II = -18mA – 1.2 V VIL (dc) Static Input LOW Voltage PWRDWN – 0.3 0.7 V VIH (dc) Static Input HIGH Voltage PWRDWN 1.7 VDDQ + 0.3 VIL (ac) Dynamic Input LOW Voltage CLK, CLK, FBIN, FBIN 0.7 VIH (ac) Dynamic Input HIGH Voltage CLK, CLK, FBIN, FBIN 1.7 VDDQ Output LOW Voltage AVDD/VDDQ = Min., IOL = 100µA 0.1 AVDD/VDDQ = Min., IOL = 12mA 0.6 VIK VOL VOH VIX Output HIGH Voltage AVDD/VDDQ = Min., IOH = -100µA VDDQ – 0.1 AVDD/VDDQ = Min., IOH = -12mA 1.7 Input Differential Cross Voltage VID(DC) (1) DC Input Differential Voltage VID(AC) (1) AC Input Differential Voltage V V V VDDQ/2 – 0.2 VDDQ/2 + 0.2 V 0.36 VDDQ + 0.6 V 0.7 VDDQ + 0.6 V Input Current VDDQ = 2.7V, VI = 0V to 2.7V ±10 µA IDDPD Power-Down Current on VDDQ and AVDD AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L 100 200 µA IDDQ Dynamic Power Supply Current on VDDQ AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF 320 360 mA AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF 250 300 IADD Dynamic Power Supply Current on AVDD AVDD/VDDQ = Max., CLK = 200MHz IIN 12 mA NOTE: 1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK. TIMING REQUIREMENTS FOR PC1600 - PC2700 Symbol fCLK Parameter Min. Max. Unit Operating Clock Frequency(1,2) 60 200 MHz Application Clock Frequency(1,3) 60 200 MHz tDC Input Clock Duty Cycle 40 60 % tL Stabilization Time(4) 100 µs NOTES: 1. The PLL will track a spread spectrum clock input. 2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. 3. Application clock frequency is the range over which timing specifications apply. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. TIMING REQUIREMENTS FOR PC3200 Symbol fCLK Parameter Min. Max. Unit Operating Clock Frequency(1,2) 60 220 MHz Application Clock Frequency(1,3) 60 220 MHz tDC Input Clock Duty Cycle 40 60 % tL Stabilization Time(4) 100 µs NOTES: 1. The PLL will track a spread spectrum clock input. 2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. 3. Application clock frequency is the range over which timing specifications apply. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. 7 IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS FOR PC1600 - PC2700 Symbol Description Test Conditions tPLH(1) Min. LOW to HIGH Level Propagation Delay Time Test mode, CLK to any output tPHL(1) HIGH to LOW Level Propagation Delay Time Test mode, CLK to any output tJIT(PER) Jitter (period), see figure 6 66MHz tJIT(CC) Jitter (cycle-to-cycle), see figure 3 tJIT(HPER) Half-Period Jitter, see figure 7 tSLR(O) Output Clock Slew Rate (Single-Ended) tSLR(I) Input Clock Slew Rate t (∅) Static Phase Offset, see figure 4(2,3) tSK(O) Output Skew, see figure 5 tR, tF VOX(5) Typ.(1) Max. 4.5 ns 4.5 – 90 ns 90 100/ 133/ 167/ 200 MHz – 75 75 66MHz – 180 180 100/ 133/ 167/ 200 MHz – 75 75 66MHz – 160 160 100/ 133/ 167/ 200 MHz – 100 100 100/ 133/ 167/ 200 MHz (20% to 80%) Unit ps ps ps 1 2.5 V/ns 1 4 V/ns 66/ 100/ 133/ 167/ 200 MHz – 50 50 ps 75 ps Output Rise and Fall Times (20% to 80%) Load: 120Ω / 14pF 650 900 ps Output Differential Voltage Differential outputs are terminated VDDQ/2 VDDQ/2 V with 120Ω – 0.15 + 0.15 The PLL on the CSPT857D will meet all the above test parameters while supporting SSC synthesizers(4) with the following parameters: SSC Modulation Frequency 30 50 KHz SSC Clock Input Frequency Deviation 0 -0.5 % f3dB PLL Loop Bandwidth 5 MHz NOTES: 1. Refers to transition of non-inverting output. 2. Static phase offset does not include jitter. 3. t(φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V. 4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 5. VOX is specified at the SDRAM clock input or test load. 8 IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS FOR PC3200 Symbol Test Conditions LOW to HIGH Level Propagation Delay Time Test mode, CLK to any output 4.5 ns tPHL(1) HIGH to LOW Level Propagation Delay Time Test mode, CLK to any output 4.5 ns tJIT(PER) Jitter (period), see figure 6 66MHz tJIT(CC) Jitter (cycle-to-cycle), see figure 3 tJIT(HPER) Half-Period Jitter, see figure 7 tSLR(O) Output Clock Slew Rate (Single-Ended) tSLR(I) Input Clock Slew Rate Min. Typ.(1) Description tPLH(1) – 90 Max. 90 200 MHz – 50 50 66MHz – 180 180 ps ps 200 MHz – 75 75 66MHz – 160 160 200 MHz – 75 75 1 2.5 V/ns 1 4 V/ns – 50 50 ps 75 ps 650 900 ps V 200 MHz (20% to 80%) t (∅) Static Phase Offset, see figure 4(2,3) tSK(O) Output Skew, see figure 5 tR, tF Output Rise and Fall Times (20% to 80%) Load: 120Ω / 14pF Output Differential Voltage Differential outputs are terminated VDDQ/2 VDDQ/2 with 120Ω – 0.15 + 0.15 VOX(5) Unit 200 MHz ps The PLL on the CSPT857D will meet all the above test parameters while supporting SSC synthesizers(4) with the following parameters: SSC Modulation Frequency 30 50 KHz SSC Clock Input Frequency Deviation 0 -0.5 % f3dB PLL Loop Bandwidth 5 MHz NOTES: 1. Refers to transition of non-inverting output. 2. Static phase offset does not include jitter. 3. t(φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V. 4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 5. VOX is specified at the SDRAM clock input or test load. 9 IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TEST CIRCUIT AND SWITCHING WAVEFORMS VDD Z = 60Ω C = 14pF R = 120Ω Z = 60Ω VSS C = 14pF VSS CSPT857D VSS Figure 1. Output Load VDDQ/2 R = 10Ω Z = 60Ω Z = 50Ω C = 14pF R = 50Ω VDDQ/2 0V R = 10Ω Z = 60Ω Z = 50Ω C = 14pF R = 50Ω 0V VDDQ/2 CSPT857D SCOPE VDDQ/2 Figure 2. Output Load Test Circuit 10 IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT tcycle n tcycle n+1 tjit(cc) = tcycle n tcycle n+1 Figure 3. Cycle-to-Cycle jitter CLK CLK FBIN FBIN t(Ø)n + 1 t(Ø)n ∑ t(Ø) n=N 1 = t(Ø)n N Figure 4. Static Phase Offset Yx Yx Yx, FBOUT Yx, FBOUT tsk(o) Figure 5. Output Skew 11 (N is a large number of samples) IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT tcycle n Yx, FBOUT Yx, FBOUT 1 fo tjit(per) = tcycle n 1 fo Figure 6. Period jitter Yx, FBOUT Yx, FBOUT thalf period n+1 thalf period n Yx, FBOUT Yx, FBOUT 1 fo tjit(hper) = thalf period n Figure 7. Half-Period jitter 12 1 2*f o IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TEST CIRCUIT AND SWITCHING WAVEFORMS 80% 80% Clock Inputs and Outputs VID, VOD 20% 20% tF tR Figure 8. Input and Output Slew Rates APPLICATION INFORMATION Clock Loading on the PLL outputs (pF) Clock Structure # of SDRAM Loads per Clock Min. #1 2 4 7 #2 4 8 14 13 Max. IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES APPLICATION INFORMATION ~0.6" (split to terminator) ~2.5" SDRAM CSPT857D Z = 60Ω CLK C = 14pF R = 120Ω R = 120Ω Z = 60Ω CLK FBIN (1) C = 14pF 8 more SDRAM ~0.3" R = 120Ω FBIN Feedback path Figure 9. Clock Structure 1 ~0.6" (split to terminator) ~2.5" SDRAM Stacked SDRAM CSPT857D Z = 60Ω CLK C = 14pF R = 120Ω R = 120Ω Z = 60Ω CLK FBIN (1) C = 14pF SDRAM 8 more ~0.3" R = 120Ω SDRAM FBIN Feedback path Figure 10. Clock Structure 2 NOTE: 1. Memory module vendors may need to adjust the feedback capacitive load in order to meet DDR SDRAM registered DIMM timing requirements. 14 Stacked IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDTCSPT XXXXX Device Type X XX Package Process Blank I 0°C to +70°C (Commercial) -40°C to +85°C (Industrial) Thin Shrink Small Outline Package TSSOP - Green Thin Very Small Outline Package Very Fine Pitch Ball Grid Array Thermally-Enhanced Plastic Very Fine Pitch Flat No Lead Package VFQFPN MLF - Green PA PAG PF BV NL 2.5V - 2.6V PLL Differential 1:10 SDRAM Clock Driver 857D CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 15 for Tech Support: [email protected] (408) 654-6459