PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Features Description • PLL clock distribution optimized for DDR2 SDRAM applications. PI6CU877 PLL clock driver is developed for Registered DDR2 DIMM applications with 1.8V operation and differential data input and output levels. • Distributes one differential clock input pair to ten differential clock output pairs. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to eleven differential pairs of clock outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT, FBOUT). • Differential Inputs (CLK, CLK) and (FBIN, FBIN) • Input OE/OS: LVCMOS • Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT) The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the LVCMOS (OE, OS) and the Analog Power input (AVDD). When OE is LOW the outputs except FBOUT, FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS is a program pin that must be tied to GND or VDD. When OS is high, OE will function as described above. When OS is LOW, OE has no effect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 1.8V for core circuit and internal PLL, and VDDQ = 1.8V for differential output drivers • Packaging (Pb-free & Green available): – 52-ball VFBGA (NF) When CLK/CLK are logic low, the device will enter a low power mode. An input logic detection circuit will detect the logic low level and perform a low power state where all Y[0:9], Y[0:9]; FBOUT, FBOUT, and PLL are OFF. Pin Configuration 1 2 3 4 5 6 A Y1 Y0 Y0 Y5 Y5 Y6 B Y1 GND GND GND GND Y6 C Y2 GND NB NB GND Y7 D Y2 VDDQ VDDQ VDDQ OS Y7 E CK VDDQ NB NB VDDQ FBIN F CK VDDQ NB NB OE FBIN G AGND VDDQ VDDQ VDDQ VDDQ FBOUT H AVDD GND NB NB GND FBOUT J Y3 GND GND GND GND Y8 k Y3 Y4 Y4 Y9 Y9 Y8 PI6CU877 is a high performance, low skew, and low jitter PLL clock driver, and it is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. 1 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Block Diagram Y0 OE OS AVDD LD* or OE Powerdown LD*, OS or OE Control & Test Logic PLL bypass LD* Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 CK CK 10K - 100kΩ Y6 Y7 PLL Y7 Y8 FBIN FBIN Y8 Y9 * The Logic Detect (LD) powers down the device when a logic low is applied to both CK and CK. 2 Y9 FBOUT FBOUT PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Pinout Table Pin Name Characteristics Desctription AGND Ground Analog ground AVDD 1.8V nominal Analog power CK Differential Input Clock input with a (10K - 100KΩ) pulldown resistor CK Differential Input Complementary clock input with a (10K - 100KΩ) pulldown resistor FBIN Differential Input Complementary feedback clock input FBIN Differential Input Feedback clock input FBOUT Differenital Output Complementary Feedback clock output FBOUT Differential Output Feedback clock output OE LVCMOS input Output enable (async.) OS LVCMOS input Output select (tied to GND or VDDQ) GND Ground Ground VDDQ 1.8V nominal Logic and output power Y[0:9] Differential Outputs Clock outputs Y[0:9] Differential Outputs Complementary clock outputs NB No Ball (VFBGA only) Function Table Inputs Outputs PLL State AVDD OE OS CK CK Y Y FBOUT FBOUT GND H X L H L H L H Bypass/Off GND H X H L H L H L Bypass/Off H L(Z)(1) L(Z)(1) L H Bypass/Off L(Z)(1), Y7 active H L Bypass/Off L H On H L On GND L H L GND L L H L L(Z)(1), Y7 active 1.8V (nom) L H L H L(Z)(1) L(Z)(1) L(Z)(1), L(Z)(1), 1.8V (nom) L L H L 1.8V (nom) H X L 1.8V (nom) H X H Y7 active Y7 active H L H L H On L H L H L On L(Z)(1) L(Z)(1) L(Z)(1) L(Z)(1) Off 1.8V (nom) X X L L 1.8V (nom) X X H H Reserved Notes: 1. L(Z) means the outputs are disabled to a low state meeting the IODL limit on DC Specification 3 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Absolute Maximum Ratings (Over operating free-air temperature range) Symbol Min. Max. I/O supply voltage range and analog /core supply voltage range -0.5 2.5 VI Input voltage range -0.5 VDDQ +0.5 VO Output voltage range -0.5 IIK Input clamp current -50 50 IOK Output clamp current -50 50 IO Continuous output current -50 50 Continuous current through each VDDQ or GND -100 100 Storage temperature -65 150 ºC Units VDDQ, AVDD IO(PWR) TSTG Parameter Units V mA Note: 1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. DC Specifications Recommended Operating Conditions Symbol Parameter VDDQ Output supply Voltage AVDD Supply Min. Typ. Max. 1.7 1.8 1.9 voltage(4) VDDQ 0.35 x VDDQ VIL Low-level input voltage(5) OE, OS, CK, CK VIH High-level input voltage(5) OE, OS, CK, CK IOH High-level output current, see Fig 2 - -9 IOL Low-level output current, see Fig. 2 - 9 (VDDQ/2) -0.15 (VDDQ/2) -0.15 -0.3 VDDQ +0.3 DC 0.3 VDDQ +0.4 AC 0.6 VDDQ +0.4 0 70 VIX Input differential-pair crossing voltage VIN Input voltage level VID Input differenital voltage, See Fig 9 (5) TA Operating free air temperature V 0.65 x VDDQ mA V ºC Notes: 4. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are guaranteed. 5. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK, VIH and VIL limits are used to define the DC low and high levels for the logic detect state. 4 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Timing Requirements (Over recommended operating free-air temperature) Symbol FCK tDC AVDD, VDDQ = 1.8V ±0.1V Decription Operation clock frequency(7, 8) Application clock frequency(7, 9) Input clock duty cycle Max. 25 300 160 270 40 60 % 15 µs 8 ns time(10) tL Stabalization tOFF Device power Units Min. down(10) MHz Notes: 7. The PLL is able to handle spread spectrum induced skew. 8. Operating clock frequency indicates a range over which the PLL is able to lock, but in which it is not required to meet the other timing parameters. (Used for low-speed debug). 9. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 10. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up . During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK maybe left floating after they have been driven low for one complete clock cycle. DC Specifications Parameter Description Test Condition AVDD, VDDQ Min. VIK All Inputs II= -18mA 1.7V VOH HIGH output voltage IOH = -100µA 1.7 to 1.9V VDDQ -0.2 1.7 1.1 IOH = -9mA IODL Output disabled low current OE = L, VODL = 100mV VOD Output differenital voltage, the magniture of the difference between the true and complimentary outputs, see fig. 9 for dimentions 1.7V Typ. Max. 1.2 V 100 µA 0.6 V CK, CK VI = VDDQ or GND ±250 OE, OS, FBIN, FBIN VI = VDDQ or GND ±10 IDDLD Static Supple current, IDDQ + IADD CK and CK = L IDD Dynamic supply current, IDDQ + IADD, see note 6 for CPD calculation CK and CK = 270MHz, all outputs are open (not connected to a PCB) CK, CK VI = VDDQ or GND FBIN, FBIN VI = VDDQ or GND CK, CK VI = VDDQ or GND FBIN, FBIN VI = VDDQ or GND II CI CI(∆) µA 500 1.9V 300 1.8V Units 2 3 2 3 0.25 mA pF 0.25 Notes: 6. Total IDD = IDDQ + IADD = FCK *CPD *VDDQ, solving for CPD = (IDDQ + IADD)/(FCK*VDDQ) where FCK is the input frequency, VDDQ is the power supply and CPD is the Power Dissipation Capacitance. 5 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory AC Specifications Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)(15) Parameter Description Diagram AVDD, VDDQ = 1.8V ±0.1V Min. Nom. Max. ten OE to and Y/Y see Fig 11 8 tdis OE to and Y/Y see Fig 11 8 Cycle-to-cycle jitter see Fig 4 tjit(cc+) tjit(cc-) t(Ø) 40 0 -40 see Fig 5 -50 50 Dynamic phase offset see Fig 10 -50 50 Output clock skew see Fig 6 Static phase offset t(Ø)dyn tsk(o) tjit(per) tjit(hper) slr(i) 0 Period (11) jitter(12) see Fig 7 -40 40 see Fig 8 -75 75 Input clock slew rate see Fig 9 1 see Fig 9 0.5 see Fig 1, 9 1.5 Output enable (OE) (14, 16) slr(o) Output clock slew rate VOX Outpu differenital-pair cross voltage(13) see Fig 2 ns ps 40 (12) Halk period jitter Units (VDDQ/2) -0.1 2.5 4 V/ns 2.5 3 (VDDQ/2) +0.1 V The PLL on the PI6CU877 is capable of meeting all the above test parameters while supporting SSC synthesirers with the following parameters: SSC modulation frequency 30.00 33 kHz SSC clock input frequency deviation 0.00 -0.50 % PI6CU877 PLL design should target the values below to minimize the SCC induced skew: PLL Loop Bandwidth 2.0 MHz Notes: 11. Static Phase Offset does not include Jitter 12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. 13. VOX specified at the DRAM clock input or the test load. 14. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2 DIMM application. 15. There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables should be used. 16. The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended. 6 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory VDD VCK PI6CU877 R = 60Ω R = 60Ω VDD/2 VCK GND Figure 1. IBIS Model Output Load ��� �������� ����� ��� �����Ω �������� ������Ω ������ �������Ω ��� �����Ω �������� �������� ��� �������� ������Ω ������ ����������������� ��� ��� Figure 2. Output Load Test Circuit 1 VDD/2 SCOPE C = 10pF –VDD/2 Z= 60Ω R = 10Ω Z= 50Ω R = 10Ω Z= 50Ω L= 2.97" Z= 60Ω R = 50Ω VTT L= 2.97" R = 50Ω C = 10pF PI6CU877 –VDD/2 VTT Note: VTT = GND –VDD/2 Figure 3. Output Load Test Circuit 2 7 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory �������� �������� � ������� � ��������� � ���������� � ���������� � ��������� Figure 4. Cycle-to-Cycle Jitter �� �� ���� �� ���� � ����� �� � ������ ��� ∑� � ��� � � ������� � �������������������������������� Figure 5. Static Phase Offset �� �� ��������� ��������� t sk(o) Figure 6. Output Skew 8 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory ��������� ��������� � ������� ��������� ��������� � �� � ����������� � ������� � �� Figure 7. Period Jitter (fo = average input frequency measured at CK/CK) ��������� ��������� � ��� ������������ � ������������� � �� � ������������ �� ������������� � ��� � Figure 8. Half-Period Jitter ��� ��� � ������ ������������ �������������� ��� ��� � ������� ���� ������������������������� ������� ������������������������� ������� � � ������ ���� Figure 9. Input and Output Slew Rates 9 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory ��� ��� ���� ����� ���� ������� ���� ������� ������ ������� ������ ������� ������� ������� Figure 10. Dynamic Phase Offset 50% VDD OE ten Y 50% VDD Y Y/Y OE 50% VDD tdis Y 50% VDD Y Figure 11. Time Delay Between Output Enable (OE) and Clock Output (Y, Y) 10 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Packaging Mechanical: 52-Pin VFBGA (NF) Ordering Information Ordering Code Package Code Package Description PI6CU877NF NF 52-ball VFBGA PI6CU877NFE NF Pb-free & Green, 52-ball VFBGA Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/ Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com 11 PS8689B 08/05/04