ETC PI6CV857A

PI6CV857
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PLL Clock Driver for
2.5V DDR-SDRAM Memory
Product Features
Product Description
• PLL clock distribution optimized for Double Data Rate
SDRAM applications.
• Distributes one differential clock input pair to ten differential
clock output pairs.
• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
• Input PWRDWN: LVCMOS
• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
• External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
• Operates at AVDD = 2.5V for core circuit and internal PLL,
and VDDQ = 2.5V for differential output drivers
• Package:
Plastic 48-pin TSSOP
PI6CV857 PLL clock device is developed for registered DDR DIMM
applications This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V
AVDD operation and differential data input and output levels.
Package options include plastic Thin Shrink Small-Outline Package
(TSSOP).The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock
outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock
outputs (FBOUT,FBOUT) . The clock outputs are controlled by the
input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN) and the Analog Power input (AVDD).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off and the differential clock
outputs are 3-stated. When the AVDD is strapped low, the PLL is
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection frequency that is below the operating frequency of the PLL, the device
will enter a low power mode. An input frequency detection circuit will
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CV857 clock driver uses input clocks (CLK, CLK)
and feedback clocks (FBIN,FBIN) to provide high-performance, lowskew, low-jitter output differential clocks (Y[0:9], Y[0:9]). PI6CV857
is also able to track Spread Spectrum Clocking for reduced EMI.
Block Diagram/Pin Configuration
CLK
CLK
FBIN
FBIN
PWRDWN
AVDD
PLL
Powerdown
and Test
Logic
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
GND
Y0
Y0
VD D Q
Y1
Y1
GND
GND
Y2
Y2
VD D Q
VD D Q
CLK
CLK
VD D Q
AV D D
AG N D
GND
Y3
Y3
VD D Q
Y4
Y4
GND
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin
A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y5
Y5
VD D Q
Y6
Y6
GND
GND
Y7
Y7
VD D Q
P W R DW N
FBIN
FBIN
VD D Q
FBOUT
FBOUT
GND
Y8
Y8
VD D Q
Y9
Y9
GND
PS8464C
06/04/01
PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory
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Pinout Table
Pin Name
Pin No.
I/O Type
CLK
CLK
13
14
I
Yx
3,5,10,20,22,27,29,39,44,46
Yx
2,6,9,19,23,26,30,40,43,47
FBOUT
FBOUT
32
33
Feedback output, and Complement Feedback Output
FBIN
FBIN
36
35
Feedback output, and Complement Feedback Output
Reference Clock input
Clock outputs.
Complement Clock outputs.
O
Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0,
the part is powered down and the differential clock outputs are disabled to a
3- state. When PWRDWN = 1, all differential clock outputs are enabled and run at
the same frequency as CLK.
I
PWRDWN
37
VDDQ
4,11,12,15,21,28,34,38,45
AVDD
16
AGND
17
GND
1,7,8,18,24,25,31,41,42,48
De s cription
Power Supply for I/O.
Power
Ground
Analog /core power supply. AVDD can be used to bypass the PLL for testing
purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is
buffered directly to the device outputs.
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
Function Table
Inputs
Outputs
PLL State
AVDD
G
CLK
CLK
Y
Y
FBOUT
FBOUT
GND
H
L
H
L
H
L
H
Bypassed/off
GND
H
H
L
H
L
H
L
Bypassed/off
X
L
L
H
Z
Z
Z
Z
off
X
L
H
L
Z
Z
Z
Z
off
2.5V(nom)
H
L
H
L
H
L
H
on
2.5V(nom)
H
H
L
H
L
H
L
on
2.5V(nom)
X
Z
Z
Z
Z
off
<20 MHz (1)
Notes: For testing and power saving purposes, PI6CV857 will power down if the frequency of the reference inputs CLK, CLK is well
below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CV857 will be
powered down when the CLK,CLK stop running.
Z = High impedance
X = Don’t care
2
PS8464C
06/04/01
PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory
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Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
M in.
M ax.
I/O supply voltage range and analog/core supply voltage range
– 0.5
3.6
VI
Input voltage range
– 0.5
VO
Output voltage range
– 0.5
Tstg
Storage temperature
– 65
VDDQ, AVDD
Parame te r
Units
V
VDDQ+0.5
oC
150
Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Timing Requirements (Over recommended operating free-air temperature)
Symbol
fCK
tDC
tSTAB
AVDD, VDDQ = 2.5V ±0.2V
D e s cription
Units
M in.
M ax.
O perating clock frequency(1,2)
60
170
Application clock frequency(3)
95
170
Input clock duty cycle
40
60
%
100
µs
PLL stabilization time after powerup
MHz
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to
meet the other timing parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
3
PS8464C
06/04/01
PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory
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DC Specifications
Recommended Operating Conditions
Symbol
Parame te r
M in.
Nom.
M ax.
Units
AVDD
Analog/core supply voltage
2.3
2.5
2.7
VDDQ
Output supply voltage
2.3
2.5
2.7
VIL
Low- level input voltage for PWRDWN pin
–0.3
0.7
VIH
High- level input voltage for PWRDWN pin
1.7
VDDQ +0.3
VOH
High- level output voltage
1.8
VDDQ
VOL
Low- level output voltage
0
0.5
VIX
Input differential- pair crossing voltage
(VDDQ/2) –0.2
(VDDQ/2) +0.2
VOX
Output differential- pair crossing voltage at the DRAM clock input
(VDDQ/2) –0.2
(VDDQ/2) +0.2
VIN
Input voltage level
–0.3
VDDQ +0.3
VID
Input differential voltage between CK and CK
0.36
VDDQ +0.6
VOD
Output differential voltage between Y[n] and Y[n] and FBOUT
and FBOUT
0.70
VDDQ +0.6
0
70
TA
Operating free air temperature
V
°C
Electrical Characteristics
Parame te r
Te s t Conditions
AVDD, VDDQ
M in.
M ax.
Units
–1.2
V
±10
µA
300
mA
VIK
All inputs
II = –18mA
II
CK , FBIN
VI = VDDQ or GND
PWRDWN
VI = VDDQ or GND
Dynamic supply current of VDDQ
VDD = 2.7V (1)
Static supply current
CK & CK <20 MHz or
PWRDWN = Low (2)
100
µA
Dynamic supply current of AVDD
VDD = 2.7V (1)
12
mA
Static supply current
CK & CK <20 MHz or
PWRDWN = Low (2)
100
µA
3.0
pF
IDDQ
IADD
CI
CK and CK
FBIN and FBIN
2.3V
Typ.
2.7V
VI = VDD or GND
2.5V
2.0
Notes:
1. Driving 9 or 18 DDR SDRAM memory chips with 120-ohm termination resistor for each clock output pair at 134 MHz.
2. The maximum power down clock frequency is below 20 MHz.
4
PS8464C
06/04/01
PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory
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AC Specifications
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)
Parame te r
De s cription
Diagram
AVDD, VDDQ = 2.5V ±0.2V
M in.
Nom.
Units
M ax
tjit(cc)
Cycle- to- cycle jitter
see Figure 3
–75
75
t(θ)
Static phase offset(1)
see Figure 4
–50
tsk(o)
Output clock skew
see Figure 5
tjit(per)
Period jitter
see Figure 6
–75
75
tjit(hper)
Half- period jitter
see Figure 7
–100
100
tsl(i)
Input clock slew rate(2)
see Figure 8
1.0
2.0
tsl(o)
Output clock slew rate(2)
see Figure 8
1.0
2.0
0
50
100
ps
V/ns
The PLL on PI6CV857 meets the above parameters while supporting SSC synthesizers with the following parameters(3).
SSC modulation frequency
30.00
50.00
kHz
SSC clock input frequency deviation
0.00
–0.50
%
PLL loop bandwidth
2
Phase angle
MHz
–0.031
degrees
Notes:
1. Static Phase offset does not include Jitter.
2. The slew rate is determined from the IBIS model and not from the test load.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
5
PS8464C
06/04/01
PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory
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VDD
Z=60Ω
DDR
SDRAM
R=120Ω
Z=60Ω
DDR
SDRAM
PI6CV857
Figure 1. Output Load
VDDQ/2
Z= 60Ω
R = 10Ω
Z= 50Ω
C = 14pF
R = 50Ω
Z= 60Ω
–VDDQ/2
R = 10Ω
Z= 50Ω
GND
C = 14pF
R = 50Ω
–VDDQ/2
GND
PI6CV857
SCOPE
–VDDQ/2
Figure 2. Output Load Test Circuit
6
PS8464C
06/04/01
PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory
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Yx,FBOUT
Yx,FBOUT
t cycle n
t cycle n+1
t jit(cc) = t cycle n - t cycle n+1
Figure 3. Cycle-to-Cycle Jitter
CK
CK
FBIN
FBIN
t(
t(
)n
∑
1
=
) n+1
n=N
t
t(
N
)n
(N is a large number of samples)
Figure 4. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
t sk(o)
Figure 5. Output Skew
7
PS8464C
06/04/01
PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory
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Yx, FBOUT
Yx, FBOUT
t cycle n
Yx, FBOUT
Yx, FBOUT
1
fO
t jit(per) = t cycle n
1
fO
Figure 6. Period Jitter
Yx, FBOUT
Yx, FBOUT
t n+1
half period
t half period n
1
fO
t jit(hper) = t half period n
1
2*f O
Figure 7. Half-Period Jitter
80%
80%
V ID
Clock Inputs
and Outputs
20%
20%
t sl(i), t sl(o)
t sl(i), t sl(o)
Figure 8. Input and Output Slew Rates
8
PS8464C
06/04/01
PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory
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Packaging Mechanical: 48-Pin TSSOP (A)
48
.236
.244
1
6.0
6.2
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
.004 0.09
.008 0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.0197
BSC
0.50
.002
.006
0.05
0.15
.007
.010
0.17
0.27
0.45 .018
0.75 .030
.319
BSC
8.1
Ordering Information
Orde ring Code
Package
Name
Package Type
PI6CV857A
A48
48- pin, 240- mil wide TSSOP
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8464C
06/04/01