MSDL (Mobile Shrink Data Link) Transceivers for Mobile Phones Data rate 1350Mbps RGB Interface BU7964GUW No.10058EAT04 ●Description BU7964GUW is a differential serial interface connecting mobile phone LCD modules to the host CPU. Unique technology is utilized for lower power consumption and EMI. MSDL minimizes the number of wires required - an important consideration in hinge phones - resulting in greater reliability and design flexibility. ●Features 1) MSDL3 high-speed differential interface with a maximum transfer rate of 1350 Mbps. 2) Compatible with24-bit RGB video mode for LCD controller-to-LCD interface. 3) Pixel clock frequency range from 4 to 45MHz. 4) Depending on the data transfer rate, either, two or three differential data channels can be selected. ●Applications Serial Interface for LCD Display Interface of Mobile Devices Application. ●Absolute Maximum Ratings Parameter Power Supply Voltage Input Voltage Output Voltage Input Current Symbol Ratings Unit Remarks DVDD -0.3 ~ +2.5 V - MSVDD -0.3 ~ +2.5 V - -0.3 ~ MSVDD+0.3 V I/O terminals of MSVDD line VIN VOUT -0.3 ~ DVDD+0.3 V I/O terminals of DVDD line -0.3 ~ MSVDD+0.3 V I/O terminals of MSVDD line -0.3 ~ DVDD+0.3 V I/O terminals of DVDD line IIN -10 ~ +10 mA - Output Current IOUT -70 ~ +70 mA - Preservation Temperature Tstg -55 ~ +125 ℃ - Unit Conditions ●Operating Conditions Parameter Symbol Ratings Min Typ Max Supply Voltage for DVDD VDVDD 1.65 1.80 1.95 V Supply Voltage for MSVDD VMSVDD 1.65 1.80 1.95 V Data Transmission Rate DR 120 - 450 Mbps/ch - Operating Temperature Range Topr -30 25 85 ℃ - www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/18 VDVDD = VMSVDD 2010.04 - Rev.A Technical Note BU7964GUW ●Package View 1PIN MARK 5.0±0.1 BU7964 LOT NO. 0.9 MAX 5.0±0.1 0.08 0.10 S S 0.75±0.1 0.75±0.1 A P = 0.5×7 0.5 63-φ0.295±0.05 0.05 M S AB H B G P = 0.5×7 F E D C B A 1 2 3 4 5 6 7 8 (UNIT:mm) Fig.1. Package View (VBGA063W50) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/18 2010.04 - Rev.A Technical Note BU7964GUW ●Block Diagram MSVDD DVDD High Speed I/F D0 D0+ D1 D1+ PD Serial to Parallel Error Detection I/F Logic PLL Timing Generator PCLK Control CPO D2 D2+ CLKCLK+ Link Monitor Reset Generator PCLK XSD LS DRVR Control Logic Reference F_XS PLLBW TEST MSGND DGND Fig.2. Block Diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/18 2010.04 - Rev.A Technical Note BU7964GUW ●Pin Layout A 1 2 3 4 5 6 7 8 TEST0 PD19 PD17 PD16 PD14 PD13 PD10 CPO PCLK PD18 PD15 PD12 PD11 PD9 PD8 B C PD22 PD20 PLL_BW0 DVDD N.C. F_XS PD7 PD6 D PD23 PD21 N.C. DGND DGND DVDD PD4 PD5 E PD25 PD24 DVDD DGND MSGND N.C. PD1 PD3 F PD26 LS0 MSVDD MSGND MSVDD N.C. XSD PD2 G LS1 PLL_BW1 D2- D1- CLK- D0- N.C. PD0 H N.C. N.C. D2+ D1+ CLK+ D0+ DRVR TEST1 Fig.3. Pin Layout (Top View) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/18 2010.04 - Rev.A Technical Note BU7964GUW ●Pin Functions Table 1. Power Supply and Ground Power Supply / Ground: 10-pin Name Width Functions DVDD 3 Logic core, CMOS I/O power supply. MSVDD 2 Analog core power supply. DGND 3 CMOS I/O and logic core ground. MSGND 2 Analog core ground. Table 2. MSDL3 High-Speed Serial Interface: 8-pin Shutdown Equivalent Schematic CLK+pin. Pull Down D I CLK-pin. Pull Down D Analog I D0+pin. Pull Down D 1 Analog I D0-pin. Pull Down D D1+ 1 Analog I D1+pin. Pull Down D D1- 1 Analog I D1-pin. Pull Down D D2+ 1 Analog I D2+pin. Pull Down D D2- 1 Analog I D2-pin. Pull Down D Shutdown Equivalent Schematic - D Shutdown Equivalent Schematic Name Width Level I/O CLK+ 1 Analog I CLK- 1 Analog D0+ 1 D0- Functions Table 3. Analog Analog: 1-pin Name Width Level I/O DRVR 1 Analog - Functions 10kΩ ± 5% register should be connected between DRVR and MSGND. Table 4. Parallel Data Interface Parallel Data Interface: 29-pin Name Width Level I/O PCLK 1 CMOS O PCLK interface. ‘L’ C PD[26:0] 27 CMOS O Parallel data interface. ‘L’ C CPO 1 CMOS O Parity error toggled output, normally ‘L,’ output is toggled during one PCLK period when a parity error is detected ‘L’ C www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Functions 5/18 2010.04 - Rev.A Technical Note BU7964GUW Table 5. Control Control: 8-pin Shutdown Equivalent Schematic Shutdown pin. ‘L’: shutdown. ‘H’: normal operation. Input A I Selection of the number of data channel and the data format. Refer to section 0. * Set the same number of data channel bet wean the TX device and the RX device. Input A CMOS I Selection of CMOS output rising and falling slope ‘L’: slow ‘H’: fast Input A CMOS I Selection of PLL bandwidth. Input A I Test mode pins. ‘L’: normal mode. ‘H’: test mode. Must be open or ‘L.’ Name Width Level I/O XSD 1 CMOS I LS0 1 CMOS LS1 1 F_XS 1 PLL_BW0 1 PLL_BW1 1 TEST0 1 Pull down TEST1 1 B Input B DVDD DVDD A Functions B MSVDD DVDD C D Fig.4. Equivalent Schematics www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/18 2010.04 - Rev.A Technical Note BU7964GUW ●Operation Control MSDL3 Channel Count Selection Pins LS0 and LS1 are used to control the high-speed data channel count and data format. High-speed data channel count, data format should be the same between the transmitting and receiving devices (the BU7963GUW and BU7964GUW, respectively). Table 6 shows and Receipt Data rate ranges for the LS pin settings. Table 6. The Range of The Receipt Data rate LS1 LS0 The Number of Data Channel The Range of PCLK Input Frequency [MHz] The Range of The Data Receipt Rate [Mbits/sec] ‘L’ ‘L’ 1-channel (27-bit format). 4.0-15.0 120-450 ‘L’ ‘H’ 2-channel (27-bit format). 8.0-30.0 240-900 ‘H’ ‘L’ 3-channel (27-bit format). 12.0-45.0 360-1350 CMOS Output Drivability Selection F_XS determines output drivability of the parallel data interface. Table 7 shows output drivability. Table 7. Output Drivability Output Drivability F_XS ‘L’ 1mA Type ‘H’ 3mA Type PLL Bandwidth Selection BU7964GUW controls the range of the CLK+ / CLK− input frequency (= PCLK output frequency) by the setting of the data format (LS1, and LS0) of the high-speed data channel and the bandwidth setting of PLL_BW0 and PLL_BW1. Table 8. PLL Bandwidth Selection LS1 LS0 PLL_BW1 PLL_BW0 CLK+/CLK- Frequency Range [MHz] (PCLK Input Frequency) Min Max ‘L’ ‘L’ ‘L’ ‘L’ 4 7 ‘L’ ‘L’ ‘L’ ‘H’ 6 11 ‘L’ ‘L’ ‘H’ ‘L’ 10 15 ‘L’ ‘H’ ‘L’ ‘L’ 8 14 ‘L’ ‘H’ ‘L’ ‘H’ 12 22 ‘L’ ‘H’ ‘H’ ‘L’ 20 30 ‘H’ ‘L’ ‘L’ ‘L’ 12 21 ‘H’ ‘L’ ‘L’ ‘H’ 18 33 ‘H’ ‘L’ ‘H’ ‘L’ 30 45 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/18 2010.04 - Rev.A Technical Note BU7964GUW ●Power Modes BU7964UW has three power modes. 1) Shutdown Mode BU7964GUW goes to Shutdown Mode when XSD = ‘L.’ AII logic circuits are initialized in the Shutdown Mode. All high-speed signaling are pulled down to MSGND. All parallel data interface output ‘L’. 2) Standby Mode BU7964GUW goes to a Standby Mode when XSD = ‘H’ and CLK+ / CLK− is Hi-Z. All high-speed signaling inputs sink DC current in order to pull the pins down to MSGND. BU7964GUW is monitoring VCM of CLK+ / CLK−. When TX device starts driving high-speed signaling outputs, BU7964GUW detects its VCM and switches to Active Mode. In Standby Mode, All parallel data interface output ‘L’. 3) Active Mode BU7964UW goes to Active Mode when XSD = ‘H’ and VCM is running. Table 9. Power Modes Input Power Mode Operation XSD Vcm of CLK+/CLK- Functions MSDL3 Terminals Parallel output Shutdown ‘L’ MSGND Initialized Disabled(Pull-down) Initial value Standby ‘H’ MSGND MSDL3 Vcm detection MSDL3 Vcm detection (Pull-down) Initial value Active ‘H’ Clock input is active MSDL3 VCM monitor. Normal operation. (S2P conv) MSDL3 VCM monitor. Enabled. Normal operation 4) Power Modes Transition Fig.5.shows the Transition of power modes. XSD = ”L” Shutdown XSD = ”H” Standby PCLK input disabled (Hi-z) PCLK input detected Active Fig.5. Power Modes Transition www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/18 2010.04 - Rev.A Technical Note BU7964GUW ●Link Error Detection Detection of Parity Error BU7964GUW counts the number of ‘H’ bits in PD[26:0] and CP in every pixel information received and detects parity error as follows: ・There is no parity error occurred if the number of ‘H’ bits in PD[26:0] and CP is odd. ・There is parity error occurred if the number of ‘H’ bits in PD[26:0] and CP is even. If parity error is detected, BU7964GUW outputs the previous error-free pixel information and discards the invalid pixel information. At the same time, BU7964GUW toggles CPO during one PCLK period. BU7964GUW outputs initial value, if the parity error is detected when there is no previous pixel information. Otherwise, BU7964GUW outputs the received pixel information from the high-speed data channel(s) and CPO keeps ‘L.’ Error correction is not supported in BU7964GUW. ●High-Speed Data Channel Protocols Fig.6 Fig.7 and Fig.8 show high-speed data channel protocols. CP D0channel PD26 PD25 PD24 PD23 CLK channel PD22 PD21 PD20 PD19 PD18 PD17 PD3 PD2 PD16 PD15 PD14 PD13 PD12 Frame start / end PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD1 PD0 res res PD16 PD15 PD2 PD1 CP PD26 PD25 res CP PD26 PD0 res PD14 Fig.6. MSDL3 Protocol for 1-channel Data (27-bit) D0channel CP PD26 PD25 PD24 D1channel res PD14 PD13 PD12 PD11 PD10 PD23 PD22 PD21 PD20 PD9 PD8 PD19 PD18 PD17 PD7 PD6 PD5 PD4 PD3 CLK channel Frame start / end Fig.7. MSDL3 Protocol for 2-channel Data (27-bit) D0channel CP PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD2 CP PD26 D1channel res PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD1 res PD18 D2channel res PD10 PD9 PD7 PD6 PD3 PD0 res PD10 PD8 PD5 PD4 CLK channel Frame start / end Fig.8. MSDL3 Protocol for 3-channel Data (27-bit) “res” is reserved bit for the future use, the default state of those is ‘0.’ CP is the parity bit of data payload. BU7964GUW adds an odd parity on CP of the high-speed channel data. ・When the number of ‘H’ bits in parallel data is even, CP bit is ‘H.’ ・When the number of ‘H’ bits in parallel data is odd, CP bit is ‘L.’ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/18 2010.04 - Rev.A Technical Note BU7964GUW ●Electrical Characteristics 1) DC Characteristics Table 10. Digital Input / Output DC Characteristics Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter Limits Symbol Min Typ Max Unit ‘L’ Input Voltage 1 VIL1 DGND - 0.3 x DVDD V ‘H’ Input Voltage 1 VIH1 0.7 x DVDD - DVDD V Output ‘L’ Voltage1 VOL1 DGND - 0.3 x DVDD V Output ‘H’ Voltage1 VOH1 0.7 x DVDD - DVDD V Output ‘L’ Voltage2 VOL2 DGND - 0.3 x DVDD V Output ‘H’ Voltage2 VOH2 0.7 x DVDD - DVDD V Output ‘L’ Voltage3 VOL3 DGND - 0.15 x DVDD V Output ‘H’ Voltage3 VOH3 0.85 x DVDD - DVDD V Conditions XSD, F_XS PLL_BW[1:0], LS[1:0]Pin XSD, F_XS PLL_BW[1:0], LS[1:0]Pin F_XS=‘L’, IO = 1mA, PCLK, CPO, PD[26:0]Pin F_XS=‘L’, IO = -1mA, PCLK, CPO, PD[26:0]Pin F_XS=‘H’, IO = 3mA, PCLK, CPO, PD[26:0]Pin F_XS=‘H’, IO = -3mA, PCLK, CPO, PD[26:0]Pin IO = 100µA, PCLK, CPO, PD[26:0]Pin IO = -100µA, PCLK, CPO, PD[26:0]Pin Table 11. Current Consumption Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter Symbol Shutdown Current Standby Current Active Current 1-channel / 27-bit Format Active Current 2-channel / 27-bit Format Active Current 3-channel / 27- bit Format Limits Unit Conditions Min Typ Max Iop_sht_rx - 0.2 10 µA XSD = ‘L’, IDVDD + IMSVDD Iop_stb_rx - 41.8 90 µA XSD = ‘H’, IDVDD + IMSVDD mA LS[1:0] = “LL”, PLL_BW[1:0] = “HL”, DVDD = MSVDD, PCLK = 15MHz, XSD = ‘H’, CL = 10pF, Total operating current (IDVDD + IMSVDD) with PD[26:0] outputs toggling 0x2AAAAAA and 0x5555555 mA LS[1:0] = “LH”, PLL_BW[1:0] = “HL” , DVDD = MSVDD, PCLK = 30MHz, XSD = ‘H’, CL = 10pF, Total operating current (IDVDD + IMSVDD) with PD[26:0] outputs toggling 0x2AAAAAA and 0x5555555 mA LS[1:0] = “HL”, PLL_BW[1:0] = “HL” , DVDD = MSVDD, PCLK = 45MHz, XSD = ‘H’, CL = 10pF, Total operating current (IDVDD + IMSVDD) with PD[26:0] outputs toggling 0x2AAAAAA and 0x5555555 Iop_act_rx1 Iop_act_rx2 Iop_act_rx3 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. - - - 17.6 28.0 36.0 10/18 24.0 36.8 48.6 2010.04 - Rev.A Technical Note BU7964GUW 2) AC Characteristics Parallel Data Output Timing tR tR _D tR tR _R, _F _D 0.7×DVDD P [2 : 0] 0.5×DVDD 0.3×DVDD PCL 0.5×DVDD tR tR _DUTY _PCLK Fig.9. Parallel Data Output Timing Table 12. Parallel Data Output AC Timing Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter Symbol PCLK Output Duty Cycle tRX_DUTY Output Data Setup Time tRX_DS Output Data Hold Time tRX_DH Output Data Rise Time/Fall time tRX_R tRX_F www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Limits Unit Conditions Min Typ Max 45 0.41X 50 55 % CL=10pF - - ns CL=10pF tRx_PCLK 0.41X tRx_PCLK - - - ns CL=10pF 9 - ns F_XS=0, CL=10pF - 3 - ns F_XS=1, CL=10pF 11/18 2010.04 - Rev.A Technical Note BU7964GUW 3) Power-On / Off Sequence Power-On Sequence Fig.10 shows power-on sequence of BU7964GUW. DVDD ,MSVDD of Tx tTX_VDD_XSD XSD of Tx PCLK of Tx t TX_IN_VAL Provided Stopped tTX_OUT_VAL Tx MSDL 3 Output DVDD ,MSVDD of Rx HiZ Valid tRX_VDD_XSD XSD of Rx Rx Power mode t RX_IN_VAL Standby / Active Shutdown t RX_OUT_VAL Rx All Outputs Valid Outputs Initial Value Tx : BU 7963 GUW Rx: BU 7964 GUW Fig.10. Power-On Sequence Table 13. Power-On Sequence Timing Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter Symbol Limits Unit Min Typ Max Reset Valid After Power Supplied tRX_VDD_XSD 10 - - µs PCLK Valid After XSD Released tRX_IN_VAL - - 10 µs Parallel Data Valid After TX HighSpeed Signals Valid tRX_OUT_VAL - - 2 ms www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/18 Conditions 2010.04 - Rev.A Technical Note BU7964GUW Power-Off Sequence Fig.11 shows the power-off sequence of BU7964GUW. PCLK of Tx Provided Stopped t TX_OUT_INV Tx MSDL 3 Output HiZ Valid t RX_OUT_INV Rx All Outputs Valid Outputs Initial Value XSD of Tx DVDD ,MSVDD of Tx t TX_XSD_VDD XSD of Rx DVDD ,MSVDD of Rx t RX_XSD_VDD Tx : BU 7963 GUW Rx: BU 7964 GUW Fig.11. Power-Off Sequence Timing Table 14. Power-Off Sequence Timing Ta=25°C, DVDD=MSVDD=1.80V, DGND=MSGND=0.00V, unless otherwise noted. Parameter Symbol Limits Min Typ Max Unit Parallel output delay time tRX_OUT_INV - - 100 µs XSD hold time tRX_XSD_VDD 10 - - µs www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/18 Conditions 2010.04 - Rev.A Technical Note BU7964GUW ●Frequency Change Sequence Fig.12 shows the frequency change sequence of BU7964GUW. DVDD , MSVDD of Tx and Rx t TX_XSD_OUT XSD of Tx PCLK of Tx tTX_IN_XSD Frequency 1 Frequency 2 t TX_XSD_CTL PLL _BW[ 1 :0] of Tx t TX_CTL_XSD State 2 State 1 XSD of Rx tRX_XSD_CTL PLL _BW[ 1 :0] of Rx t RX_CTL_XSD State 1 State 2 Tx : BU 7963 GUW Rx: BU 7964 GUW Fig.12. Frequency Change Sequence Table 15. Frequency Change Sequence Timing Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter Symbol Limits Min Typ Max Unit Control Signal Hold Time tRX_XSD_CTL 2.0 - - µs Control Signal Setup Time tRX_CTL_XSD 2.0 - - µs www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/18 Conditions 2010.04 - Rev.A Technical Note BU7964GUW ●High-Speed Channel Characteristic Table 16. High-speed channel characteristic Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter Symbol Differential Voltage Range Limits Min Typ Max Unit Vdiff_rx 70 100 200 mVpp LOW-level threshold voltage Vthl -40 - - mV HIGH-level threshold voltage Vthh - - 40 mV Common Mode Voltage Range Vcm_rx 0.6 0.9 1.2 V Internal termination resistance R_rx 75 100 125 Ω Operating Frequency fopr_rx - - 225 MHz RX sink current IPULL_RX 12 30 90 µA Link detection threshold voltage VLINK_RX 0.2 0.3 0.4 V Conditions fopr_rx Single-end InP(D0+,D1+,D2+) Vcm_rx InN(D0-,D1-,D2-) Vdiff_rx Differential (InP-InN) Differential (InP-InN) 0 Vthh 0 Vthl Fig.13. High-Speed Channel Characteristic Fig.14 shows high-speed channel equivalent schematic. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/18 2010.04 - Rev.A Technical Note BU7964GUW MSDL 3 TX MSVDD MSDL 3 RX Transmission line VO + ILEA ILEA _T _R MSVDD Logical input to MSDL 3 TX RT / 2 RR / 2 RT / 2 RR / 2 VI+ Logical output from MSDL 3 RX VIMSGND VO - ILEA ILEA _T MSVDD _R IPUL MSGND MSGND _R V LIN Link detection comparator output VC _R MSGND Fig.14. High-Speed Channel Equivalent Schematic. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/18 2010.04 - Rev.A Technical Note BU7964GUW ●Application Circuit Example 1.8V 1.8V 0.1μ×2 0.1μ×3 D0+ D0- D1+ D1- D1+ D1- D2+ D2- D2+ D2- DGND DGND MSVDD DVDD 27 PD[26:0] CPO R[7:0],G[7:0],B[7:0], HS,VS,DE DVDD PLLBW1 PLLBW0 LS1 LS0 F_XS DRVR WVGA LCD panel TEST[1:0] XSD XSD TEST[1:0] Pixel clock PCLK BU7964GUW （Rx device） D0+ D0- DRVR RVS CLK+ CLK- Video Mode LCD Controller Reset PLLBW POL_PCLK LS1 LS0 MSGND 1.8V GND 10KΩ±5% DVDD Reset 1.8V GND 10KΩ±5% CKD BU7963GUW （Tx device） PD[26:0] MSGND DVDD DGND 27 100p×3 100p×2 CLK+ CLK- PCLK Pixel clock R[7:0],G[7:0],B[7:0], HS,VS,DE MSVDD 100p×2 100p×3 MPU 1.8V 1.8V 0.1μ×3 0.1μ×2 MSGND MSGND DGND Fig.15. Application Circuit www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 17/18 2010.04 - Rev.A Technical Note BU7964GUW ●Ordering Part Number B U 7 Part No. 9 6 4 G Part No. U W Package GUW: VBGA063W050 - E 2 Packaging and forming specification E2: Embossed tape and reel VBGA063W050 <Tape and Reel information> 5.0 ± 0.1 5.0±0.1 0.08 S 63- φ 0.295±0.05 φ 0.05 M S AB P=0.5×7 0.5 0.1 0.9MAX 1PIN MARK Tape Embossed carrier tape (with dry pack) Quantity 2500pcs Direction of feed S E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 0.75±0.1 0.5 B 12345678 0.75± 0.1 H G F E D C B A P=0.5× 7 A www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1pin (Unit : mm) Reel 18/18 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2010.04 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. R1010A