S-77100/77101 Series www.sii-ic.com © SII Semiconductor Corporation, 2015 POWER SEQUENCER Rev.1.0_01 The S-77100/77101 Series is a power sequencer. The S-77100 Series can output enable signals of 4 channels, and controls the external power supply circuit. The S-77100 Series turns on and off the enable signals successively by changing "H" and "L" of the ON pin. The S-77101 Series can output enable signals of 3 channels, and controls the external power supply circuit. The S-77101 Series turns on the enable_______ signals successively by changing the ON pin from "L" to "H", and turns off the enable signals successively by changing OFF pin from "H" to "L". The delay time for each enable signal can be set by the external capacitor. Also, the small 8-Pin TSSOP or SNT-8A package makes high-density mounting possible. Features • Easy support for sequencing of multiple power supplies. • Delay time can be set by the external capacitor. • Sequence operations of 4 channels can be controlled by 1 input signal. (S-77100 Series) • On-sequence operation and off-sequence operation can be controlled by the separate input signal. (S-77101 Series) • Enable output can be increased by cascade connection. • Low current consumption: 3.0 μA typ. (Off period, power-good period, VDD = 3.3 V, Ta = +25°C) • Wide range of operation voltage: 2.2 V to 5.5 V • Operation temperature range: Ta = −40°C to +85°C • Output form is selectable: CMOS output, Nch open-drain output • Output logic is selectable: Active "H", active "L" • Lead-free (Sn 100%), halogen-free: Applications • • • • Power sequencing for multiple devices Sequencing for microprocessor and microcontroller Power sequencing for FPGA Power sequencing for TV, camera, printer, etc. Packages • 8-Pin TSSOP • SNT-8A 1 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Block Diagrams 1. S-77100 Series ON Status control circuit UVLO *1 ENBL_A Comparator CDLY Charge / discharge selection circuit ENBL_B Latch circuit ENBL_C VDD VSS ENBL_D *1. Selectable as the option Figure 1 2. S-77101 Series ON Status control circuit UVLO OFF *1 ENBL_A CDLY Comparator Charge / discharge selection circuit Latch circuit ENBL_B VDD VSS ENBL_C *1. Selectable as the option Figure 2 2 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Product Name Structure _______ Users can select the presence of the OFF pin, order of enable output, and output form, etc. for the S-77100/77101 Series. Refer to "1. Product name" regarding the contents of product name, "2. Product option list" regarding the product type, "3. Packages" regarding the package drawings. 1. Product name S-7710 x x xx - xxxx U 4 Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications*1 T8T1: 8-Pin TSSOP, Tape I8T1: SNT-8A, Tape Option code 2*2 *3 Option code 1 A: Reverse type B: Forward type Number of channel _______ 0: 4 channels (without OFF pin) _______ 1: 3 channels (with OFF pin) *1. *2. *3. 2. Refer to the tape drawing. Code added by the optional function that is user-selected. Refer to "2. Product option list" for the kinds of options. Please contact our sales office for the option code 2. Refer to "2. Product option list". Product option list Table 1 Option Order of enable output (Option code 1) Number of times of external capacitor (CDLY) charge and discharge (Option code 2) Input level (Option code 2) Output form (Option code 2) Output logic (Option code 2) Description The order that the enable output (ENBL_x pin) inverts during off-sequence period can be selected. The S-77100 Series A: The ENBL_D pin, the ENBL_C pin, the ENBL_B pin and the ENBL_A pin change to "L" in turn. B: The ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin change to "L" in turn. The S-77101 Series A: The ENBL_C pin, the ENBL_B pin and the ENBL_A pin change to "L" in turn. B: The ENBL_A pin, the ENBL_B pin and the ENBL_C pin change to "L" in turn. Option for the delay time (tDLY) adjustment. The number of times of CDLY charge and discharge can be selected. 2 times / 4 times / 8 times / 16 times This datasheet describes the example when "4 times" is selected. _______ Input level of the ON pin and the OFF pin can be selected. Schmitt trigger input / Comparator input Output form of the ENBL_x pin can be selected. CMOS output / Nch open-drain output Output logic of the ENBL_x pin can be selected. Active "H": The type which is "H" during power-good period. / Active "L": The type which is "L" during power-good period. This datasheet describes the example when active "H" is selected. 3 POWER SEQUENCER S-77100/77101 Series 3. Rev.1.0_01 Packages Table 2 Package Name 8-Pin TSSOP SNT-8A Dimension FT008-A-P-SD PH008-A-P-SD Package Drawing Codes Tape FT008-E-C-SD PH008-A-C-SD Reel FT008-E-R-S1 PH008-A-R-SD Land − PH008-A-L-SD Pin Configurations 1. 8-Pin TSSOP Top view Table 3 1 2 3 4 8 7 6 5 Figure 3 Pin No. Symbol 1 2 3 4 5 ENBL_A ENBL_B CDLY VSS ON ENBL_D*1 _______ 6 OFF*2 7 ENBL_C 8 VDD *1. The S-77100 Series only *2. The S-77101 Series only Description Enable signal output pin Enable signal output pin External capacitor (CDLY) connection pin GND pin Enable trigger input pin Enable signal output pin Disable trigger input pin Enable signal output pin Positive power supply pin 2. SNT-8A Top view 1 2 3 4 8 7 6 5 Figure 4 4 Table 4 Pin No. 1 2 3 4 5 Symbol ENBL_A ENBL_B CDLY VSS ON *1 ENBL_D _______ 6 *2 OFF 7 ENBL_C 8 VDD *1. The S-77100 Series only *2. The S-77101 Series only Description Enable signal output pin Enable signal output pin External capacitor (CDLY) connection pin GND pin Enable trigger input pin Enable signal output pin Disable trigger input pin Enable signal output pin Positive power supply pin Rev.1.0_01 POWER SEQUENCER S-77100/77101 Series Pin Functions 1. ON pin This is a trigger input pin to start the sequence operation. In the S-77100 Series, the on-sequence operation is performed when the rising signal is detected. The off-sequence operation is performed when the falling signal is detected. In the S-77101 Series, the on-sequence operation is performed when the rising signal is detected. Refer to "1. Sequence operation" in " Operation" for details. 2. _______ OFF pin (S-77101 Series only) This is a trigger input pin to start the off-sequence operation. The off-sequence operation is performed when the falling signal is detected. Refer to "1. Sequence operation" in " Operation" for details. 3. ENBL_A, ENBL_B, ENBL_C, ENBL_D pins (ENBL_D pin is S-77100 Series only) These are pins to output the enable signals to the external power supply circuits. The ENBL_x pin output form of Nch open-drain output / CMOS output can be selected as the option. Moreover, the ENBL_x pin output logic of active "H" / active "L" can be selected as the option. Refer to "1. Sequence operation" in " Operation" for the sequence operation, "2. Product option list" in " Product Name Structure" for the options. 4. CDLY pin This is a pin for connecting the external capacitor (CDLY) in order to generate the delay time (tDLY) of the on-sequence operation and the off-sequence operation. CDLY is charged and discharged by the constant current circuit. The charge-discharge operation starts when the ON pin rises, the period from the starting to the ENBL_A pin rising is tDLY which is generated by the S-77100/77101 Series. Refer to "1. Sequence Operation" in " Operation" for the operation timing, " Relation between Delay Time and External Capacitor" for the delay time. 5. VDD pin Connect this pin with a positive power supply. Refer to " Electrical Characteristics" for the values of voltage to be applied. 6. VSS pin Connect this pin to GND. 5 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Absolute Maximum Ratings Table 5 Item Power supply voltage Input voltage Symbol Applicable Pin VDD VIN VDD _______ ON, OFF (S-77101 Series only) Output voltage VOUT ENBL_A, ENBL_B, ENBL_C, ENBL_D (S-77100 Series only) Absolute Maximum Rating VSS − 0.3 to VSS + 6.5 VSS − 0.3 to VDD + 0.3*1 Nch open-drain VSS − 0.3 to VSS + 6.5 output VSS − 0.3 to VDD + 0.3*1 CMOS output Unit V V V V Operation ambient Topr − −40 to +85 °C temperature*2 Storage temperature Tstg − −55 to +150 °C *1. Be sure not to exceed 6.5 V. *2. Conditions with no condensation or frost. Condensation or frost causes short-circuiting between pins, resulting in a malfunction. Caution 6 The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Electrical Characteristics Table 6 Item Symbol (Ta = −40°C to +85°C, VDD = 2.2 V to 5.5 V, VSS = 0 V unless otherwise specified) Applied Pin Condition Typ.*1 Min. Max. Unit Operation power supply voltage VDD VDD Current consumption 1 (Off period) IDD1 VDD Current consumption 2 (Power-good period) IDD2 VDD IDD3 VDD VUVLO IIZH IIZL VDD _______ ON, _______ OFF *2 ON, OFF *2 VIL ON, OFF *2 VIH ON, OFF *2 VIT_ON ON, OFF *2 Current consumption 3 (On-sequence period, off-sequence period) Low voltage detection voltage High level input leakage current Low level input leakage current − V, VDD = 3.3_______ ON pin, OFF pin*2 = VSS, ENBL_x pin = Open V, VDD = 3.3_______ ON pin, OFF pin*2 = VDD, ENBL_x pin = Open V, VDD = 3.3_______ ON pin, OFF pin*2 = VDD or VSS, ENBL_x pin = Open − VIN = VDD VIN = VSS 2.2 − 5.5 V − 3.0 6.0 μA − 3.0 6.0 μA − − 8.0 μA 1.85 −0.3 −0.3 VSS − 0.3 0.8 × VDD 2.0 − − 2.13 0.3 0.3 0.2 × VDD VDD + 0.3 V μA μA 0.3 0.8 1.3 V VOUT = VDD −0.3 − 0.3 μA VOUT = VSS −0.3 − 0.3 μA − − 0.4 V 0.8 × VDD − − V 40 45 50 ms _______ Input voltage (When Schmitt trigger input is selected) Input threshold voltage (When comparator input is selected) _______ IOZH Low level output leakage current*3 IOZL Low level output voltage VOL High level output voltage*5 VOH *1. *2. *3. *4. *5. *6. − _______ High level output leakage current*3 Delay time*6 − tDLY ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 − IOL = 2.0 mA IOH = −0.4 mA Ta = +25°C, VDD = 3.3 V, The period from ENBL_A pin rising to ENBL_B pin rising, CDLY = 10 nF, The number of times of CDLY charge and discharge = 4 times − − V V Typ. values are the values at the time of Ta = +25°C. The S-77101 Series only When Nch open-drain output is selected as the option. The S-77100 Series only When CMOS output is selected as the option. The delay time varies depending on the usage environment. Perform thorough evaluation using the actual application to set the constant. Refer to " Relation between Delay Time and External Capacitors" for details. 7 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Operation 1. Sequence operation 1. 1 S-77100A (Reverse type), S-77100B (Forward type) The S-77100 Series has enable outputs of 4 channels (the ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin). The order of the off-sequence operation is different in reverse type and forward type. 1. 1. 1 Sequence operation outline (1) On-sequence operation After the ON pin changes from "L" to "H", the external capacitor (CDLY) charge operation is started, and the discharge operation is performed when CDLY is fully charged. The period during which this is repeated n times is the delay time (tDLY), and the ENBL_A pin changes to "H". Similarly, each time tDLY elapses, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin change to "H" in turn. The period from when the ON pin changes from "L" to "H" to when the ENBL_D pin changes to "H" is called "on-sequence period". (2) Off-sequence operation After the ON pin changes from "H" to "L", CDLY charge operation is started, and the discharge operation is performed when CDLY is fully charged. The period during which this is repeated n times is tDLY, and the ENBL_D pin, the ENBL_C pin, the ENBL_B pin and the ENBL_A pin change to "L" in turn in S-77100A. The ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin change to "L" in turn in S-77100B. The period from when the ON pin changes from "H" to "L" to when the ENBL_A pin in S-77100A or the ENBL_D pin in S-77100B changes to "L" is called "off-sequence period". Do not change the ON pin during on-sequence period and off-sequence period in order to perform the sequence operation normally. The number of times of CDLY charge and discharge which determines tDLY can be selected from 2 times / 4 times / 8 times / 16 times as the option. CDLY charge operation and discharge operation to generate tDLY are performed by the constant current circuit. Refer to " Relation between Delay Time and External Capacitor" for the relation of CDLY and tDLY. In addition, the period from when the ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin all change to "H" to when the off-sequence operation starts is called "power-good period", and the period from when the ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin all change to "L" to when the on-sequence operation starts is called "off period". Refer to Figure 5 for the peripheral circuit connection example. Timing charts are shown in Figure 6 and Figure 7 for S-77100A and S-77100B, respectively. 5 V AUX DC-DC LDO 3.3 V IN OUT 0.1 F S-77100 Series VDD IN Sequence controller ENBL_A ON ENBL_B EN DC-DC LDO IN ENBL_C ENBL_D CDLY OUT OUT EN DC-DC LDO 2.5 V DC-DC LDO IN OUT EN DC-DC LDO IN OUT EN 1.8 V 1.5 V 1.1 V I/O LOGIC MEMORY CORE SoC VSS Remark The ENBL_x pin is CMOS output. Figure 5 Peripheral Circuit Connection Example (S-77100A: Reverse type, S-77100B: Forward type) Caution 1. 2. 8 The input should be performed after the power supply voltage applied to the S-77100 Series becomes stable condition. The above connection diagram does not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Off period On-sequence period Power-good period Off-sequence period Off period ON CDLY n times*1 n times*1 ENBL_A ENBL_B ENBL_C ENBL_D 2.5 V : I/O 1.8 V : LOGIC 1.5 V : MEMORY 1.1 V : CORE tDLY *1. tDLY tDLY tDLY tDLY tDLY tDLY tDLY Selectable as the option: 2 times / 4 times / 8 times / 16 times Figure 6 Off period Timing Chart (S-77100A: Reverse Type) On-sequence period Power-good period Off-sequence period Off period ON CDLY n times*1 n times*1 ENBL_A ENBL_B ENBL_C ENBL_D 2.5 V : I/O 1.8 V : LOGIC 1.5 V : MEMORY 1.1 V : CORE tDLY *1. tDLY tDLY tDLY tDLY tDLY tDLY tDLY Selectable as the option: 2 times / 4 times / 8 times / 16 times Figure 7 Timing Chart (S-77100B: Forward type) 9 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 _______ 1. 2 _______ S-77101A (Reverse type, with OFF pin), S-77101B (Forward type, with OFF pin) The _______ S-77101 Series has enable outputs of 3 channels (the ENBL_A pin, the ENBL_B pin and the ENBL_C pin) and the OFF pin. The order of the off-sequence operation is different in reverse type and forward type. 1. 2. 1 Sequence operation outline (1) On-sequence operation After the ON pin changes from "L" to "H", the external capacitor (CDLY) charge operation is started, and the discharge operation is performed when CDLY is fully charged. The period during which this is repeated n times is the delay time (tDLY), and the ENBL_A pin changes to "H". Similarly, each time tDLY elapses, the ENBL_B pin and the ENBL_C pin change to "H" in turn. The period from when the ON pin changes from "L" to "H" to when the ENBL_C pin changes to "H" is called "on-sequence period". (2) Off-sequence operation _______ After the OFF pin changes from "H" to "L", CDLY charge operation is started, and the discharge operation is performed when CDLY is fully charged. The period during which this is repeated n times is tDLY, and the ENBL_C pin, the ENBL_B pin and the ENBL_A pin change to "L" in turn in S-77101A. The ENBL_A_______ pin, the ENBL_B pin and the ENBL_C pin change to "L" in turn in S-77101B. The period from when the OFF pin changes from "H" to "L" to when the ENBL_A pin in S-77101A or the ENBL_C pin in S-77101B changes to "L" is called "off-sequence period". _______ Do not change the ON pin and the OFF pin during on-sequence period and off-sequence period in order to perform the sequence operation normally. The number of times of CDLY charge and discharge which determines tDLY can be selected from 2 times / 4 times / 8 times / 16 times as the option. CDLY charge operation and the discharge operation to generate the tDLY are performed by the constant current circuit. Refer to " Relation between Delay Time and External Capacitor" for the relation of CDLY and tDLY. In addition, the period from when the ENBL_A pin, the ENBL_B pin and the ENBL_C pin all change to "H" to when the off-sequence operation starts is called "power-good period", and the period from when the ENBL_A pin, the ENBL_B pin and the ENBL_C pin all change to "L" to when the on-sequence operation starts is called "off period". The sequence operation is not affected even if the ON pin changes from "H" to "L" during _______ power-good period or the OFF pin changes from "L" to "H" during off period. Refer to Figure 8 for the peripheral circuit connection example. Timing charts are shown in Figure 9 and Figure 10 for S-77101A and S-77101B, respectively. 5 V AUX DC-DC LDO 3.3 V IN OUT 0.1 F S-77101 Series VDD Sequence controller ON IN ENBL_A OFF ENBL_B EN DC-DC LDO IN ENBL_C CDLY VSS Remark OUT OUT 2.5 V DC-DC LDO IN OUT EN 1.8 V 1.5 V EN DC-DC LDO I/O(1) I/O(2) LOGIC System The ENBL_x pin is CMOS output. Figure 8 Peripheral _______ Circuit Connection Example _______ (S-77101A: Reverse Type, with OFF pin, S-77101B: Forward Type, with OFF pin) Caution 1. 2. 10 The input should be performed after the power supply voltage applied to the S-77101 Series becomes stable condition. The above connection diagram does not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Off period On-sequence period Power-good period Off-sequence period Off period ON OFF CDLY n times*1 n times*1 ENBL_A ENBL_B ENBL_C 2.5 V : I/O(1) 1.8 V : I/O(2) 1.5 V : LOGIC tDLY *1. tDLY tDLY tDLY tDLY tDLY Selectable as the option: 2 times / 4 times / 8 times / 16 times _______ Figure 9 Off period Timing Chart (S-77101A: Reverse Type, with OFF pin) On-sequence period Power-good period Off-sequence period Off period ON OFF CDLY n times*1 n times*1 ENBL_A ENBL_B ENBL_C 2.5 V : I/O(1) 1.8 V : I/O(2) 1.5 V : LOGIC tDLY *1. tDLY tDLY tDLY tDLY tDLY Selectable as the option: 2 times / 4 times / 8 times / 16 times _______ Figure 10 Timing Chart (S-77101B: Forward Type, with OFF pin) 11 POWER SEQUENCER S-77100/77101 Series 2. Rev.1.0_01 Cascade connection 2. 1 S-77100B (Forward type) The enable output can be increased by connecting S-77100B in cascade. The peripheral circuit connection example how two S-77100B devices are connected in cascade is shown in Figure 11. Connect the ENBL_D pin of S-77100B(1) and the ON pin of S-77100B(2). Figure 12 shows the timing chart. 5 V AUX DC-DC LDO IN OUT 3.3 V 0.1 F 3.3 V S-77100B(1) VDD IN Sequence controller ENBL_A ENBL_B ON EN DC-DC LDO IN ENBL_C ENBL_D CDLY OUT OUT EN DC-DC LDO 2.5 V DC-DC LDO 1.8 V IN OUT I/O LOGIC EN DC-DC 1.5 V LDO 1.1 V IN OUT EN MEMORY CORE SoC1 VSS System 3.3 V 0.1 F S-77100B(2) VDD IN ENBL_A ENBL_B ON EN DC-DC LDO IN ENBL_C ENBL_D CDLY OUT OUT EN DC-DC LDO 2.5 V DC-DC LDO 1.8 V IN OUT I/O LOGIC EN DC-DC 1.5 V LDO 1.1 V IN OUT EN MEMORY CORE SoC2 VSS Remark The ENBL_x pin is CMOS output. Figure 11 Caution 1. 2. 3. 12 Peripheral Circuit Connection Example (S-77100B: Forward Type) The input should be performed after the power supply voltage applied to S-77100B becomes stable condition. The above connection diagram does not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. The external capacitors (CDLY) connected to the CDLY pin of S-77100B(1) and S-77100B(2) cannot use the same capacitor. POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 (1) On-sequence period (1) Off-sequence period n times n times S-77100B(1) ON CDLY ENBL_A ENBL_B ENBL_C ENBL_D 2.5 V : I/O 1.8 V : LOGIC 1.5 V : MEMORY 1.1 V : CORE tDLY1 tDLY1 tDLY1 tDLY1 (2) On-sequence period tDLY1 tDLY1 tDLY1 tDLY1 (2) Off-sequence period S-77100B(2) ON (S-77100B(1) ENBL_D) CDLY m times ENBL_A ENBL_B ENBL_C ENBL_D m times 2.5 V : I/O 1.8 V : LOGIC 1.5 V : MEMORY 1.1 V : CORE tDLY2 tDLY2 tDLY2 tDLY2 Figure 12 tDLY2 tDLY2 tDLY2 tDLY2 Timing Chart at Cascade Connection (S-77100B: Forward Type) After the ON pin of S-77100B(1) changes from "L" to "H", the ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin of S-77100B(1) change to "H" in turn. After the ENBL_D pin of S-77100B(1) changes from "L" to "H", the ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin of S-77100B(2) change to "H" in turn. After the ON pin of S-77100B(1) changes from "H" to "L", the ENBL_A pin, the ENBL_B pin the ENBL_C pin and the ENBL_D pin of S-77100B(1) change to "L" in turn. After the ENBL_D pin of S-77100B(1) changes from "H" to "L", the ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin of S-77100B(2) change to "L" in turn. Do not change the ON pin during on-sequence period and off-sequence period in order to perform the sequence operation normally. 13 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 _______ 2. 2 S-77101A (Reverse type, with OFF pin) The enable output can be increased by connecting S-77101A in cascade. The peripheral circuit connection example how two S-77101A devices are connected in cascade is shown in Figure 13. _______ Connect the ENBL_C pin of S-77101A(1) and the ON pin of S-77101A(2), and the OFF pin of S-77101A(1) and the ENBL_A pin of S-77101A(2). Figure 14 shows the timing chart. 5 V AUX 3.3 V 0.1 F 3.3 V S-77101A(1) VDD IN ON ENBL_A OFF ENBL_B EN DC-DC LDO IN ENBL_C CDLY VSS OUT 2.5 V DC-DC LDO 1.8 V IN OUT I/O(1) I/O(2) EN OUT 1.5 V EN DC-DC LDO System 1 DC-DC LDO IN OUT LOGIC System 3.3 V 0.1 F S-77101A(2) IN ENBL_A ON ENBL_B OFF ENBL_C VSS Remark EN DC-DC LDO IN CDLY OUT OUT EN DC-DC LDO 2.5 V DC-DC LDO 1.8 V IN OUT I/O(1) I/O(2) EN 1.5 V System 2 Sequence controller VDD LOGIC The ENBL_x pin is CMOS output. _______ Figure 13 Caution 1. 2. 3. 14 Peripheral Circuit Connection Example (S-77101A: Reverse Type, with OFF pin) The input should be performed after the power supply voltage applied to S-77101A becomes stable condition. The above connection diagram does not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. The external capacitors (CDLY) connected to the CDLY pin of S-77101A(1) and S-77101A(2) cannot use the same capacitor. POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 (1) On-sequence period (1) Off-sequence period ON OFF(S-77101A(2) ENBL_A) CDLY S-77101A(1) n times n times ENBL_A ENBL_B ENBL_C 2.5 V : I/O(1) 1.8 V : I/O(2) 1.5 V : LOGIC tDLY1 tDLY1 tDLY1 (2) On-sequence period (2) Off-sequence period m times m times tDLY1 tDLY1 tDLY1 ON (S-77101A(1) ENBL_C) OFF S-77101A(2) CDLY ENBL_A ENBL_B ENBL_C 2.5 V : I/O(1) 1.8 V : I/O(2) 1.5 V : LOGIC tDLY2 tDLY2 tDLY2 tDLY2 tDLY2 tDLY2 _______ Figure 14 Timing Chart at Cascade Connection (S-77101A: Reverse Type, with OFF pin) After the ON pin of S-77101A(1) changes from "L" to "H", the ENBL_A pin, the ENBL_B pin and the ENBL_C pin of S-77101A(1) change to "H" in turn. After the ENBL_C pin of S-77101A(1) changes from "L" to "H", the ENBL_A pin, the ENBL_B pin and the ENBL_C pin of S-77101A(2) change to "H" in turn. _______ After the OFF pin of S-77101A(2) changes from "H" to "L", the ENBL_C pin, the ENBL_B pin and the ENBL_A pin of S-77101A(2) change to "L" in turn. After the ENBL_A pin of S-77101A(2) changes from "H" to "L", the ENBL_C pin, the ENBL_B pin and the ENBL_A pin of S-77101A(1) change to "L" in turn. _______ Do not change the ON pin and the OFF pin during on-sequence period and off-sequence period in order to perform the sequence operation normally. 15 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 As shown in Figure 14, after the ON pin of S-77101A(1) changes from "L" to "H", the _______ on-sequence operation is _______ performed if the OFF pin of S-77101A(2) is either "H" or "L". Similarly, after the OFF pin of S-77101A(2) changes from "H" to "L", the off-sequence operation is performed if the ON pin of S-77101A(1) is either "H" or "L". Therefore, due to connecting the control signal pin of the sequence controller, the ON pin of S-77101A(1) _______ and the OFF pin of S-77101A(2), it is possible to control S-77101A(1) and S-77101A(2) with 1 signal. Figure 15 shows the connection example. 5 V AUX 3.3 V 0.1 F 3.3 V S-77101A(1) VDD IN ON ENBL_A OFF ENBL_B EN DC-DC LDO IN ENBL_C CDLY VSS OUT 2.5 V DC-DC LDO 1.8 V IN OUT I/O(1) I/O(2) EN OUT 1.5 V EN DC-DC LDO System 1 DC-DC LDO IN OUT LOGIC System 3.3 V 0.1 F S-77101A(2) IN ON ENBL_A OFF ENBL_B ENBL_C VSS Remark EN DC-DC LDO IN CDLY OUT OUT EN DC-DC LDO 2.5 V DC-DC LDO 1.8 V IN OUT I/O(1) I/O(2) EN 1.5 V LOGIC The ENBL_x pin is CMOS output. _______ Figure 15 16 Cascade Connection Example (S-77101A: Reverse Type, with OFF pin) System 2 Sequence controller VDD POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 3. Special Operation 3. 1 S-77100 Series special operation The Operation when the sequence operation is not completed normally, the power supply voltage drops significantly or connecting the VDD pin and the ON pin is a special operation. 3. 1. 1 Special operations during on-sequence period and off-sequence period Do not change the ON pin during on-sequence period and off-sequence period in order to perform the sequence operation normally. (1) When ON pin changes from "H" to "L" during on-sequence period Since the ENBL_x pins all change to "L", the off-sequence operation timing is not guaranteed. In addition, CDLY charge operation is stopped, and the automatic discharge operation is started. The operation example is shown in Figure 16. Original on-sequence period ON CDLY ENBL_A ENBL_B ENBL_C ENBL_D Figure 16 (2) When ON pin changes from "L" to "H" during off-sequence period Since the ENBL_x pins all change to "L", the off-sequence operation timing is not guaranteed. In addition, CDLY charge operation is stopped and the automatic discharge operation is started. In order to perform the on-sequence operation again, change the ON pin to "H" after setting the pin "L" once. The operation example is shown in Figure 17. Original off-sequence period On-sequence period ON CDLY ENBL_A ENBL_B ENBL_C ENBL_D Figure 17 Remark Refer to "3. Automatic discharge time (tDCHG) approximate calculation formula" in " Relation between Delay Time and External Capacitor" for the automatic discharge operation. 17 POWER SEQUENCER S-77100/77101 Series 3. 1. 2 Rev.1.0_01 Operation when low voltage is detected (1) When low voltage is detected during power-good period Since the ENBL_x pins all change to "L" when the power supply voltage (VDD) is equal to or lower than the low voltage detection voltage (VUVLO), the off-sequence operation timing is not guaranteed. Thereafter, if the ON pin is "H" when VDD exceeds VUVLO, the on-sequence operation is performed automatically. If the ON pin is "L" when VDD exceeds VUVLO, the on-sequence operation is not performed. In order to perform the on-sequence operation, set the ON pin to "H" again. The operation example is shown in Figure 18. VDD VUVLO VSS Power-good period On-sequence period Power-good period On-sequence period ON CDLY ENBL_A ENBL_B ENBL_C ENBL_D Figure 18 (2) When low voltage is detected during on-sequence period and off-sequence period Since the ENBL_x pins all change to "L" when VDD is equal to or lower than VUVLO during on-sequence period or off-sequence period, the off-sequence operation timing is not guaranteed. In addition, CDLY charge operation is stopped and the automatic discharge operation is started. The operation example is shown in Figure 19. VDD VDD VUVLO VSS VUVLO VSS Original off-sequence period Original on-sequence period ON ON CDLY CDLY ENBL_A ENBL_A ENBL_B ENBL_B ENBL_C ENBL_C ENBL_D ENBL_D Figure 19 Remark Refer to "3. Automatic discharge time (tDCHG) approximate calculation formula" in " Relation between Delay Time and External Capacitor" for the automatic discharge operation. 18 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 3. 1. 3 Operation when connecting VDD pin and ON pin The on-sequence operation is performed automatically when connecting the VDD pin and the ON pin and the power supply is raised. However, since the ENBL_x pins all change to "L" if VDD is equal to or lower than VUVLO when the power supply is fallen, the off-sequence operation timing is not guaranteed. The operation example is shown in Figure 20. VUVLO VDD, ON VSS CDLY ENBL_A ENBL_B ENBL_C ENBL_D Figure 20 19 POWER SEQUENCER S-77100/77101 Series 3. 2 Rev.1.0_01 S-77101 Series special operation The Operation when the sequence operation is not completed normally, the power supply voltage drops _______ significantly or connecting the VDD pin, the ON pin and the OFF pin is a special operation. 3. 2. 1 Special operations during on-sequence period and off-sequence period _______ Do not change the ON pin and the OFF pin during on-sequence period and off-sequence period in order to perform the sequence operation normally. _______ (1) When ON pin or OFF pin changes from "H" to "L" during on-sequence period Since the ENBL_x pins all change to "L" when the ON pin changes from "H" to "L" during on-sequence period, the off-sequence operation timing is not guaranteed. _______ In addition, CDLY charge operation is stopped and the automatic discharge operation is started. When the OFF pin changes from "H" to "L" during on-sequence period, the off-sequence operation is performed after the on-sequence operation is completed. The operation example is shown in Figure 21. Original on-sequence period On-sequence period Off-sequence period ON OFF CDLY ENBL_A ENBL_B ENBL_C Figure 21 _______ (2) When OFF pin or ON pin changes from "L" to "H" during off-sequence period _______ Since the ENBL_x pins all change to "L" when the OFF pin changes from "L" to "H" during off-sequence period, the off-sequence operation timing is not guaranteed. In addition, CDLY charge operation is stopped and the automatic discharge operation is started. When the ON pin changes from "L" to "H" during off-sequence period, the on-sequence operation is performed after the off-sequence operation is completed. The operation example is shown in Figure 22. Original off-sequence period On-sequence period Off-sequence period On-sequence period ON OFF CDLY ENBL_A ENBL_B ENBL_C Figure 22 Remark Refer to "3. Automatic discharge time (tDCHG) approximate calculation formula" in " Relation between Delay Time and External Capacitor" for the automatic discharge operation. 20 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 3. 2. 2 Operation when low voltage is detected (1) When low voltage is detected during power-good period Since the ENBL_x pins all change to "L" when the power supply voltage (VDD) is equal to or lower than the low voltage detection voltage (VUVLO), the off-sequence operation timing is not guaranteed. Thereafter, if the ON pin is "H" when VDD exceeds VUVLO, the on-sequence operation is performed automatically. If the ON pin is "L" when VDD exceeds VUVLO, the on-sequence operation is not performed. In order to perform the on-sequence operation, set the ON pin to "H" again. The operation example is shown in Figure 23. VDD VUVLO VSS Power-good period On-sequence period Power-good period On-sequence period ON OFF CDLY ENBL_A ENBL_B ENBL_C Figure 23 (2) When low voltage is detected during on-sequence period and off-sequence period Since the ENBL_x pins all change to "L" when VDD is equal to or lower than VUVLO during on-sequence period or off-sequence period, the off-sequence operation timing is not guaranteed. In addition, CDLY charge operation is stopped and the automatic discharge operation is started. The operation example is shown in Figure 24. VDD VUVLO VSS VDD VUVLO VSS Original off-sequence period Original on-sequence period ON ON OFF OFF CDLY CDLY ENBL_A ENBL_A ENBL_B ENBL_B ENBL_C ENBL_C Figure 24 Remark Refer to "3. Automatic discharge time (tDCHG) approximate calculation formula" in " Relation between Delay Time and External Capacitor" for the automatic discharge operation. 21 POWER SEQUENCER S-77100/77101 Series 3. 2. 3 Rev.1.0_01 _______ Operation when connecting VDD pin, ON pin and OFF pin _______ The on-sequence operation is performed automatically when connecting the VDD pin, the ON pin and the OFF pin and the power supply is raised. However, since the ENBL_x pins all change to "L" if VDD is equal to or lower than VUVLO when the power supply is fallen, the off-sequence operation timing is not guaranteed. The operation example is shown in Figure 25. VUVLO VDD, ON, OFF VSS CDLY ENBL_A ENBL_B ENBL_C Figure 25 22 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 _________ Input of ON Pin and OFF Pin 1. Input level (Selectable as the option) _______ The input level of the ON pin in the S-77100 Series, the ON pin and the OFF pin in the S-77101 Series can be selected from the following 2 options. 1. 1 Schmitt trigger input Schmitt trigger input has the power supply voltage dependency in the input voltage level. Refer to " Electrical Characteristics" for the input voltage. 1. 2 Comparator input The input threshold voltage of the comparator input has almost no power supply voltage dependency. For this reason, the sequence operation control by I/O interface of the low voltage microcomputer is also available. Refer to " Electrical Characteristics" for the input threshold voltage of the comparator input. 2. Pulse width _______ In order to surely input the signal to the S-77100/77101 Series, the pulse width to the ON pin and the OFF pin should be 5 μs or longer. 5 s or longer ON 5 s or longer OFF Figure 26 23 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Relation between Delay Time and External Capacitor The S-77100/77101 Series sets the delay time (tDLY) with an external capacitor (CDLY). tDLY is generated by performing CDLY charge-discharge operation. ON ENBL_A ENBL_B ENBL_C ENBL_D CDLY Power-good period Off period tDLY VSS tDLY tDLY_OFFSET Figure 27 1. tDLY approximate calculation formula tDLY is calculated by using the following approximate calculation formula. When CDLY ≤ 1 nF tDLY [ms] = (1.206 × CDLY [nF] + 0.023) × the number of times of charge and discharge When CDLY > 1 nF tDLY [ms] = (1.155 × CDLY [nF] − 0.023) × the number of times of charge and discharge 2. Offset delay time (tDLY_OFFSET) approximate calculation formula As shown in Figure 27, the CDLY pin during off period or power-good period is discharged to the VSS level. For this reason, there is an offset delay time (tDLY_OFFSET) immediately after the transition from off period to on-sequence period or from power-good period to off-sequence period. tDLY_OFFSET varies depending on the capacitance of CDLY. tDLY_OFFSET is calculated by using the following approximate calculation formula. When CDLY ≤ 1 nF tDLY_OFFSET [ms] = 0.241 × CDLY [nF] − 0.024 When CDLY > 1 nF tDLY_OFFSET [ms] = 0.299 × CDLY [nF] − 0.150 24 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 3. Automatic discharge time (tDCHG) approximate calculation formula Automatic discharge operation is the operation that electrical charge remained in CDLY is discharged. After the charge-discharge operation is completed, the automatic discharge operation is performed by the constant current circuit. Special operation ON On-sequence period On-sequence period Idle period CDLY VSS tDCHG Figure 28 The automatic discharge operation of the S-77100/77101 Series is performed in the following cases. • When the ON pin changes during on-sequence period. (Refer to Figure 28.) • When on-sequence period is completed. • When the ON pin changes during off-sequence period. (The S-77100 Series only) _______ • When the OFF pin changes during off-sequence period. (The S-77101 Series only) • When off-sequence period is completed. • When VDD is equal to or lower than VUVLO during on-sequence period or off-sequence period. tDCHG varies depending on the capacitance of CDLY and is calculated by using the following approximate calculation formula. tDCHG [ms] = 0.219 × CDLY [nF] The period from when the S-77100/77101 Series starts the automatic discharge operation to when it starts the next on-sequence operation or the off-sequence operation is called "idle period". The idle period should be equal to or longer than tDCHG. The idle period is necessary in order to discharge the electrical charge in CDLY completely and start the next on-sequence operation or off-sequence operation normally. In addition, by setting power-good period and off period equal to or longer than t DCHG during the sequence operation, the next off-sequence period and the on-sequence period will be the intended length. Caution 1. 2. Remark The capacitor of 100 pF to 47 nF can be used as CDLY. CDLY should be placed as close to the S-77100/77101 Series as possible since the CDLY pin internal impedance is high and the pin is easily affected by external noise etc. tDLY, tDLY_OFFSET and tDCHG may not match the calculation formula due to parasitic capacitance of the CDLY pin or internal delay in the IC. Perform thorough evaluation to determine the capacitance of CDLY. All of the above are approximate calculation formulas at Ta = +25°C. 25 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Power-on When the power supply is raised, the S-77100/77101 Series performs initialization due to the power-on reset circuit. If initialization is not performed normally, a malfunction may occur. In order to operate the power-on reset circuit normally, raise the power supply with the following method. 1. Power supply raising method As shown in Figure 29, start to raise the power supply from 0.2 V or lower. Moreover, the time the voltage reaches to the operation power supply voltage min. should be within 10 ms. Within 10 ms 2.2 V (Operation power supply voltage min.) 0.2 V or lower 0 V *1 tINIT *2 *1. *2. 0 V indicates that there is no potential difference between the VDD pin and the VSS pin of the S-77100/77101 Series. Initialization time (tINIT) indicates the time that the S-77100/77101 Series performs the initialization internally. During this duration, the S-77100/77101 Series does not accept the input. Refer to "2. Initialization time" for the details. Figure 29 If initialization is completed normally due to the power-on reset circuit, the S-77100/77101 Series becomes off period when the ON pin is "L", and on-sequence period when the ON pin is "H". When the operation conditions of the power-on reset circuit are not satisfied, a malfunction may occur since the S-77100/77101 Series cannot perform initialization. When the operation is unstable, raise the power supply voltage again so as to satisfy the condition of Figure 29 after lowering the power supply voltage to the VSS level. 26 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Initialization time When the power supply is raised, the S-77100/77101 Series performs initialization. During initialization period, the _______ S-77100/77101 Series does not accept the inputs to the ON pin and the OFF pin. The relation between the initialization time and the power supply rising (0 V → 2.2 V) time (tRISE) is shown in Figure 30. 100 m Initialization time (tINIT) [s] 2. 10 m 1.0 m 100 10 1.0 1.0 10 100 1.0 m 10 m 100 m Power supply rising (0 V 2.2 V) time (tRISE) [s] Figure 30 27 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 UVLO (under voltage lock out) Operation The power supply voltage range and the output pin status are shown in Figure 31. VDD 5.5 V Operation guaranteed voltage 2.2 V VUVLO (2.0 V typ.) 1.3 V typ. Output pin fixed UVLO detection Output pin unstable Figure 31 In the S-77100/77101 Series, the output pin status is not guaranteed when the power supply voltage (VDD) is equal to or lower than 1.3 V typ. The output pin status is fixed when VDD rises and exceeds 1.3 V typ. The sequence operation is invalid when VDD is equal to or lower than VUVLO. VDD is operation voltage when it exceeds VUVLO, however, the operation guaranteed voltage as the power sequencer is 2.2 V to 5.5 V. 28 Rev.1.0_01 POWER SEQUENCER S-77100/77101 Series Precautions • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • SII Semiconductor Corporation claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 29 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 Characteristics (Typical Data) 1. Current consumption 1, current consumption 2, current consumption 3 1. 1 Current consumption vs. Power supply voltage 5.0 IDD3 4.0 IDD1, IDD2 3.0 2.0 1.0 0.0 0 1 2 3 4 5 Current consumption vs. Temperature S-77100 Series ON pin = VSS or VDD, ENBL_x pin = Open Schmitt trigger input, VDD = 3.3 V 6.0 IDD1, IDD2, IDD3 [A] IDD1, IDD2, IDD3 [A] S-77100 Series ON pin = VSS or VDD, ENBL_x pin = Open Schmitt trigger input, Ta = +25°C 6.0 1. 2 5.0 IDD3 4.0 IDD1, IDD2 3.0 2.0 1.0 0.0 40 25 6 0 VDD [V] 2. 25 Ta [C] 50 75 85 Low voltage detection voltage 2. 1 Low voltage detection voltage vs. Temperature VUVLO [V] 3.0 2.5 2.0 1.5 1.0 3. 40 25 0 25 Ta [C] 50 75 85 High level input leakage current, low level input leakage current 3. 1 Input leakage current vs. Power supply voltage ___________ Input leakage current vs. Temperature ___________ ON pin, OFF pin*1, VIN = VDD (IIZH), VIN = VSS (IIZL) VDD = 3.3 V 0.3 0.2 0.2 0.1 IIZH, IIZL 0 0.1 0.2 0.1 IIZH, IIZL 0 0.1 0.2 0.3 0.0 0 1 2 3 VDD [V] *1. The S-77101 Series only 30 3. 2 IIZH, IIZL [A] IIZH, IIZL [A] ON pin, OFF pin*1, VIN = VDD (IIZH), VIN = VSS (IIZL) Ta = +25°C 0.3 4 5 6 40 25 0 25 Ta [C] 50 75 85 POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 4. Input voltage (When Schmitt trigger input is selected) 4. 1 Input voltage vs. Power supply voltage 4. 2 Input voltage vs. Temperature ___________ 0.8 VIH/VDD 0.6 0.4 ON pin, OFF pin*1 VDD = 3.3 V 1.0 VIH/VDD, VIL/VDD 1.0 VIH/VDD, VIL/VDD ___________ ON pin, OFF pin*1 Ta = +25°C VIL/VDD 0.2 0 0 1 2 3 4 5 0.8 VIH/VDD 0.6 0.4 VIL/VDD 0.2 0 6 40 25 0 VDD [V] 5. 50 75 85 Input threshold voltage (When comparator input is selected) 5. 1 Input threshold voltage vs. Power supply voltage ___________ Input threshold voltage vs. Temperature ___________ ON pin, OFF pin*1 VDD = 3.3 V 3.0 2.5 2.5 2.0 2.0 VIT_ON [V] VIT_ON [V] 5. 2 pin*1 ON pin, OFF Ta = +25°C 3.0 1.5 1.0 1.5 1.0 0.5 0.5 0 0 0 1 2 3 4 5 40 25 6 0 VDD [V] 6. 25 Ta [C] 25 Ta [C] 50 75 85 High level output leakage current, low level output leakage current 6. 1 Output leakage current vs. Power supply voltage 0.2 0.1 6. 2 IOZH, IOZL 0 0.1 0.2 Output leakage current vs. Temperature ENBL_A pin, ENBL_B pin, ENBL_C pin, ENBL_D pin*2 VOUT = VDD (IOZH), VOUT = VSS (IOZL), VDD = 3.3 V 0.3 IOZH, IOZL [A] IOZH, IOZL [A] ENBL_A pin, ENBL_B pin, ENBL_C pin, ENBL_D pin*2 VOUT = VDD (IOZH), VOUT = VSS (IOZL), Ta = +25°C 0.3 0.2 0.1 IOZH, IOZL 0 0.1 0.2 0.3 0.3 0 1 2 3 VDD [V] 4 5 6 40 25 0 25 Ta [C] 50 75 85 *1. The S-77101 Series only *2. The S-77100 Series only 31 POWER SEQUENCER S-77100/77101 Series 7. Rev.1.0_01 Low level output voltage 7. 1 Low level output voltage vs. Low level output current 7. 2 ENBL_A pin, ENBL_B pin, ENBL_C pin, ENBL_D pin*1 Ta = +25°C 0.6 ENBL_A pin, ENBL_B pin, ENBL_C pin, ENBL_D pin*1 IOL = 2.0 mA 0.6 0.5 VDD = 2.2 V 0.4 VOL [V] VOL [V] 0.5 VDD = 3.3 V 0.3 VDD = 5.5 V 0.2 0.3 VDD = 3.3 V 0.2 VDD = 5.5 V 0 0 0 1 2 3 IOL [mA] 40 25 5 4 0 25 Ta [C] 50 75 85 High level output voltage 8. 1 High level output voltage vs. High level output current 8. 2 ENBL_A pin, ENBL_B pin, ENBL_C pin, ENBL_D pin*1 CMOS output, Ta = +25°C 6.0 3.0 2.0 1.0 0 5.0 VDD = 5.5 V 4.0 High level output voltage vs. Temperature ENBL_A pin, ENBL_B pin, ENBL_C pin, ENBL_D pin*1 CMOS output, IOH = −0.4 mA 6.0 VOH [V] VOH [V] 5.0 9. VDD = 2.2 V 0.4 0.1 0.1 8. Low level output voltage vs. Temperature VDD = 3.3 V VDD = 2.2 V VDD = 5.5 V 4.0 VDD = 3.3 V 3.0 2.0 1.0 VDD = 2.2 V 0 1.5 1.25 1.0 0.75 0.5 0.25 IOH [mA] 40 25 0 0 25 Ta [C] 50 75 85 Delay time 9. 1 Delay time vs. Power supply voltage 9. 2 Delay time vs. CDLY 55 250 50 200 tDLY [ms] tDLY [ms] The number of times of CDLY charge and discharge = 4 times, The number of times of CDLY charge and discharge = 4 times, VDD = 3.3 V, Ta = +25°C CDLY = 10 nF, Ta = +25°C 60 300 45 40 35 100 50 30 0 0 1 2 3 VDD [V] *1. The S-77100 Series only 32 150 4 5 6 0 10 20 30 40 CDLY [nF] 50 60 +0.3 3.00 -0.2 8 5 1 4 0.17±0.05 0.2±0.1 0.65 No. FT008-A-P-SD-1.1 TITLE TSSOP8-E-PKG Dimensions FT008-A-P-SD-1.1 No. SCALE UNIT mm SII Semiconductor Corporation 4.0±0.1 2.0±0.05 ø1.55±0.05 0.3±0.05 +0.1 8.0±0.1 ø1.55 -0.05 (4.4) +0.4 6.6 -0.2 1 8 4 5 Feed direction No. FT008-E-C-SD-1.0 TITLE TSSOP8-E-Carrier Tape FT008-E-C-SD-1.0 No. SCALE UNIT mm SII Semiconductor Corporation 13.4±1.0 17.5±1.0 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.5 No. FT008-E-R-S1-1.0 TITLE TSSOP8-E-Reel FT008-E-R-S1-1.0 No. SCALE UNIT QTY. 4,000 mm SII Semiconductor Corporation 1.97±0.03 8 7 6 5 3 4 +0.05 1 0.5 2 0.08 -0.02 0.48±0.02 0.2±0.05 No. PH008-A-P-SD-2.0 TITLE SNT-8A-A-PKG Dimensions No. PH008-A-P-SD-2.0 SCALE UNIT mm SII Semiconductor Corporation +0.1 ø1.5 -0 5° 2.25±0.05 4.0±0.1 2.0±0.05 ø0.5±0.1 0.25±0.05 0.65±0.05 4.0±0.1 4 321 5 6 78 Feed direction No. PH008-A-C-SD-1.0 TITLE SNT-8A-A-Carrier Tape No. PH008-A-C-SD-1.0 SCALE UNIT mm SII Semiconductor Corporation 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. PH008-A-R-SD-1.0 TITLE SNT-8A-A-Reel No. PH008-A-R-SD-1.0 SCALE UNIT QTY. 5,000 mm SII Semiconductor Corporation 0.52 2.01 2 0.52 0.2 0.3 1. 2. 1 (0.25 mm min. / 0.30 mm typ.) (1.96 mm ~ 2.06 mm) 1. 2. 3. 4. 0.03 mm SNT 1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.). 2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm). Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package. 2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm or less from the land pattern surface. 3. Match the mask aperture size and aperture position with the land pattern. 4. Refer to "SNT Package User's Guide" for details. 1. 2. (0.25 mm min. / 0.30 mm typ.) (1.96 mm ~ 2.06 mm) TITLE No. PH008-A-L-SD-4.1 SNT-8A-A -Land Recommendation PH008-A-L-SD-4.1 No. SCALE UNIT mm SII Semiconductor Corporation Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. SII Semiconductor Corporation is not responsible for damages caused by the reasons other than the products or infringement of third-party intellectual property rights and any other rights due to the use of the information described herein. 3. SII Semiconductor Corporation is not responsible for damages caused by the incorrect information described herein. 4. Take care to use the products described herein within their specified ranges. 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