HD74HC95 8-bit Shift Register REJ03D0558-0200 (Previous ADE-205-431) Rev.2.00 Oct 06, 2005 Description This 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register has three mode operation: • Parallel (broadside) load • Shift right (the direction QA toward QD) • Shift left (the direction QD toward QA) Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock-1 when the mode control is low; shift left is accomplished on the high-to-low transition of clock-2 when the mode control is high by connecting the output of each flip-flop (QD to input C, etc.) and serial data is entered at input D. The clock input may be applied commonly to clock-1 and clock-2 if both modes can be clocked from the same source. Changes at the mode control input should normally be made while both clock inputs are low: however, conditions described in the last three lines of the function table will also ensure that register contents are protected. Features • • • • • • High Speed Operation: tpd (Clock to Q) = 17 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type HD74HC95P DILP-14 pin HD74HC95RPEL SOP-14 pin (JEDEC) Rev.2.00, Oct 06, 2005 page 1 of 6 Package Code (Previous Code) PRDP0014AB-B (DP-14AV) PRSP0014DE-A (FP-14DNV) Package Abbreviation Taping Abbreviation (Quantity) P — RP EL (2,500 pcs/reel) HD74HC95 Function Table Inputs Mode Control H H Clocks 2 (L) 1 (R) H H L L L L X X Outputs Serial A Parallel B C D QA QB QC QD X X X X X a X b X c X d QA0 a QB0 b QC0 c QD0 d X H X X QB+ X QC+ X QD+ X d X QBn QA0 QCn QB0 QDn QC0 d QD0 H L X X X X X X X X H L QAn QAn QBn QBn QCn QCn L L L L X X X X X X X X X X QA0 QA0 QB0 QB0 QC0 QC0 QD0 QD0 L H H L X X X X X X X X X X QA0 QA0 QB0 QB0 QC0 QC0 QD0 QD0 H H X X X X X QA0 QB0 QC0 QD0 Notes: 1. H : High level, L : Low level, X : Irrelevant 2. a to d : The level of steady-state input at inputs A, B, C or D respectively 3. QA0 to QD0 : The level of QA, QB, QC or QD respectively before the indicated steady-state input conditions were established. 4. QAn to QDn : The level of QA, QB, QC or QD respectively before the most-recent ( ) transition of the clock. 5. + : Shifting left requires external connection of QB to A, QC to B and QD to C. Serial data is entered at input D. Pin Arrangement Serial Input 14 Vcc 1 Serial A 2 A Input QA 13 QA B 3 B QB 12 QB Outputs Inputs C 4 C QC 11 QC D 5 D QD 10 QD 6 Mode CK1 9 7 CK2 8 Mode Control GND (Top View) Rev.2.00, Oct 06, 2005 page 2 of 6 Clock1 R-Shift Clock2 L-Shift (Load) HD74HC95 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input / Output voltage VCC Vin, Vout –0.5 to 7.0 –0.5 to VCC +0.5 V V IIK, IOK IO ±20 ±25 mA mA ICC or IGND PT ±50 500 mA mW Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Tstg –65 to +150 °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Symbol VCC Ratings 2 to 6 Unit V Input / Output voltage Operating temperature VIN, VOUT Ta 0 to VCC –40 to 85 V °C tr , tf 0 to 1000 0 to 500 ns Input rise / fall time Note: *1 0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Electrical Characteristics Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Input current Quiescent supply current Iin ICC Min Ta = 25°C Typ Max Ta = –40 to+85°C Unit Min Max 2.0 4.5 1.5 3.15 — — — — 1.5 3.15 — — 6.0 2.0 4.2 — — — — 0.5 4.2 — — 0.5 4.5 6.0 — — — — 1.35 1.8 — — 1.35 1.8 2.0 4.5 1.9 4.4 2.0 4.5 — — 1.9 4.4 — — 6.0 4.5 5.9 4.18 6.0 — — — 5.9 4.13 — — 6.0 2.0 5.68 — — 0.0 — 0.1 5.63 — — 0.1 4.5 6.0 — — 0.0 0.0 0.1 0.1 — — 0.1 0.1 4.5 6.0 — — — — 0.26 0.26 — — 0.33 0.33 6.0 6.0 — — — — ±0.1 4.0 — — ±1.0 40 Rev.2.00, Oct 06, 2005 page 3 of 6 Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA V IOH = –5.2 mA Vin = VIH or VIL IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC95 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = 25°C Item Symbol VCC (V) Maximum clock frequency fmax Propagation delay time tPLH tPHL Pulse width tw Setup time tsu Hold time th Output rise/fall time tTLH, tTHL Input capacitance Cin Ta = –40 to +85°C 2.0 Min — Typ — Max 4 Min — Max 3 4.5 6.0 — — — — 20 24 — — 16 19 2.0 4.5 — — — 17 145 29 — — 180 36 6.0 2.0 — — — — 25 170 — — 31 215 4.5 6.0 — — 17 — 34 29 — — 43 37 2.0 4.5 80 16 — 6 — — 100 20 — — 6.0 2.0 14 100 — — — — 17 125 — — 4.5 6.0 20 17 2 — — — 25 21 — — 2.0 4.5 10 10 — –1 — — 10 10 — — 6.0 2.0 10 — — — — 75 10 — — 95 4.5 6.0 — — 5 — 15 13 — — 19 16 — — 5 10 — 10 Unit Test Conditions MHz ns ns ns Clock ns ns ns pF Test Circuit VCC VCC Input Pulse generator Zout = 50 Ω Input Pulse generator Zout = 50 Ω See Function Table Output Serial Input Mode Control Clock 1 Clock 2 A B C D QA Output CL = 50 pF QB Output CL = 50 pF QC Output CL = 50 pF QD CL = 50 pF Note: C L includes the probe and jig capacitance. Rev.2.00, Oct 06, 2005 page 4 of 6 HD74HC95 Waveforms • Waveform − 1 tr tf 90 % Data tw VCC 90 % 50 % 50 % 50 % 10 % 10 % t su th t su tf Clock-1 or Clock-2 0V th tr 90 % 50 % 90 % 50 % VCC 50 % 10 % 0V tw t PHL t PLH VOH 90 % 90 % QA to QD 50 % 50 % 10 % 10 % t THL VOL t TLH Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. Enable = GND Package Dimensions JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B Previous Code DP-14AV MASS[Typ.] 0.97g D 8 E 14 1 7 b3 Z A1 A Reference Symbol bp θ c e1 7.62 D 19.2 E 6.3 A1 0.51 bp 0.40 20.32 7.4 0.48 0.56 1.30 b3 c 0.19 θ 0° e 2.29 L Max 5.06 Z ( Ni/Pd/Au plating ) Rev.2.00, Oct 06, 2005 page 5 of 6 Nom e1 A L e Dimension in Millimeters Min 0.25 0.31 2.54 2.79 15° 2.39 2.54 HD74HC95 JEITA Package Code P-SOP14-3.95x8.65-1.27 RENESAS Code PRSP0014DE-A *1 MASS[Typ.] 0.13g Previous Code FP-14DNV NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F D 14 8 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 8.65 9.05 E 3.95 A2 A1 7 1 Z e *3 bp 0.10 0.14 A x M bp L1 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 b1 c A c1 A1 θ L y Detail F θ 0° HE 5.80 1.27 e x 0.25 y 0.15 0.635 Z L L Rev.2.00, Oct 06, 2005 page 6 of 6 8° 0.40 1 0.60 1.08 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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