HD74HC194 4-bit Bidirectional Universal Shift Register REJ03D0589–0200 (Previous ADE-205-466) Rev.2.00 Jan 31, 2006 Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control inputs, and a direct overriding clear line. The register has four distinct modes of operation: parallel (broadside) load, shift right (in the direction QA toware QD); shift left; inhibit clock (do nothing). Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into their respective flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift left serial input. Clocking of the flip-flops is inhibited when both mode control inputs are low. The mode control inputs should be changed only when the clock input is high. Features • • • • • • High Speed Operation: tpd (Clock to Q) = 12 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max Ordering Information Part Name HD74HC194P Package Type DILP-16 pin Rev.2.00 Jan 31, 2006 page 1 of 8 Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation P Taping Abbreviation (Quantity) — HD74HC194 Function Table Operating Mode Clear Parallel load Shift right Shift left Hold H : L : X : : Clear L H H H H H H H H Inputs Serial Clock Shift Left Shift Right X X X X X X H X L H X L X Mode S0 S1 X X H H L H L H H L H L L L X X X X X L H X X X X X X Outputs A X a X X X X Parallel B C X X b c X X X X X X X X D X d X X X X QA L a H L QBn QBn X X X X X X X X X QA0 QA0 QA0 X X X QB L b QAn QAn QCn QCn QB0 QB0 QB0 QC L c QD L d QBn QBn QDn QDn QC0 QC0 QC0 QCn QCn H L QD0 QD0 QD0 high level (Steady state) low level (Steady state) don’t care transition from low to high level. a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively. QA0, QB0, QC0, QD0 : the level of QA, QB, QC or QD respectively, before the indicated steady-state input conditions were established. QAn, QBn, QCn, QDn : the level of QA, QB, QC or QD respectively before the most recent Pin Arrangement Clear 1 Shift Right Serial-Input Parallel Inputs 16 VCC 2 R A 3 A CLR QA 15 QA QB 14 QB B 4 B QC 13 QC C 5 C QD 12 QD D 6 D CK 11 Clock S1 10 S1 Shift Left Serial-Input 7 L S0 GND 8 Mode Control 9 S0 (Top view) Rev.2.00 Jan 31, 2006 page 2 of 8 Parallel Outputs transition of the clock. HD74HC194 Timing Diagram Clock Mode Control Inputs S0 S1 Clear Serial Data Inputs R L A Parallel Data Inputs H B L C H D L QA QB Outputs QC QD Shift Right Clear Shift Left Inhibit Load Clear Logic Diagram Serial Shift Left D C B Serial Shift Right A S0 S1 D C C Q CL CL D C C Q CL CL D C C Q CL CL D C C Q CL CL Clock Clear QD QC QB QA Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 Unit V V mA mA mA PT Tstg 500 –65 to +150 mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00 Jan 31, 2006 page 3 of 8 HD74HC194 Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V °C ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Output voltage Symbol VCC (V) Ta = 25°C Min Typ Max 1.5 — — 3.15 — — 4.2 — — Ta = –40 to+85°C Unit Min Max 1.5 — V 3.15 — 4.2 — VIH 2.0 4.5 6.0 VIL 2.0 4.5 6.0 — — — — — — 0.5 1.35 1.8 — — — 0.5 1.35 1.8 V VOH 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 1.9 4.4 5.9 4.18 5.68 — — — — — — — 2.0 4.5 6.0 — — 0.0 0.0 0.0 — — — — — — — — — 0.1 0.1 0.1 0.26 0.26 ±0.1 4.0 1.9 4.4 5.9 4.13 5.63 — — — — — — — — — — — — 0.1 0.1 0.1 0.33 0.33 ±1.0 40 V VOL Input current Iin Quiescent supply current ICC Rev.2.00 Jan 31, 2006 page 4 of 8 V Test Conditions Vin = VIH or VIL IOH = –20 µA Vin = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC194 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Maximum clock frequency fmax Propagation delay time tPHL tPLH tPHL Pulse width tw Setup time tsu Hold time th Removal time trem Output rise/fall time tTLH tTHL Input capacitance Cin Ta = 25°C Ta = –40 to +85°C Unit Test Conditions Typ Max Min Max — 6 — 5 ns — 30 — 24 — 35 — 28 — 140 — 175 ns Clock to Q 12 28 — 35 — 24 — 30 — 140 — 175 ns 12 28 — 35 — 24 — 30 — 150 — 190 ns Clear to Q 13 30 — 38 — 26 — 33 — — 100 — ns Clock or Clear 6 — 20 — — — 17 — — — 125 — ns A, B, C or D to Clock 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 Min — — — — — — — — — — — — 80 16 14 100 4.5 6.0 2.0 4.5 6.0 20 17 150 30 25 7 — — 17 — — — — — — 25 21 187 37 31 — — — — — 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 0 0 0 25 5 4 — — — — –4 — — 1 — — 5 — — — — — — — 75 15 13 0 0 0 31 6 5 — — — — — — — — — 95 19 16 — — 5 10 — 10 Rev.2.00 Jan 31, 2006 page 5 of 8 ns Mode controls to Clock ns Any input ns Clear inactive to Clock ns pF HD74HC194 Test Circuit Input Pulse Generator Zout = 50 Ω VCC See Function Table VCC Clear Clock S0 S1 R L A B C D Output QA Output QB CL = 50 pF Output CL = 50 pF QC Output CL = 50 pF QD CL = 50 pF Note : 1. CL includes probe and jig capacitance. Rev.2.00 Jan 31, 2006 page 6 of 8 HD74HC194 Waveforms • Waveform – 1 tn tn+1 tn tn+1 tf tr VCC 50% 50% Clock tsu tsu th 0V th VCC L or R 50% 50% 50% 50% 0V tPLH tPHL VOH 50% Q 50% VOL Notes : 1. For right shift, measure QA at tn+1, QB at tn+2, QC at tn+3, QD at tn+4, respectively. For left shift, measure QA at tn+4, QB at tn+3, QC at tn+2, QD at tn+1, respectively. 2. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns • Waveform – 2 tr tf VCC 90 % Clock 50 % 50 % 10 % tw 10 % 0V tf VOH 90 % 50 % Clear 10 % VOL t PHL VOH Q 50 % 10 % t THL Note : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns Rev.2.00 Jan 31, 2006 page 7 of 8 VOL HD74HC194 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e e bp Dimension in Millimeters Min D 19.2 E 6.3 A θ c e1 A1 0.51 b p 0.40 b 3 20.32 7.4 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 L Max 5.06 Z ( Ni/Pd/Au plating ) Rev.2.00 Jan 31, 2006 page 8 of 8 Nom 7.62 1 0.25 0.31 2.54 2.79 15° 1.12 2.54 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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