HD74AC194 4-bit Bidirectional Unviersal Shift Register REJ03D0259–0200Z (Previous ADE-205-379 (Z)) Rev.2.00 Jul.16.2004 Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control inputs, and a direct overriding clear line. The register has four destinct modes of operation: parallel (broadside) load, shift right (in the direction Q0 toward Q3); shift left; inhibit clock (do nothing). Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into their respective flip-flops and appear at the output after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial date for this mode is entered at the shift right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shifts left serial input. Clocking of the flip-flops is inhibited when both mode control inputs are low. The mode control inputs should be changed only when the clock input is high. Features • Asynchronous Master Reset • Hole (Do Nothing) Mode • Outputs Source/Sink 24 mA • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC194FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) HD74AC194RPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Rev.2.00, Jul.16.2004, page 1 of 7 HD74AC194 Pin Arrangement MR 1 16 VCC DSR 2 15 Q0 P0 3 14 Q1 P1 4 13 Q2 P2 5 12 Q3 P3 6 11 CP DSL 7 10 S1 GND 8 9 S0 (Top view) Logic Symbol DSR P0 P1 P2 P3 DSL S0 S1 CP MR Rev.2.00, Jul.16.2004, page 2 of 7 Q0 Q1 Q2 Q3 HD74AC194 Pin Names S0, S1 P0 to P3 DSR DSL CP MR Q0 to Q3 Mode Control Inputs Parallel Data Inputs Serial Data Input (Shift Right) Serial Data Input (Shift Left) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Parallel Outputs Logic Diagram DSL P3 P2 P1 P0 DSR S0 S1 D D D D C C C C C Q CL CL C Q CL CL C Q CL CL C Q CL CL CP MR Q3 Q2 Q1 Q0 Mode Select Table MR Operating Mode Inputs S0 DSR S1 Output DSL Pn Q0 Q1 Q2 Q3 Reset Hold L H X L X L X X X X X X L q0 L q1 L q2 L q3 Shift Left H H H H L L X X L H X X q1 q1 q2 q2 q3 q3 L H Shift Right H H L L H H L H X X X X L H q0 q0 q1 q1 q2 q2 Parallel Load H H H X X pn p0 p1 p2 p3 H : HIGH Voltage Level L : LOW Voltage Level pn (qn) : Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition X : Immaterial Rev.2.00, Jul.16.2004, page 3 of 7 HD74AC194 Timing Diagram CP Mode S0 Control Inputs S1 MR Parallel DSH Data Inputs Parallel DSL P0 H P1 L P2 H Data Inputs L P3 Q0 Outputs Q1 Q2 Q3 Shift Right Clear Shift Left Inhibit Load Clear Absolute Maximum Ratings Supply voltage Item Symbol VCC Ratings –0.5 to 7 V Unit DC input diode current IIK –20 20 mA mA DC input voltage DC output diode current VI IOK –0.5 to Vcc+0.5 –50 V mA DC output voltage VO 50 –0.5 to Vcc+0.5 mA V DC output source or sink current DC VCC or ground current per output pin IO ICC, IGND ±50 ±50 mA mA Storage temperature Tstg –65 to +150 °C Condition VI = –0.5V VI = Vcc+0.5V VO = –0.5V VO = Vcc+0.5V Recommended Operating Conditions Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Rev.2.00, Jul.16.2004, page 4 of 7 Symbol VCC 2 to 6 Ratings V Unit VI, VO Ta 0 to VCC –40 to +85 V °C tr, tf 8 ns/V Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V HD74AC194 DC Characteristics Item Input Voltage Symbol VIH VIL Output voltage VOH VOL Ta = 25°°C Vcc (V) 3.0 min. 2.1 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.1 — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 Unit V Condition VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA Input leakage current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOL = 24 mA Dynamic output current* IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 — — 8.0 — 80 µA VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics Item Symbol VCC (V)*1 Ta = +25°C CL = 50 pF Min Typ Max Ta = –40°C to +85°C CL = 50 pF Min Max Maximum clock frequency fmax 3.3 5.0 75 100 — — Propagation delay CP to Qn tPLH 3.3 5.0 1.0 1.0 — — 13.0 10.0 1.0 1.0 15.0 11.5 ns Propagation delay CP to Qn tPHL 3.3 5.0 1.0 1.0 — — 13.0 10.0 1.0 1.0 15.0 11.5 ns Propagation delay MR to Qn tPHL 3.3 5.0 1.0 1.0 — — 10.5 8.0 1.0 1.0 12.5 9.0 ns Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 5 of 7 65 85 Unit MHz HD74AC194 AC Operating Requirements Ta = +25°C CL = 50 pF Item Setup time, HIGH or LOW Symbol VCC (V)*1 tsu 3.3 — Pn or DSR or DSL to CP Hold time, HIGH or LOW th 5.0 3.3 Pn or DSR or DSL to CP Setup time, HIGH or LOW Typ Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 5.5 7.0 ns Unit — — 4.0 2.0 5.0 3.0 ns — — 1.5 6.0 2.0 7.5 ns tsu 5.0 3.3 Sn to CP Hold time, HIGH or LOW th 5.0 3.3 — — 4.5 0.0 5.5 0.0 ns Sn to CP Recovery time trec 5.0 3.3 — — 0.0 0.5 0.0 0.5 ns MR to CP Pulse width tw 5.0 3.3 — — 0.5 5.5 0.5 7.0 ns 5.0 — 4.5 5.0 Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 6 of 7 Symbol CIN CPD Typ 4.5 100 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC194 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ + 0.67 0.60 – 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 7 of 7 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g Sales Strategic Planning Div. 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