APL3203D Li+ Charger Protection IC Features General Description • Input Over-Voltage Protection The APL3203D provides complete Li+ charger protec- • Programmable Input Over-Current Protection • Battery Over-Voltage Protection tions against over-voltage, over-current, and battery overvoltage. The IC is designed to monitor input voltage, in- • • Over-Temperature Protection High Immunity of False Triggering • High Accuracy Protection Thresholds • Fault Status Indication • Enable Input • Available in TDFN2x2-8 Package • Lead Free and Green Devices Available put current, and battery voltage. When any of the monitored parameters are over the threshold, the IC removes the power from the charging system by turning off an internal switch. All protections also have deglitch time against false triggering due to voltage spikes or current transients. The APL3203D also provides over-temperature protection, a FAULT output pin to indicate the fault conditions, and the EN pin to allow the system to disable the IC. (RoHS Compliant) Simplified Application Circuit Applications • Smart Phones and PDAs • Digital Still Cameras • Portable Devices 5V Adapter or USB Charger Input IN OUT APL3203D EN Pin Configuration FAULT Charger Output and System ILIM IN 1 GND 2 NC 3 8 OUT EP FAULT 4 BAT GND 7 ILIM Li+ Battery 6 BAT 5 EN Simplified Application TDFN2x2-8 (Top View) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 1 www.anpec.com.tw APL3203D Ordering and Marking Information Package Code QB : TDFN2x2-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL3203D Assembly Material Handling Code Temperature Range Package Code APL3203D QB: L03D X X - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Parameter Rating Unit VIN IN Input Voltage (IN pin to GND) -0.3 to 30 V VOUT, VBAT OUT, BAT Pins to GND Voltage -0.3 to 7 V ILIM, FAULT, EN, Pins to GND Voltage -0.3 to 7 V VILIM, VFAULT , VEN IOUT TJ OUT Output Current 2 Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature,10 Seconds A 150 o -65 to 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Junction to Ambient Thermal Resistance in Free Air Typical Value Unit 80 °C/W (Note 2) TDFN2x2-8 Note 2 :θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Symbol Parameter Range Unit 4.5 to 5.5 V OUT Output Current 0 to 1.5 A TJ Junction Temperature -40 to 125 °C TA Ambient Temperature -40 to 85 °C VIN IN Input Voltage IOUT Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 2 www.anpec.com.tw APL3203D Electrical Characteristics Refer to the typical application circuit. These specifications apply over VIN=5V, TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APL3203D Test Conditions Unit Min. Typ. Max. 2.5 - 2.8 V - 230 - mV EN = Low - 250 350 EN = High - 100 150 VIN rising to VOUT rising - 8 - ms POWER-ON-RESET (POR) AND SUPPLY CURRENT VPOR IN POR Threshold VIN rising IN POR Hysteresis ICC TB(IN) IN Supply Current Input Power-On Blanking Time µA INTERNAL POWER SWITCH AND OUT DISCHARGE RESISTANCE Power Switch On Resistance IOUT = 0.5A - 250 450 mΩ OUT Discharge Resistance VOUT = 3V - 500 - Ω VIN rising INPUT OVER-VOLTAGE PROTECTION (OVP) VOVP TON(OVP) Input OVP Threshold 5.67 5.85 6.00 V Input OVP Recovery Hysteresis - 200 - mV Input OVP Propagation Delay - - 1 µs Input OVP Recovery Time - 8 - ms 1000 1200 mA OVER-CURRENT PROTECTION (OCP) IOCP OCP Threshold RILIM = 25kΩ 930 OCP Threshold Accuracy IOCP = 300mA to 1500mA -10 - +10 % TB(OCP) OCP Blanking Time - 176 - µs TON(OCP) OCP Recovery Time - 64 - ms 4.4 4.435 4.465 V - 270 - mV - - 20 nA - 176 - µs BATTERY OVER-VOLTAGE PROTECTION VBOVP Battery OVP Threshold VBAT rising Battery OVP Hysteresis IBAT TB(BOVP) BAT Pin Leakage Current VBAT = 4.4V Battery OVP Blanking Time EN LOGIC LEVELS EN Input Logic High 1.4 - - V EN Input Logic Low - - 0.4 V EN Internal Pull-Low Resistor - 500 - kΩ FAULT LOGIC LEVELS AND DELAY TIME FAULT Output Low Voltage Sink 5mA current - - 0.4 V FAULT Pin Leakage Current VFAULT = 5V - - 1 µA Over-Temperature Threshold - 140 - °C Over-Temperature Hysteresis - 20 - °C OVER-TEMPERATURE PROTECTION (OTP) TOTP Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 3 www.anpec.com.tw APL3203D Typical Operating Characteristics Battery OVP Threshold vs. Junction Temperature Input OVP Threshold vs. Junction Temperature 4.485 Battery OVP Threshold, VBOVP (V) Input OVP Threshold , VOVP (V) 6.00 5.95 5.90 5.85 VIN Increasing 5.80 5.75 5.70 VIN Decreasing 5.65 5.60 5.55 -50 -25 0 25 50 75 100 4.435 VBAT Increasing 4.385 4.335 4.285 4.235 4.185 VBAT Decreasing 4.135 4.085 -50 125 -25 Junction Temperature ( oC ) 0 25 50 75 100 125 o Junction Temperature ( C) IN Supply Current vs. Junction Temperature OCP Threshold vs. Junction Temperature 150 1200 IN Supply Current, ICC (µΑ) OCP Threshold, IOCP (mA) 1150 1100 1050 1000 950 900 125 100 EN = high 75 850 50 800 -50 -25 0 25 50 75 100 -50 125 -25 Power Switch On Resistance, RDS,ON (Ω) POR Threshold, VPOR (V) 2.80 VIN Increasing 2.60 2.50 2.40 VIN Decreasing 2.30 2.20 -25 0 25 50 75 100 75 100 125 0.35 0.30 0.25 0.20 0.15 0.10 3.0 125 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Input Voltage, VIN (V) Junction Temperature (oC) Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 50 Power Switch On Resistance vs. Input Voltage POR Threshold vs. Junction Temperature -50 25 Junction Temperature (oC) Junction Temperature (oC) 2.70 0 4 www.anpec.com.tw APL3203D Typical Operating Characteristics (Cont.) Power Switch On Resistance, RDS,ON (mΩ) Power Switch On Resistance vs. Junction Temperature 400 350 300 250 200 150 -50 -25 0 25 50 75 100 125 o Junction Temperature ( C) Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 5 www.anpec.com.tw APL3203D Operating Waveforms Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. Normal Power On OVP at Power On VIN = 0 to 12V VIN = 0 to 5V VIN VIN 1 VOUT 1 VOUT 2 2 IOUT VFAULT 3 3 COUT =1µF, CIN =1µF, ROUT = 10Ω CH1: VIN, 10V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 2ms/Div COUT =1µF, CIN =1µF, ROUT = 10Ω CH1: VIN, 5V/Div, DC CH2: VOUT, 2V/Div, DC CH3: IOUT, 0.5A/Div, DC TIME: 2ms/Div Input Over-Voltage Protection COUT = 1µF, CIN=1µF, ROUT=50Ω CH1: VIN, 5V/Div, AC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 20µs/Div Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 6 www.anpec.com.tw APL3203D Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. Battery Over-Voltage Protection Battery Over-Voltage Protection VB A T VB A T 1 1 VOUT V OUT 2 2 V FAULT VFAULT 3 3 VBAT = 3.6V to 4.4V, ROUT=33.3Ω COUT =1µF, CIN =1µF CH1: VBAT, 2V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 50µs/Div VBAT = 3.6V to 4.4V to 3.6V, R OUT=33.3Ω COUT =1µF, CIN =1µF CH1: VBAT, 2V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 5ms/Div Recovery from Battery OVP Over-Current Protection VBAT IOUT 1 1 V OUT VOUT 2 2 VFAULT VFAULT 3 3 VBAT = 4.4V to 3.6V, ROUT=33.3Ω COUT =1µF, CIN =1µF CH1: VBAT, 2V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 50µs/Div Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 COUT =1µF, CIN =1µF, IOUT = 0.5A to 1.2A CH1: IOUT, 0.5A/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 50µs/Div 7 www.anpec.com.tw APL3203D Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. Over-Current Protection VIN 1 2 VOUT IOUT 3 VFAULT 4 COUT =1µF, CIN =1µF, ROUT = 2.5Ω CH1: V IN, 5V/Div, DC CH2: V OUT, 5V/Div, DC CH3: I OUT, 0.5A/Div, DC CH4: V FAULT, 5V/Div, DC TIME: 200ms/Div Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 8 www.anpec.com.tw APL3203D Pin Description PIN NO. FUNCTION NAME 1 IN 2 GND Power Supply Input. 3 NC 4 FAULT 5 EN Enable Input. Pull this pin to high to disable the device and pull this pin to low to enable device. 6 BAT Battery OVP Sense Pin. Connect to positive terminal of battery through a resistor. 7 ILIM Over-current Protection Setting Pin. Connect a resistor to GND to set the over-current threshold. 8 OUT Output Voltage Pin. The output voltage follows the input voltage when no fault is detected. - EP Ground. No Connection. Fault Indication Pin. This pin goes low when input OVP, OCP, or battery OVP is detected. Exposed Thermal Pad. Must be electrically connected to the GND pin. Block Diagram IN OUT POR ILIM Charge Pump 0.5V Gate Driver and Control Logic 1.2V 1V BAT FAULT OTP EN Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 GND 9 www.anpec.com.tw APL3203D Typical Application Circuit 5V Adapter/USB 1 IN OUT 8 1µF Charger 1µF APL3203D 50K 4 VIO MCU FAULT 50K EN 25K 7 5 GPIO 50K 6 ILIM BAT GND 100K 2 Li+ Battery Figure 1. The Typical Protection Circuit for Charger Systems. Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 10 www.anpec.com.tw APL3203D Function Description the internal power FET is turned off. When the BP voltage returns below the battery OVP threshold minus the Power-Up The APL3203D has a built-in power-on-reset circuit to keep the output shutting off until internal circuitry is oper- hysteresis, the FET is turned on again. The APL3203D has a built-in counter. When the total count of battery OVP ating properly. The POR circuit has hysteresis and a deglitch feature so that it will typically ignore undershoot fault reaches 16, the FET is turned off permanently, requiring either a VIN POR or EN re-enable again to restart. transients on the input. When input voltage exceeds the POR threshold and after 8ms blanking time, the output Over-Temperature Protection voltage starts a soft-start to reduce the inrush current. When the junction temperature exceeds 140οC, the internal thermal sense circuit turns off the power FET and Input Over-Voltage Protection (OVP) allows the device to cool down. When the device’s junction temperature cools by 20οC, the internal thermal sense The input voltage is monitored by the internal OVP circuit. When the input voltage rises above the input OVP circuit will enable the device, resulting in a pulsed output during continuous thermal protection. Thermal protec- threshold, the internal FET will be turned off within 1µs to protect connected system on OUT pin. When the input tion is designed to protect the IC in the event of over temperature conditions. For normal operation, the junction voltage returns below the input OVP threshold minus the hysteresis, the FET is turned on again after 8ms recovery temperature cannot exceed TJ=+125 οC. time. The input OVP circuit has a 200mV hysteresis and a recovery time of TON(OVP) to provide noise immunity FAULT Output against transient conditions. Over-Current Protection (OCP) The APL3203D provides an open-drain output to indicate that a fault has occurred. When any of input OVP, OCP, The output current is monitored by the internal OCP circuit. battery OVP, is detected, the FAULT goes low to indicate When the output current reaches the OCP threshold, the device limits the output current at OCP threshold level. If that a fault has occurred. Since the FAULT pin is an opendrain output, connecting a resistor to a pull high voltage the OCP condition continues for a blanking time of TB(OCP), the internal power FET is turned off. After the recovery is necessary. Enable/Shutdown time of TON(OCP), the FET will be turned on again and the output current is monitored again. The APL3203D has Pull the EN pin voltage above 1.4V to disable the device have a built-in counter. When the total count of OCP fault reaches 16, the FET is turned off permanently, requiring and pull EN pin voltage below 0.4V to enable the device. The EN pin has an internal pull-down resistor and can be either a VIN POR or EN re-enable again to restart. The OCP threshold is programmed by a resistor RILIM con- left floating. When the IC is latched off due to the total count of OCP or battery OVP reaches 16, disable and reenable the device with the EN pin can clear the counter. nected from ILIM pin to GND. The OCP threshold is calculated by the following equation: KILIM IOCP = RILIM where KILIM=25000AΩ Battery Over-Voltage Protection The APL3203D monitors the BAT pin voltage for battery over-voltage protection. The battery OVP threshold is internally set to 4.435V. When the BAT pin voltage exceeds the battery OVP threshold for a blanking time of TB(BOVP), Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 11 www.anpec.com.tw APL3203D Function Description (Cont.) VOVP VPOR VIN VOUT VFAULT TB(IN) TON(OVP) Figure 2. OVP Timing Chart VOUT OCP Threshold Count 13 times IOUT VFAULT TB(OCP) TON(OCP) TB(OCP) TB(OCP) Total count 16 times IC is latched off Figure 3. OCP Timing Chart Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 12 www.anpec.com.tw APL3203D Function Description (Cont.) VBAT VBOVP VBOVP VBOVP Count 13 times VOUT VFAULT TB(BOVP) TB(BOVP) TB(BOVP) Total count 16 times IC is latched off Figure 4. Battery OVP Timing Chart Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 13 www.anpec.com.tw APL3203D Application Information RBAT Selection RUP FAULT Connect the BAT pin to the positive terminal of battery VIO through a resistor RBAT for battery OVP function. The RBAT limits the current flowing from BAT to battery in case of RFAULT GPIO BAT pin is shortened to VIN pin under a failure mode. The recommended value of RBAT is 100kΩ. In the worse case REN EN of an IC failure, the current flowing from the BAT pin to the battery is: MCU GPIO BAT RBAT (30V-3V)/ 100kΩ =270µA where the 30V is the maximum IN voltage and the 3V is Li+ Battery the minimum battery voltage. The current is so small and can be absorbed by the charger system. Figure 5. RUP, RFAULT, REN and RBAT The disadvantage with the large RBAT is that the error of the battery OVP threshold will be increased. The addi- Capacitor Selection The input capacitor is for decoupling and prevents the input voltage from overshooting to dangerous levels. In tional error is the voltage drop across the RBAT because of the BAT bias current. When RBAT is 100kΩ, the worse- the AC adapter hot plug-in applications or load current step-down transient, the input voltage has a transient case additional error is 100kΩx20nA=2mV, which is acceptable in most applications. spike due to the parasitic inductance of the input cable. A 25V, X5R, dielectric ceramic capacitor with a value be- REN Selection tween 1µF and 4.7µF placed close to the IN pin is For the same reason as the BAT pin case, the EN pin recommended. The output capacitor is for output voltage decoupling, and should be connected to the MCU GPIO pin through a resistor. The value of the REN is dependent on the IO also can be as the input capacitor of the charging circuit. At least, a 1µF, 10V, X5R capacitor is recommended. voltage of the MCU. Since the IO voltage is divided by REN and EN internal pull low resistor for EN voltage. It has to be ensured that the EN voltage is above the EN logic high voltage when the Layout Consideration GPIO output of the MCU is high. In some failure modes, a high voltage may be applied to the device. Make sure the clearance constraint of the PCB FAULT Output layout must satisfy the design rule for high voltage. The exposed pad of the TDFN2x2-8 performs the func- Since the FAULT pin is an open-drain output, connecting a resistor RUP to a pull high voltage is necessary. It is also tion of channeling heat away. It is recommended that connect the exposed pad to a large copper ground plane recommended that connect the FAULT to the MCU GPIO through a resistor RFAULT. The RFAULT prevents damage to on the backside of the circuit board through several thermal vias to improve heat dissipation. the MCU under a failure mode. The recommended value of the resistors should be between 10kΩ to 100kΩ. The input and output capacitors should be placed close to the IC. RILIM also should be placed close to the IC. The high current traces like input trace and output trace must be wide and short. Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 14 www.anpec.com.tw APL3203D Package Information TDFN2x2-8 A b E D D2 A1 E2 A3 L Pin 1 Corner e S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 TDFN2x2-8 MILLIMETERS A3 INCHES 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 1.90 2.10 0.075 0.083 0.063 D2 1.00 1.60 0.039 E 1.90 2.10 0.075 0.083 1.00 0.024 0.039 E2 0.60 e L 0.50 BSC 0.30 Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 0.020 BSC 0.012 0.45 15 0.018 www.anpec.com.tw APL3203D Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN2x2-8 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 2.35±0.20 2.35±0.20 1.00±0.20 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type TDFN2x2-8 Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 Unit Tape & Reel Quantity 3000 16 www.anpec.com.tw APL3203D Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 17 www.anpec.com.tw APL3203D Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 18 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL3203D Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.6 - Mar., 2013 19 www.anpec.com.tw