APL3215/A Li+ Charger Protection IC with Integrated P-MOSFET Features • • • • • • • • • General Description Input Over-Voltage Protection Input Over-Current Protection The APL3215/A provides complete Li+ charger protection against input over-voltage, input over-current, and battery Battery Over-Voltage Protection High Immunity of False Triggering over-voltage. When any of the monitored parameters are over the threshold, the IC removes the power from the High Accuracy Protection Threshold A Built-In P-MOSFET charging system by turning off an internal switch. All protections also have deglitch time against false triggering Thermal Shutdown Protection Available in a TDFN2x2-8 Package due to voltage spikes or current transients. The APL3215/A integrates a P-MOSFET with the body di- Lead Free and Green Devices Available (RoHS Compliant) ode reverse protection to replace the external P-MOSFET and Schottky diode for charger function of cell phone’s PMIC. When the CHRIN voltage drops below VBAT+20mV, the internal power select circuit will reverse the body diode’s terminal to prevent a reverse current flowing from the battery back to CHRIN pin. The APL3215/A provides complete Li+ charger protections and saves the external MOSFET and Schottky diode Applications • for the charger of cell phone’s PMIC. The above features and small package make the APL3215/A an ideal part for Cell Phones cell phones applications. Pin Configuration Simplified Application Circuit ACIN 1 8 OUT ACIN 2 7 OUT GND 3 EP VBAT 4 5V Adapter or USB ACIN CHRIN 6 CHRIN 5 GATDRV TDFN2x2-8 (Top View) EP APL3215/A PMIC GATDRV OUT GATDRV ISENS GND = Exposed Pad (connected to ground plane for better heat dissipation) CHRIN VBAT VBAT Li+ Battery ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 1 www.anpec.com.tw APL3215/A Ordering and Marking Information APL3215 APL3215A Package Code QB : TDFN2x2-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code APL3215 QB: APL3215A QB: L15 X X - Date Code L15A X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Rating Unit VACIN ACIN Input Voltage (ACIN to GND) Parameter -0.3 ~ 20 V VCHRIN CHRIN to GND Voltage -0.3 ~ 7 V VGATDRV GATDRV to GND Voltage -0.3 ~ VCHRIN V VBAT VBAT to GND Voltage -0.3 ~ 7 V VOUT OUT to GND Voltage -0.3 ~ 7 V IOUT OUT Output Current 1.5 TJ Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds A 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristic Symbol θJA Parameter Junction-to-Ambient Resistance in Free Air Typical Value Unit (Note 2) o TDFN2x2-8 75 C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TDFN2x2-8 is soldered directly on the PCB. Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 2 www.anpec.com.tw APL3215/A Recommended Operating Conditions (Note 3) Symbol Parameter Range Unit 4.5 ~ 5.5 V Output Current 0 ~ 700 mA Ambient Temperature -40 ~ 85 o -40 ~ 125 o VACIN ACIN Input Voltage IOUT TA TJ Junction Temperature C C Note 3: Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3215/A Test Conditions Unit Min. Typ. Max. - 250 350 ACIN INPUT CURRENT AND POWER-ON-RESET (POR) IACIN VACIN TB(ACIN) ACIN Supply Current IOUT=0A, ICHRIN=0A, TA=25oC µA ACIN POR Threshold 2.4 - 2.8 V ACIN POR Hysteresis 200 275 350 mV - 8 - ms - 0.5 - Ω - 500 - Ω ACIN Power-On Blanking Time INTERNAL SWITCH ON RESISTANCE ACIN to OUT On Resistance IOUT=0.7A CHRIN Discharge On Resistance INPUT OVER-VOLTAGE PROTECTION (OVP) VOVP Input OVP Threshold APL3215 VACIN rising APL3215A Input OVP Hysteresis TON(OVP) 6 6.17 6.35 6.6 6.8 7 V 200 300 400 Input OVP Propagation Delay - - 1 mV µs Input OVP Recovery Time - 8 - ms OVER-CURRENT PROTECTION (OCP) IOCP OCP Threshold TA=25oC 1 1.5 - A TB(OCP) OCP Blanking Time - 176 - µs TON(OCP) OCP Recovery Time - 64 - ms 4.32 4.35 4.38 V 220 270 320 mV - - 20 nA - 176 - µs VCHRIN from low to high, P-MOSFET is controlled by GATDRV - 150 - VCHRIN from high to low, P-MOSFET is off - 20 - OUT Input Current VCHRIN=0V, VOUT=4.2V, VGATDRV=0V - - 1 µA GATDRV Leakage Current VACIN=VCHRIN= VOUT=5V, VGATDRV=0V - - 1 µA OUT Leakage Current VACIN=VCHRIN= VGATDRV =5V, VOUT=0V - - 1 µA BATTERY OVER-VOLTAGE PROTECTION VBOVP Battery OVP Threshold VBAT rising Battery OVP Hysteresis IVBAT VBAT Pin Leakage Current TB(BOVP) Battery OVP Blanking Time VBAT = 4.4V CHRIN, OUT AND GATDRV VCHRIN-VBAT Lockout Threshold Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 3 mV www.anpec.com.tw APL3215/A Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3215/A Test Conditions Unit Min. Typ. Max. P-MOSFET Input Capacitance - 200 - pF GATDRV Gate Resistance - 15 - Ω P-MOSFET Gate Threshold Voltage IOUT=0.7A - 1.8 - V - 160 - o - o CHRIN, OUT AND GATDRV (CONT.) THERMAL SHUTDOWN PROTECTION TOTP Thermal Shutdown Threshold Thermal Shutdown Hysteresis Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 - 4 40 C C www.anpec.com.tw APL3215/A Typical Operating Characteristics Input OVP Threshold vs. Junction Temperature 1.55 APL3215A 1.50 6.9 VACIN Increasing OCP Threshold, IOCP (A) Input OVP Threshold , VOVP (V) 7.0 OCP Threshold vs. Junction Temperature 6.8 6.7 6.6 6.5 6.4 VACIN Decreasing 6.3 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 6.2 -50 -25 0 25 50 75 100 1.00 -50 125 -25 Junction Temperature (oC) 50 75 100 125 Junction Temperature ( C) Power Switch On Resistance vs. Junction Temperature 800 4.40 4.35 Power Switch On Resistance, RDS,ON (mΩ) Battery OVP Threshold, VBOVP (V) 25 o Battery OVP Threshold vs. Junction Temperature VBAT Increasing 4.30 4.25 4.20 4.15 VBAT Decreasing 4.10 4.05 4.00 -50 -25 0 25 50 75 700 ACIN to OUT On Resistance 600 500 400 300 -50 100 125 -25 0 25 50 75 100 125 o Junction Temperature (oC) Junction Temperature ( C) ACIN Supply Current vs. Junction Temperature POR Threshold vs. Junction Temperature 350 2.8 325 2.7 POR Threshold, VPOR (V) ACIN Supply Current, I ACIN (µA) 0 300 275 250 225 200 VACIN Increasing 2.6 2.5 2.4 2.3 VACIN Decreasing 2.2 2.1 175 150 2.0 -50 -25 0 25 50 75 100 125 -50 o 0 25 50 75 100 125 o Junction Temperature ( C) Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 -25 Junction Temperature ( C) 5 www.anpec.com.tw APL3215/A Operating Waveforms The test condition is VACIN=5V, VBAT=3.8V, CACIN=1µF, CCHRIN=1µF, TA= 25oC unless otherwise specified. Normal Power On OVP at Power On VACIN 1 VACIN VOUT 1 VCHRIN 2 VCHRIN VOUT 2,3 IOUT 4 3 VGATDRV = VCHRIN CH1: VACIN, 5V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VCHRIN, 2V/Div, DC CH4: IOUT, 0.2A/Div, DC TIME: 2ms/Div VACIN = 0 to 12V, VGATDRV = VCHRIN CH1: VACIN, 10V/Div, DC CH2: VCHRIN, 2V/Div, DC CH3: VOUT, 2V/Div, DC TIME: 2ms/Div Recovery from Input OVP Input Over-Voltage Pretection APL3215A APL3215A VACIN VACIN 1 VCHRIN 1 VCHRIN 2 IOUT 2 3 IOUT 3 VACIN = 5V to 12V, ROUT = 50Ω VACIN = 12V to 5V, ROUT = 50Ω CH1: VACIN, 5V/Div, DC CH2: VCHRIN, 2V/Div, DC CH3: IOUT, 100mA/Div, DC TIME:5µs/Div CH1: VACIN, 5V/Div, DC CH2: VCHRIN, 2V/Div, DC CH3: IOUT, 100mA/Div, DC TIME: 2ms/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 6 www.anpec.com.tw APL3215/A Operating Waveforms (Cont.) The test condition is VACIN=5V, VBAT=3.8V, CACIN=1µF, CCHRIN=1µF, TA= 25oC unless otherwise specified. Battery Over-Voltage Protection Battery Over-Voltage Protection VBAT VBAT 1 1 VCHRIN VCHRIN 2 2 VBAT = 3.6V to 4.4V to 3.6V VBAT = 3.6V to 4.4V CH1: VBAT, 2V/Div, AC CH2: VCHRIN, 2V/Div, DC TIME: 50ms/Div CH1: VBAT, 2V/Div, DC CH2: VCHRIN, 2V/Div, DC TIME: 200µs/Div Over-Current Pretection Over-Current Protection VCHRIN VACIN 1 VOUT VCHRIN 1 2 2 VOUT IOUT IOUT 3 3 ROUT=2.5Ω, VBAT = 0V, VGATDRV=0V IOUT = 0A to 1.3A, VBAT = 0V, VGATDRV=0V CH1: VACIN, 5V/Div, DC CH2: VCHRIN, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: IOUT, 1A/Div, DC TIME: 200ms/Div Note: OUT pin connected with a resistor to ground. CH1: VCHRIN, 2V/Div, DC CH2: VOUT, 2V/Div, DC CH3: IOUT, 0.5A/Div, DC TIME: 50µs/Div Note: OUT pin connected with a resistor to ground. Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 7 www.anpec.com.tw APL3215/A Pin Description PIN FUNCTION NO. NAME 1,2 ACIN Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1µF (minimum) ceramic capacitor. 3 GND Ground Terminal. 4 VBAT Battery Voltage Sense Input. Connect this pin to pack positive terminal through a resistor. 5 GATDRV 6 CHRIN 7,8 OUT - EP Internal P-MOSFET Gate Input. Output Pin. This pin provides supply voltage to the PMIC input. Bypass to GND with a 1µF (minimum) ceramic capacitor. Output Pins. These pins provide supply source current in series with a resistor to battery. Exposed Thermal Pad. Must be electrically connected to the GND pin. Block Diagram ACIN CHRIN POR OUT Charge Pump ACIN OVP OCP Gate Driver and Control Logic VBAT OVP 0.5V 1V GATDRV GND VBAT Thermal Shutdown Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 8 www.anpec.com.tw APL3215/A Typical Application Circuit 5V Adapter/USB 1, 2 CACIN 1µF ACIN CHRIN 6 CHRIN CCHRIN 1µF APL3215/A GATDRV PMIC 5 GATDRV 7, 8 ISENS OUT 0.2Ω 3 GND VBAT 4 VBAT RBAT 200kΩ Designation Li+ Battery Description CACIN 1µF, 25V, X5R, 0603 Murata GRM188R61E105K CCHRIN 1µF, 10V, X5R, 0603 Murata GRM188R61A105K Murata website: www.murata.com Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 9 www.anpec.com.tw APL3215/A Function Description ACIN Power-On-Reset (POR) Over-Temperature Protection The APL3215/A has a built-in power-on-reset circuit to When the junction temperature exceeds 160oC, the internal thermal sense circuit turns off the power FET and keep the output shutting off until internal circuitry is operating properly. The POR circuit has hysteresis and a de- allows the device to cool down. When the device’s junction temperature cools by 40 oC, the internal thermal glitch feature so that it will typically ignore undershoot transients on the input. When the input voltage exceeds sense circuit will enable the device, resulting in a pulsed output during continuous thermal protection. Thermal pro- the POR threshold and after 8ms blanking time, the output voltage starts a soft-start to reduce the inrush current. tection is designed to protect the IC in the event of overtemperature conditions. For normal operation, the junc- ACIN Over-Voltage Protection (OVP) tion temperature cannot exceed TJ=+125oC. The input voltage is monitored by the internal OVP circuit. When the input voltage rises above the input OVP Internal P-MOSFET threshold, the internal FET will be turned off within 1µs to protect connected system on OUT pin. When the input The APL3215/A integrates a P-channel MOSFET with the body diode reverse protection to replace the external PMOSFET and Schottky diode for cell phone’s PMIC. The voltage returns below the input OVP threshold minus the hysteresis, the FET is turned on again after 8ms recovery body diode reverse protection prevents a reverse current flowing from the battery back to CHRIN pin. During power- time. The input OVP circuit has a 300mV hysteresis and a recovery time of TON(OVP) to provide noise immunity against transient conditions. on, when CHRIN voltage rises above the VBAT voltage by more than 150mV, the body diode of the P-channel Over-Current Protection (OCP) MOSFET is forward biased from OUT to CHRIN, and PMOSFET is controlled by the external GATDRV voltage. The output current is monitored by the internal OCP circuit. When the CHRIN voltage drops below VBAT+20mV, the body diode of the P-channel MOSFET is forward biased When the output current reaches the OCP threshold, the device limits the output current at OCP threshold level. If from CHRIN to OUT and P-channel MOSFET is turned off. When any of input OVP, OCP, battery OVP, is detected, the OCP condition continues for a blanking time of TB(OCP), the internal power FET is turned off. After the recovery the internal P-channel MOSFET is also turned off. time of TON(OCP), the FET will be turned on again. The APL3215/A has a built-in counter. When the total count of ESD Tests OCP fault reaches 16, the FET is turned off permanently, requiring a VACIN POR again to restart. The APL3215/A VIN input pin fully supports the IEC61000-4-2. That means the VIN pin has immunity of Battery Over-Voltage Protection ±15kV ESD discharge in Air condition, and immunity of ±8kV ESD discharge in Contact condition. The APL3215/A monitors the VBAT pin voltage for battery over-voltage protection. The battery OVP threshold is internally set to 4.35V. When the VBAT pin voltage exceeds the battery OVP threshold for a blanking time of TB(BOVP), the internal power FET is turned off. When the VBAT voltage returns below the battery OVP threshold minus the hysteresis, the FET is turned on again. The APL3215/A has a built-in counter. When the total count of battery OVP fault reaches 16, the FET is turned off permanently, requiring a VACIN POR again to restart. Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 10 www.anpec.com.tw APL3215/A Function Description (Cont.) VOVP VPOR VACIN VCHRIN -VBAT = 150mV VCHRIN -VBAT = 150mV VCHRIN VOUT GATDRV is pulled low P-MOS Gate Control Controlled by GATDRV Turn Off Internal P-MOSFET Controlled by GATDRV Turn Off Internal P-MOSFET TB(ACIN) ACIN OVP TON(OVP) Figure 1. OVP Timing Diagram IOCP IOUT GATDRV is pulled low VCHRIN P-MOS Gate Control Count 13 times Controlled by GATDRV TB(OCP) Turn Off Internal P-MOSFET Controlled by GATDRV TON(OCP) Turn Off Internal PMOSFET TB(OCP) Controlled by GATDRV Turn Off Internal PMOSFET Total count 16 times, IC is TB(OCP) latched off Figure 2. OCP Timing Diagram Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 11 www.anpec.com.tw APL3215/A Function Description (Cont.) VBAT VBOVP VBOVP VCHRIN -VOUT = 150mV VCHRIN Count 13 times P-MOS Gate Controlled Control by GATDRV Turn Off Internal P-MOSFET TB(BOVP) Controlled by GATDRV Turn Off Internal PMOSFET TB(BOVP) Controlled by GATDRV Turn Off Internal P-MOSFET TB(BOVP) Total count 16 times, IC is latched off Figure 3. Battery OVP Timing Diagram Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 12 www.anpec.com.tw APL3215/A Application Information calculated by the following formula : RBAT Selection PD(MAX) = (125oC-25oC) / (75oC/W) = 1.33W Connect the VBAT pin to the positive terminal of battery through a resistor RBAT for battery OVP function. The RBAT for TDFN2x2-8 packages limits the current flowing from VBAT to battery in case of VBAT pin is shortened to ACIN pin under a failure mode. The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resis- The recommended value of RBAT is 200kΩ. In the worse case of an IC failure, the current flowing from the VBAT tance θJA. For APL3215/A packages, the Figure 4 of derating curves allows the designer to see the effect of rising pin to the battery is: ambient temperature on the maximum power allowed. (20V-3V) / 200kΩ =85µA 1.6 where the 20V is the maximum ACIN voltage and the 3V TDFN2x2-8 1.4 Power Dissipation (W) is the minimum battery voltage. The current is so small and can be absorbed by the charger system. Capacitor Selection The input capacitor is for decoupling and prevents the input voltage from overshooting to dangerous levels. In the AC adapter hot plug-in applications or load current 1.2 1.0 0.8 0.6 0.4 0.2 step-down transient, the input voltage has a transient spike due to the parasitic inductance of the input cable. A 0 0 25 50 75 100 125 Ambient Temperature (oC) 25V, X5R, dielectric ceramic capacitor with a value between 1µF and 4.7µF placed close to the ACIN pin is Figure 4. Derating Curves for APL3215/A Packages recommended. The output capacitor of CHRIN is for CHRIN voltage decoupling. Also, it can be as the input capacitor of the charging circuit. At least, a 1µF, 10V, X5R capacitor is Layout Consideration recommended. the device. Make sure the clearance constraint of the PCB layout must satisfy the design rule for high voltage. The In some failure modes, a high voltage may be applied to Thermal Considerations exposed pad of the TDFN2x2-8 performs the function of channeling heat away. It is recommended that connect The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can to improve heat dissipation. The input and output capacitors should be placed close to the IC. The high current be calculated by the following formula: PD(MAX) = (TJ(MAX)-TA) / θJA traces like input trace and output trace must be wide and short. Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of APL3215/A, where TJ(MAX) is 125oC and TA is the operated ambient temperature. The junction to ambient thermal resistance θJA for TDFN2x2-8 package is 75oC/W on a high effective thermal conductivity test board in free air. The maximum power dissipation at TA = 25 oC can be Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 13 www.anpec.com.tw APL3215/A Package Information TDFN2x2-8 D b E A A1 D2 E2 A3 L K Pin 1 Corner e S Y M B O L TDFN2x2-8 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 1.90 2.10 0.075 0.083 D2 1.00 1.60 0.039 0.063 0.083 0.039 E 1.90 2.10 0.075 E2 0.60 1.00 0.024 0.45 0.012 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.018 0.008 Note : 1. Followed from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 14 www.anpec.com.tw APL3215/A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN2x2-8 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.50±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.4 3.35 MIN 3.35 MIN 1.30±0.20 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity TDFN2x2-8 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 15 www.anpec.com.tw APL3215/A Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 16 www.anpec.com.tw APL3215/A Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 17 www.anpec.com.tw APL3215/A Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Sep., 2011 18 www.anpec.com.tw