REJ03F0285-0100
Rev. 1.00
Dec.08.2009
R8A66154SP
8-bit I/O EXPANDER WITH LED DRIVE FUNCTION
DESCRIPTION
R8A66154 is a semiconductor integrated circuit which has 8-bit shift register function to execute serial in parallel out conversion and parallel in - serial out conversion.
Built in two shift registers for serial in - parallel out and parallel in - serial out are constructed independently,
This IC is able to read serial input data into a shift register while output the serial data converting from the
parallel data input.
Also, parallel data I/O pins can be set to input mode or output mode by a bit.
R8A66154 is useful in a wide range of applications, such as MCU (micro controller unit) I/O port extension
and serial bus system data communication.
Moreover, R8A66154 can be used as the anode common LED drive, too.
FEATURES
Bi-directional serial communication with MCU
Serial data can be input during parallel to serial data conversion
Parallel data I/O pins can be set input mode or output mode by a bit
Schmitt input (DI, CLK, /S, /CS)
N-ch open drain output (DO, D1~D8).
High output current IOL=24mA (at VCC=4.5V), IOL=15mA (at VCC=3.0V)
Parallel data I/O pins (D1~D8)
Wide supply voltage range (Vcc=2.0 to 6.0V)
Wide operating temperature range (Ta=-40 to 85℃)
APPLICATION
Serial - parallel or parallel - serial data conversion for MCU peripheral.
Serial bus control by MCU.
LED array drive, The various LED display modules.
PIN CONFIGURATION (TOP VIEW)
GND
1
16
D1
SERIAL DATA OUTPUT DO
2
15
D2
DI
3
14
D3
CLOCK INPUT CLK
4
13
D4
CHIP SELECT INPUT CS
5
12
D5
Vcc
6
11
D6
S
7
10
D7
GND
8
9
D8
SERIAL DATA INPUT
SET INPUT
REJ03F0285-0100 Rev.1.00 Dec.08.2009
Page 1 of 7
PARALLEL DATA I/O
R8A66154SP
BLOCK DIAGRAM
Vcc
Vcc
6
Shift register 1
DO
D8 D7 D6
D3 D2 D1
S
7
CS
5
DO
CLK, S, CS, DI
S
16 D1
15 D2
14 D3
Control circuit
CLK 4
2
Input type
11 D6
10 D7
9 D8
Vcc
Q8 Q 7 Q6
Q3 Q2 Q1
Parallel output latch
D8 D7 D6
D3 D2 D1
Vcc
D1～D8
DO
Q8 Q7 Q6
Q3 Q 2 Q1
Shift register 2
DI
DI 3
Output
1
8
GND GND
Inout
Output type
FUNCTION
The R8A66154 is produced by using the silicon gate CMOS technology and has low power dissipation and
high noise margin.
Built in two shift registers for serial in-parallel out (Shift register 2) and parallel in-serial out (Shift register 1)
are constructed independently, R8A66154 is able to read serial input data into a shift register while output
the serial data converting from the parallel data input.
Serial output operation of 8-bit parallel latched data and serial input operation from MCU are started when
/CS is changed from "H" to "L".
8-bits parallel data are latched by the negative edge of /CS and are output from the DO terminal
synchronously to the negative edge of CLK, and also the DI terminal read serial input data from MCU and
are written into the internal shift register 2.
The 9th and following shift clock pulse are ignored and serial input data is masked, and DO terminal
becomes high-impedance ("High-Z").
When /CS is changed from "L" to "H", 8-bits serial data which is read from the DI terminal are output to the
D1~D8 terminals as parallel data.
As the output circuit type of D1~D8 terminals is N-ch open drain output, write data "H" for pins which should
be set to input mode.
REJ03F0285-0100 Rev.1.00 Dec.08.2009
Page 2 of 7
R8A66154SP
DESCRIPTION OF OPERATION
(1) When power ON, the status of DO and D1~D8 terminals are not determined. These terminals are turn
to high-impedance when "L" is input to the /S terminal.
(2) By the negative edge of /CS, the status of D1~D8 terminals is loaded on shift register 1.
(3) Synchronous to the negative edge of CLK, 8-bit loaded data is serial output from the DO terminal.
(4) Synchronous to the positive edge of CLK, 8-bit serial input data from DI is written into the shift register 2.
(5) The 9th and following shift clock pulse are ignored and the serial data input operation is stopped.
And the DO terminal becomes high-impedance ("High-Z").
(6) By the positive edge of /CS, input data described in (4) is output to D1~D8 terminals.
(7) Shift register 1 loads the AND tie data of external parallel input data and latched data on parallel output
latch.
(8) If the /CS is changed from "L" to "H" before reaches the 8th bit of CLK, parallel output latch latches
data which has been written on shift register 2 and output it to D1~D8 terminals. Serial data after this
since is ignored and the DO terminal becomes high-impedance.
(9) Input/output mode set to D1~D8 terminals are done by the serial input data to the DI terminal.
Terminals which "H" is written are set to input, and "L" is written are set to output.
OPERATION TIMING CHART
S
(1)
(2)
CS
1
2
3
4
5
6
7
8
9 (5)
CLK
(4)
DI
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DI2
DI3
DI4
DI5
DI6
DI7
DI8
(3)
DO
High-Z
DI1
High-Z
(6)
D1
D2
High-Z
High-Z
DI1
DO1
DI2
DO2
DI8
DO8
High-Z
D8
１Sequence
REJ03F0285-0100 Rev.1.00 Dec.08.2009
Page 3 of 7
R8A66154SP
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
(Ta=-40~85℃, unless otherwise noted)
Conditions
Ratings
Unit
VCC
Supply voltage
-0.5 ~ +7.0
V
VI
Input voltage
-0.5 ~ Vcc+0.5
V
VO
Output voltage
-0.5 ~ Vcc+0.5
V
IO
Output current per output pin
ICC
Supply / GND current
VCC, GND
Pd
Power dissipation
(Note)
Tstg
Storage temperature range
50
mA
230
mA
500
mW
-65 ~ 150
℃
Note: R8A66154SP: Ta=-40～+80℃. Ta=80～85℃ are derated at -12 mW/℃.
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
VI
VO
Topr
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature range
Limits
Min.
2.0
0
0
-40
Typ.
ELECTRICAL CHARACTERISTICS
Symbol
VT+
VTVIH
VIL
VOL
Parameter
Positive going threshold voltage
(*1)
Negative going threshold voltage
(*1)
"H" input voltage (*2)
"L" input voltage (*2)
"L" output voltage
IO
Output leakage current
IIH
IIL
"H" input current
"L" input current
Icc
Quiescent supply current
*1 : DI, CLK, /CS, /S
*2 : D1~D8
REJ03F0285-0100 Rev.1.00 Dec.08.2009
Page 4 of 7
Max.
6.0
Vcc
Vcc
85
Unit
V
V
V
℃
(Vcc=2.0~6.0V, Ta=-40~85℃, unless otherwise noted)
Test conditions
Vo=0.1V, Vcc-0.1V
l Io l=20uA
Min.
Limits
Typ.
Max.
0.35 x Vcc
0.80 x Vcc
V
0.20 x Vcc
0.65 x Vcc
V
0.25 x Vcc
V
V
V
0.75 x Vcc
VI=VT+,VTVcc=4.5V
VI=VT+,VTVcc=3.0V
VI=VT+,VTVcc=2.0V
IOL=24mA
0.5
IOL=15mA
0.5
V
IOL=8mA
0.3
V
Vo=Vcc
Vo=GND
VI=Vcc, Vcc=6V
VI=GND, Vcc=6V
VI=Vcc, GND
Vcc=6V
Vcc=6V
Unit
10
-10
1
-1
100
uA
uA
uA
R8A66154SP
SWITCHING CHARACTERISTICS
Symbol
fmax
tPLZ
tPZL
tPLZ
tPZL
tPLZ
Parameter
Test conditions
Maximum repeat frequency
Output "L-Z" and "Z-L" propagation time
CLK - DO
Output "L-Z" and "Z-L" propagation time
/CS - D1~D8
Output "L-Z" propagation time
/S - DO, /S - D1~D8
TIMING REQUIREMENTS
Symbol
tw
(Vcc=2.0~6.0V, Ta=-40~85℃, unless otherwise noted)
th
trec
Limits
Typ.
CL=50pF
RL=1kΩ
(note1)
Unit
Max.
1.9
400
400
400
400
MHz
ns
ns
ns
ns
400
ns
(Vcc=2.0~6.0V, Ta=-40~85℃, unless otherwise noted)
Parameter
Test conditions
CLK, /CS, /S pulse width
Setup time of DI to CLK
Setup time of /CS to CLK
Setup time of D1~D8 to /CS
Hold time of DI to CLK
Hold time of /CS to CLK
Hold time of D1~D8 to /CS
Recovery time of /CS to /S
tsu
Min.
Min.
260
130
130
130
130
130
130
130
Limits
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTE1: TEST CIRCUIT
(1) The pulse generator (P.G.) has the following characteristics
(10%~90%)
tr=6ns,
tf=6ns,
Zo=50 Ω
(2) The capacitance CL includes stray wiring capacitance
and the probe input capacitance.
Inpu
Vcc
Vcc
RL
DUT
P.G.
50Ω
DO,
D1～D8
GND
REJ03F0285-0100 Rev.1.00 Dec.08.2009
Page 5 of 7
CL
R8A66154SP
TIMING DIAGRAM
tw
CLK
tw
50%
50%
CS
50%
tPLZ
tPZL
DO
50%
50%
tsu
50%
CLK
th
50%
50%
10%
tw
CS
tw
50%
50%
tPLZ
tPZL
D1～D8
tw
50%
50%
tPLZ
DO,
D1～D8
DI
10%
tsu
CLK
D1～D8
50%
50%
th
50%
50%
50%
tsu
CS
REJ03F0285-0100 Rev.1.00 Dec.08.2009
Page 6 of 7
th
50%
50%
trec
50%
10%
S
S
50%
CS
50%
R8A66154SP
PACKAGE OUTLINE
Package
16pin SOP
RENESAS Code
PRSP0016DJ-A
Previous Code
16P2X-E
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REJ03F0285-0100 Rev.1.00 Dec.08.2009
Page 7 of 7
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