IDT IDT723612L15PQF

IDT723612
BiCMOS SyncBiFIFO
64 x 36 x 2
Integrated Device Technology, Inc.
FEATURES:
• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs (64 x 36 storage
capacity each) buffering data in opposite directions
• Mailbox bypass Register for each FIFO
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor interface control logic
• EFA, FFA, AEA, and AFA flags synchronized by CLKA
• EFB, FFB, AEB, and AFB flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port
•
•
•
•
Low-power advanced BiCMOS technology
Supports clock frequencies up to 67 MHz
Fast access times of 10ns
Available in 132-pin plastic quad flat package (PQF) or
space-saving 120-pin thin quad flat package (TQFP)
• Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT723612 is a monolithic high-speed, low-power
BiCMOS bi-directional clocked FIFO memory. It supports
clock frequencies up to 67 MHz and has read access times as
FUNCTIONAL BLOCK DIAGRAM
CLKA
Port-A
Control
Logic
MBF1
EVEN
Parity
Generation
PGB
64 x 36
SRAM
Device
Control
Write
Pointer
FFA
AFA
36
Read
Pointer
EFB
AEB
Status Flag
Logic
FIFO1
36
FS0
FS1
A0 - A35
Programmable Flag
Offset Register
B0 - B36
FIFO2
EFA
AEA
FFB
AFB
Status Flag
Logic
Parity
Generation
Output
Register
Read
Pointer
PGA
Parity
Gen/Check
PEFA
Write
Pointer
64 x 36
SRAM
36
Input
Register
ODD/
Input
Register
RST
PEFB
Parity
Gen/Check
Mail 1
Register
Output
Register
CSA
W/RA
ENA
MBA
Mail 2
Register
Port-B
Control
Logic
MBF2
CLKB
CSB
W/RB
ENB
MBB
3136 drw 01
The IDT logo is a registered trademark and Sync BiFIFO is a trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
1997 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3136/4
1
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
fast as 10ns. Two independent 64 x 36 dual-port SRAM
FIFOs on board the chip buffer data in opposite directions.
Each FIFO has flags to indicate empty and full conditions and
two programmable flags (almost-full and almost-empty) to
indicate when a selected number of words is stored in
memory. Communication between each port can bypass the
FIFOs via two 36-bit mailbox registers. Each mailbox register
has a flag to signal when new mail has been stored. Parity is
checked passively on each port and may be ignored if not
desired. Parity generation can be selected for data read from
each port. Two or more devices can be used in parallel to
create wider data paths.
The IDT723612 is a clocked FIFO, which means each port
employs a synchronous interface. All data transfers through
a port are gated to the LOW-to-HIGH transition of a port clock
by enable signals. The clocks for each port are independent
of one another and can be asynchronous or coincident. The
enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses
with synchronous control.
The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of
a FIFO are two-stage synchronized to the port clock that writes
data to its array. The empty flag (EFA, EFB) and almost-empty
(AEA, AEB) flag of a FIFO are two stage synchronized to the
port clock that reads data from its array.
The IDT723612 is characterized for operation from 0°C to
70°C.
GND
PGB
VCC
W/ B
CLKB
ENB
GND
NC
NC
NC
NC
MBB
MBA
FS1
FS0
ODD/
GND
*
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
GND
B0
B1
B2
GND
B3
B4
B5
B6
VCC
B7
B8
B9
GND
B10
B11
VCC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
VCC
A24
A25
A26
GND
A27
A28
A29
VCC
A30
A31
A32
GND
A33
A34
A35
GND
B35
B34
B33
GND
B32
B31
B30
VCC
B29
B28
B27
GND
B26
B25
B24
VCC
A0
A1
A2
GND
A3
A4
A5
A6
VCC
A7
A8
A9
GND
A10
A11
VCC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
GND
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
ENA
CLKA
W/ A
VCC
PGA
PIN CONFIGURATIONS
3136 drw 02
*
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP (PQ132-1, order code: PQF)
TOP VIEW
Note:
1. NC - No internal connection
2. Uses Yamaichi socket IC51-1324-828
2
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
A24
A25
A26
VCC
A27
A28
A29
GND
A30
A31
A32
A33
A34
A35
GND
B35
B34
B33
B32
B31
B30
GND
B29
B28
B27
VCC
B26
B25
B24
B23
PIN CONFIGURATIONS (CONT.)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
B8
B7
VCC
B6
B5
B4
B3
GND
B2
B1
B0
PGB
VCC
W/ B
CLKB
ENB
GND
NC
NC
NC
NC
MBB
ODD/
MBA
FS1
FS0
ENA
CLKA
W/ A
VCC
PGA
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
VCC
A6
A5
A4
A3
GND
A2
A1
A0
3136 drw 03
TQFP (PN120-1, order code: PF)
TOP VIEW
Note:
1. NC - No internal connection
3
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
A0-A35
Name
Port-A Data
I/O
I/O
AEA
Almost-Empty Flag
O
(Port A)
AEB
AFA
AFB
Port-B Almost-Empty
O
Flag
(PortB)
Port-A Almost-Full
Flag
O
(Port A)
Port-B Almost-Empty
O
Flag
(Port B)
B0-B35
CLKA
Port-B Data.
Port-A Clock
I/O
I
CLKB
Port-B Clock
I
CSA
Port-A Chip Select
I
CSB
Port-B Chip Select
I
EFA
Port-A Empty Flag
O
(Port A)
EFB
Port-B Empty Flag
O
(Port B)
ENA
Port-A Enable
I
ENB
Port-B Enable
I
FFA
Port-A Full Flag
O
(Port A)
FFB
Port-B Full Flag
O
(Port B)
Programmable almost-empty flag synchronized to CLKA. It is LOW when
the number of words in the FIFO2 is less than or equal to the value in the
offset register, X.
Programmable almost-full flag synchronized to CLKB. It is LOW when the
number of words in FIFO1 is less than or equal to the value in the
offset register, X.
Programmable almost-full flag synchronized to CLKA. It is LOW when the
number of empty locations in FIFO1 is less than or equal to the value in the
offset register, X.
Programmable almost-full flag synchronized to CLKB. It is LOW when the
number of empty locations in FIFO2 is less than or equal to the value in the
offset register, X.
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through portA and can be aynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA
are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through portB and can be asynchronous or coincident to CLKA. EFB, FFB, AFB, and
AEB are synchronized to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A. The A0-A35 outputs are in the high-impedance state
when CSA is HIGH.
B must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B. The B0-B35 outputs are in the high-impedance state
when CSB is HIGH.
FS1, FS0 Flag-Offset Selects
MBA
Description
36-bit bidirectional data port for side A.
Port-A Mailbox Select
I
I
EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is
LOW, FIFO2 is empty, and reads from its memory are disabled. Data can
be read from FIFO2 to the output register when EFA is HIGH. EFA is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after data is loaded into empty FIFO2 memory.
EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is
LOW, the FIFO1 is empty, and reads from its memory are disabled. Data
can be read from FIFO1 to the output register when EFB is HIGH. EFB is
forced LOW when the device is reset and is set HIGH by the second LOWto-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B.
FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is
LOW, FIFO1 is full, and writes to its memory are disabled. FFA is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after reset.
FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is
LOW, FIFO2 is full, and writes to its memory are disabled. FFB is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after reset.
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1,
which selects one of four preset values for the almost-full flag and almostempty flag.
A HIGH level on MBA chooses a mailbox register for a port-A read or write
operation. When the A0-A35 outputs are active, a HIGH level on MBA
selects data from the mail2 register for output, and a LOW level selects
FIFO2 output register data for output.
4
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
SYMBOL
MBB
MBF1
NAME
I/O
Port-B Mailbox
Select
I
Mail1 Register Flag
O
DESCRIPTION
A HIGH level on MBB chooses a mailbox register for a port-B read or write
operation. When the B0-B35 outputs are active, a HIGH level on MBB selects
data from the mail1 register for output, and a LOW level selects FIFO1
output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to
the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set
LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a portB read is selected and MBB is HIGH. MBF1 is set HIGH when the device is
reset.
MBF2
ODD/
EVEN
PEFA
PEFB
Mail2 Register Flag
Odd/Even Parity
Select
Port-A Parity Error
Flag
Port-B Parity Error
Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to
the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set
LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a portA read is selected and MBA is HIGH. MBF2 is set HIGH when the device is
reset.
Odd parity is checked on each port when ODD/EVEN is HIGH, and even
parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.
O
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW.
(Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the
most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected by PGA. Therefore, if a mail2 read with
parity generation is setup by having W/RA LOW, MBA HIGH, and PGA HIGH,
the PEFA flag is forcedHIGH regardless of the A0-A35 inputs.
O
When any byte applied to terminals B0-B35 fails parity, PEFB is LOW.
(Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most
significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate
parity if parity generation is selected by PGB. Therefore, if a mail1 read with
parity generation is setup by having W/RB LOW, MBB HIGH, and PGB HIGH,
the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs.
I
Parity is generated for data reads from port A when PGA is HIGH. Generation The type of parity generated is selected by the state of the ODD/EVEN
input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.
I
PGA
Port-A Parity
PGB
Port-B Parity
Generation
I
Parity is generated for data reads from port B when PGB s HIGH. The type of
parity generated is selected by the state of the ODD/EVEN input. Bytes are
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
Reset
I
Port-A Write/Read
Select
I
Port-B Write/Read
Select
I
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-toHIGH transitions of CLKB must occur while RST is LOW. This sets the AFA,
AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA, AEB, FFA, and
FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the
FS1 and FS0 inouts to select almost-full and almost-empty flag offset.
A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/RA is HIGH.
A HIGH selects a write operation and a LOW selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/RB is HIGH.
RST
W/RA
W/RB
5
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE
(UNLESS OTHERWISE NOTED)(2)
Symbol
VCC
(2)
VI
VO
(2)
Rating
Commercial
Unit
-0.5 to 7
V
Input Voltage Range
-0.5 to VCC+0.5
V
Output Voltage Range
-0.5 to VCC+0.5
V
Supply Voltage Range
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
±20
mA
IOK
Output Clamp Current, (VO < 0 or VO > VCC)
±50
mA
IOUT
Continuous Output Current, (VO = 0 to VCC)
±50
mA
ICC
Continuous Current Through VCC or GND
±500
mA
TA
Operating Free Air Temperature Range
0 to 70
°C
TSTG
Storage Temperature Range
-65 to 150
°C
Notes:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min.
Supply Voltage
4.5
Max. Unit
5.5
V
VIH
HIGH Level Input Voltage
2
–
V
VIL
LOW-Level Input Voltage
–
0.8
V
IOH
HIGH-Level Output Current
–
-4
mA
IOL
LOW-Level Output Current
–
8
mA
TA
Operating Free-air
Temperature
0
70
°C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
Test Conditions
VOH
VCC = 4.5V,
IOH = -4 mA
VOL
VCC = 4.5 V,
IOL = 8 mA
ILI
VCC = 5.5 V,
ILO
Min.
Typ.(1)
Max.
2.4
Unit
V
0.5
V
VI = VCC or 0
±50
µA
VCC = 5.5 V,
VO = VCC or 0
±50
µA
ICC
VCC 5.5 V,
IO = 0 mA,
1
mA
CIN
VI= 0,
f = 1 MHz
4
pF
VO = 0,
f = 1 MHZ
8
pF
COUT
VI = VCC or GND
Note:
1. All typical values are at VCC = 5 V, TA = 25°C.
6
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE
Symbol
Parameter
IDT723612L15 IDT723612L20 IDT723612L30
Min. Max. Min. Max. Min. Max.
fS
Clock Frequency, CLKA or CLKB
–
tCLK
Clock Cycle Time, CLKA or CLKB
tCLKH
Pulse Duration, CLKA and CLKB HIGH
tCLKL
tDS
66.7
–
15
–
20
–
30
–
ns
6
–
8
–
12
–
ns
Pulse Duration, CLKA and CLKB LOW
6
–
8
–
12
–
ns
Setup Time, A0-A35 before CLKA↑ and B0-B35
before CLKB↑
4
–
5
–
6
–
ns
6
–
6
–
7
–
ns
Setup Time, CSA, W/RA before CLKA↑; CSB,
W/RB before CLKB↑
tENS1
50
–
33.4
Unit
MHz
tENS2
Setup Time, ENA, before CLKA↑; ENB before
CLKB↑
4
–
5
–
6
–
ns
tENS3
Setup Time, MBA before CLKA↑: MBB before
CLKB↑
4
–
5
–
6
–
ns
4
–
5
–
6
–
ns
Setup Time, ODD/EVEN and PGA before
CLKA↑; ODD/EVEN and PGB before CLKB↑(1)
tPGS
tRSTS
Setup Time, RST LOW before CLKA↑
or CLKB↑(2)
5
–
6
–
7
–
ns
tFSS
Setup Time, FS0/FS1 before RST HIGH
5
–
6
–
7
–
ns
2.5
–
2.5
–
2.5
–
ns
2
–
2
–
2
–
ns
Hold Time, A0-A35 after CLKA↑ and B0-B35
after CLKB↑
tDH
tENH1
Hold Time, CSA W/RA after CLKA↑; CSB,
W/RB after CLKB↑
tENH2
Hold Time, ENA, after CLKA↑; ENB after CLKB↑
2.5
–
2.5
–
2.5
–
ns
tENH3
Hold Time, MBA after CLKA↑; MBB after CLKB↑
1
–
1
–
1
–
ns
tPGH
Hold Time, ODD/EVEN and PGA after CLKA↑;
ODD/EVEN and PGB after CLKB↑(1)
1
–
1
–
1
–
ns
5
–
6
–
7
–
ns
4
–
4
–
4
–
ns
Skew Time, between CLKA↑ and CLKB↑
for EFA, EFB, FFA, and FFB
8
–
8
–
10
–
ns
tSKEW2(3) Skew Time, between CLKA↑ and CLKB↑
For AEA, AEB, AFA, and AFB
9
–
16
–
20
–
ns
Hold Time, RST LOW after CLKA↑ or CLKB↑(2)
tRSTH
Hold Time, FS0 and FS1 after RST HIGH
tFSH
tSKEW1
(3)
Notes:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
7
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF
Symbol
tA
tWFF
tREF
tPAE
tPAF
tPMF
Parameter
IDT723612L15 IDT723612L20 IDT723612L30
Min. Max. Min. Max. Min. Max.
Access Time, CLKA↑ to A0-A35 and CLKB↑
to B0-B35
Propagation Delay Time, CLKA↑ to FFA and
CLKB↑ to FFB
Propagation Delay Time, CLKA↑ to EFA and
and CLKB↑ to EFB
Propagation Delay Time, CLKA↑ to AEA and
CLKB↑ to AEB
Propagation Delay Time, CLKA↑ to AFA and
CLKB↑ to AFB
Propagation Delay Time, CLKA↑ to MBF1 LOW
or MBF2 HIGH and CLKB↑ to MBF2 LOW or
MBF1 HIGH
Unit
2
10
2
12
2
15
ns
2
10
2
12
2
15
ns
2
10
2
12
2
15
ns
2
10
2
12
2
15
ns
2
10
2
12
2
15
ns
1
9
1
12
1
15
ns
tPMR
Propagation Delay Time, CLKA↑ to B0-B35(1)
and CLKB↑ to A0-A35(2)
3
11
3
13
3
15
ns
tMDV
Propagation Delay Time, MBA to A0-A35 valid
and MBB to B0-B35 valid
1
11
1
11.5
1
12
ns
3
10
3
11
3
13
ns
3
11
3
12
3
14
ns
2
11
2
12
2
14
ns
1
11
1
12
1
14
ns
3
12
3
13
3
14
ns
1
15
1
20
1
30
ns
2
10
2
12
2
14
ns
1
8
1
9
1
11
ns
tPDPE
tPOPE
tPOPB(3)
tPEPE
tPEPB(3)
tRSF
tEN
tDIS
Propagation Delay Time, A0-A35 valid to PEFA
valid; B0-B35 valid to PEFB valid
Propagation Delay Time, ODD/EVEN to PEFA
and PEFB
Propagation Delay Time, ODD/EVEN to parity
bits (A8, A17, A26, A35) and (B8, B17, B26,
B35)
Propagation Delay Time, W/RA, CSA, ENA, MBA or
PGA to PEFA; W/RB, CSB, ENB. MBB, PGB to PEFB
Propagation Delay Time, W/RA, CSA, ENA, MBA or
PGA to parity bits (A8, A17, A26, A35); W/RB, CSB,
ENB. MBB or PGB to parity bits (B8, B17, B26, B35)
Propagation Delay Time, RST to (AEA, AEB)
LOW and (AFA, AFB, MBF1, MBF2) HIGH
Enable Time, CSA and W/RA LOW to A0-A35
active and CSB LOW and W/RB HIGH to
B0-B35 active
Disable Time, CSA or W/RA HIGH to A0-A35
at high impedance and CSB HIGH or W/RB
LOW to B0-B35 at high impedance
Notes:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
8
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTIONS
RESET
The IDT723612 is reset by taking the reset (RST) input
LOW for at least four port-A clock (CLKA) and four port-B clock
(CLKB) LOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of each FIFO and forces the
full flags (FFA, FFB) LOW, the empty flags (EFA, EFB) LOW,
the almost-empty flags (AEA, AEB) LOW and the almost-full
flags (AFA, AFB) HIGH. A reset also forces the mailbox flags
(MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two
LOW-to-HIGH transitions of CLKA and FFB is set HIGH after
two LOW-to-HIGH transitions of CLKB. The device must be
reset after power up before data is written to its memory.
FS1
FS0
RST
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H
H
↑
16
H
L
↑
12
L
H
↑
8
L
L
↑
4
Table 1. Flag Programming
A LOW-to-HIGH transition on the RST input loads the
almost-full and almost-empty registers (X) with the values
selected by the flag-select (FS0, FS1) inputs. The values that
can be loaded into the registers are shown in Table 1.
FIFO WRITE/READ OPERATION
The state of port-A data A0-A35 outputs is controlled by
the port-A chip select (CSA) and the port-A write/read select
(W/RA). The A0-A35 outputs are in the high-impedance state
when either CSA or W/RA is HIGH. The A0-A35 outputs are
active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH. Data is
read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA is HIGH (see Table 2).
The port-B control signals are identical to those of port A.
The state of the port-B data (B0-B35) outputs is controlled by
the port-B chip select (CSB) and the port-B write/read select
(W/RB). The B0-B35 outputs are in the high-impedance state
when either CSB or W/RB is HIGH. The B0-B35 outputs are
active when both CSB and W/RB are LOW.
Data is loaded into FIFO2 from the B0-B35 inputs on a
LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is
HIGH, ENB is HIGH, MBB is LOW, and FFB is HIGH. Data is
read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH
CSA
W/RA
ENA
MBA
CLKA
A0-A35 Outputs
Port Functions
H
X
X
X
X
In High-Impedance State
None
L
H
L
X
X
In High-Impedance State
None
L
H
H
L
↑
In High-Impedance State
FIFO1 Write
L
H
H
H
↑
In High-Impedance State
Mail1 Write
L
L
L
L
X
Active, FIFO2 Output Register
None
L
L
H
L
↑
Active, FIFO2 Output Register
FIFO2 Read
L
L
L
H
X
Active, Mail2 Register
None
L
L
H
H
↑
Active, Mail2 Register
Mail2 Read (Set MBF2 HIGH)
Table 2. Port-A Enable Function Table
CSB
W/RB
ENB
MBB
CLKB
B0-B35 Outputs
Port Functions
H
X
X
X
X
In High-Impedance State
None
L
H
L
X
X
In High-Impedance State
None
L
H
H
L
↑
In High-Impedance State
FIFO2 Write
L
H
H
H
↑
In High-Impedance State
Mail2 Write
L
L
L
L
X
Active, FIFO1 Output Register
None
L
L
H
L
↑
Active, FIFO1 Output Register
FIFO1 read
L
L
L
H
X
Active, Mail1 Register
None
L
L
H
H
↑
Active, Mail1 Register
Mail1 Read (Set MBF1 HIGH)
Table 3. Port-B Enable Function Table
9
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
transition of CLKB when CSB is LOW, W/RB is LOW, ENB is
HIGH, MBB is LOW, and EFB is HIGH (see Table 3).
The setup and hold time constraints to the port clocks for
the port chip selects (CSA, CSB) and write/read selects (W/
RA, W/RB) are only for enabling write and read operations and
are not related to high-impedance control of the data outputs.
If a port enable is LOW during a clock cycle, the port chip select
and write/read select may change states during the setup and
hold time window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through two
flip-flop stages. This is done to improve flag reliability by
reducing the probability of metastable events on the output
when CLKA and CLKB operate asynchronously to one another. EFA, AEA, FFA, and AFA are synchronized by CLKA.
EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables
4 and 5 show the relationship of each port flag to FIFO1 and
FIFO2.
EMPTY FLAGS (EFA, EFB)
The empty flag of a FIFO is synchronized to the port clock
that reads data from its array. When the empty flag is HIGH,
new data can be read to the FIFO output register. When the
empty flag is LOW, the FIFO is empty and attempted FIFO
reads are ignored.
The read pointer of a FIFO is incremented each time a
new word is clocked to the output register. The state machine
that controls an empty flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. A word written to a
FIFO can be read to the FIFO output register in a minimum of
three cycles of the empty flag synchronizing clock. Therefore,
an empty flag is LOW if a word in memory is the next data to
be sent to the FIFO output register and two cycles of the port
clock that reads data from the FIFO have not elapsed since the
time the word was written. The empty flag of the FIFO is set
HIGH by the second LOW-to-HIGH transition of the synchronizing clock, and the new data word can be read to the FIFO
output register in the following cycle.
Number of Words
Synchronized
Synchronized
to CLKB
to CLKA
to CLKB
to CLKA
0
L
L
H
H
H
1 to X
H
L
H
H
H
H
(X+1) to [64-(X+1)]
H
H
H
H
L
H
(64-X) to 63
H
H
L
H
L
64
H
H
L
L
0
L
L
H
H
1 to X
H
L
H
(X+1) to [64-(X+1)]
H
H
(64-X) to 63
H
H
H
Synchronized
FFB
FFA
H
Number of Words
Synchronized
AFB
AFA
64
ALMOST EMPTY FLAGS (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the
port clock that reads data from its array. The state machine
that controls an almost-empty flag monitors a write-pointer
comparator that indicates when the FIFO SRAM status is
almost empty, almost empty+1, or almost empty+2. The
almost-empty state is defined by the value of the almost-full
and almost-empty offset register (X). This register is loaded
with one of four preset values during a device reset (see Reset
above). An almost-empty flag is LOW when the FIFO contains
AEA
AEB
in the FIFO1
FULL FLAG (FFA, FFB)
The full flag of a FIFO is synchronized to the port clock
that writes data to its array. When the full flag is HIGH, a
memory location is free in the SRAM to receive new data. No
memory locations are free when the full flag is LOW and
attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is
incremented. The state machine that controls a full flag
monitors a write-pointer and read pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, the previous
memory location is ready to be written in a minimum of three
cycles of the full flag synchronizing clock. Therefore, a full flag
is LOW if less than two cycles of the full flag synchronizing
clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the full
flag synchronization clock after the read sets the full flag HIGH
and the data can be written in the following clock cycle.
A LOW-to-HIGH transition on a full flag synchronizing
clock begins the first synchronization cycle of a read if the
clock transition occurs at time tSKEW1 or greater after the read.
Otherwise, the subsequent clock cycle can be the first synchronization cycle.
EFA
EFB
(1)
A LOW-to-HIGH transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the
clock transition occurs at time tSKEW1 or greater after the write.
Otherwise, the subsequent clock cycle can be the first synchronization cycle.
L
Table 4. FIFO1 Flag Operation
(1)
in the FIFO
Table 5. FIFO2 Flag Operation
Note:
1. X is the value in the almost-empty flag and almost-full flag offset register.
10
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
X or less words in memory and is HIGH when the FIFO
contains (X+1) or more words.
Two LOW-to-HIGH transitions of the almost-empty flag
synchronizing clocks are required after a FIFO write for the
almost-empty flag to reflect the new level of fill. Therefore, the
almost-empty flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of the synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An almost-empty flag is set HIGH by the second LOWto-HIGH transition of the synchronizing clock after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an almost-empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figure 6 and 7).
ALMOST FULL FLAGS (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array. The state machine that
controls an almost-full flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the value of the almost-full and almostempty offset register (X). This register is loaded with one of
four preset values during a device reset (see Reset above).
An almost-full flag is LOW when the FIFO contains (64-X) or
more words in memory and is HIGH when the FIFO contains
[64-(X+1)] or less words.
Two LOW-to-HIGH transitions of the almost-full flag
synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill. Therefore, the
almost-full flag of a FIFO containing [64-(X+1)]or less words
remains LOW if two cycles of the synchronizing clock have not
elapsed since the read that reduced the number of words in
memory to [64-(X+1)]. An almost-full flag is set HIGH by the
second LOW-to-HIGH transition of the synchronizing clock
after the FIFO read that reduces the number of words in
memory to [64-(X+1)]. A second LOW-to-HIGH transition of
an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the
read that reduces the number of words in memory to [64(X+1)]. Otherwise, the subsequent synchronizing clock cycle
can be the first synchronization cycle (see Figure 13 and 14).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command
and control information between port A and port B without
putting it in queue. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A LOW-to-HIGH transition on CLKA writes
A0-A35 data to the mail1 register when a port-A write is
selected by CSA, W/RA, and ENA and MBA HIGH. A LOWto-HIGH transition on CLKB writes B0-B35 data to the mail2
register when a port-B write is selected by CSB, W/RB, and
ENB and MBB is HIGH. Writing data to a mail register sets the
corresponding flag (MBF1 or MBF2) LOW. Attempted writes
to a mail register are ignored while the mail flag is LOW.
COMMERCIAL TEMPERATURE RANGE
When a port's data outputs are active, the data on the bus
comes from the FIFO output register when the port mailboxselect input (MBA, MBB) is LOW and from the mail register
when the port mailbox-select input is HIGH. The mail1 register
flag (MBF1) is set HIGH by a LOW-to-HIGH transition on
CLKB when a port-B read is selected by CSB, W/RB, and ENB
and MBB is HIGH. The mail2 register flag (MBF2) is set HIGH
by a LOW-to-HIGH transition on CLKA when port-A read is
selected by CSA, W/RA, and ENA and MBA is HIGH. The data
in a mail register remains intact after it is read and changes
only when new data is written to the register.
PARITY CHECKING
The port-A inputs (A0-A35) and port-B inputs (B0-B35)
each have four parity trees to check the parity of incoming (or
outgoing) data. A parity failure on one or more bytes of the
input bus is reported by a LOW level on the port parity error flag
(PEFA, PEFB). Odd or even parity checking can be selected,
and the parity error flags can be ignored if this feature is not
desired.
Parity status is checked on each input bus according to
the level of the odd/even parity (ODD/EVEN) select input. A
parity error on one or more bytes of a port is reported by a LOW
level on the corresponding port parity error flag (PEFA, PEFB)
output. Port-A bytes are arranged as A0-A8, A9-A17, A18A26, and A27-A35 with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as B0-B8, B9B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. When odd/even parity is
selected, a port parity error flag (PEFA, PEFB) is LOW if any
byte on the port has an odd/even number of LOW levels
applied to the bits.
The four parity trees used to check the A0-A35 inputs are
shared by the mail2 register when parity generation is selected for port-A reads (PGA = HIGH). When a port-A read
from the mail2 register with parity generation is selected with
W/RA LOW, CSA LOW, ENA HIGH, MBA HIGH, and PGA
HIGH, the port-A parity error flag (PEFA) is held HIGH regardless of the levels applied to the A0-A35 inputs. Likewise, the
parity trees used to check the B0-B35 inputs are shared by the
mail1 register when parity generation is selected for port-B
reads (PGB = HIGH). When a port-B read from the mail1
register with parity generation is selected with W/RB LOW,
CSB LOW, ENB HIGH, MBB HIGH, and PGB HIGH, the portB parity error flag (PEFB) is held HIGH regardless of the levels
applied to the B0-B35 inputs.
PARITY GENERATION
A HIGH level on the port-A parity generate select (PGA)
or port-B parity generate select (PGB) enables the IDT723612
to generate parity bits for port reads from a FIFO or mailbox
register. Port-A bytes are arranged as A0-A8, A9-A17, A1826, and A27-A35, with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as B0-B8, B9B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. A write to a FIFO or mail
register stores the levels applied to all thirty-six inputs regardless of the state of the parity generate select (PGA, PGB)
11
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate
a parity bit according to the level on the ODD/EVEN select.
The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the
word is read to the data outputs.
Parity bits for FIFO data are generated after the data is
read from SRAM and before the data is written to the output
register. Therefore, the port-A parity generate select (PGA)
and odd/even parity select (ODD/EVEN) have setup and hold
time constraints to the port-A clock (CLKA) and the port-B
parity generate select (PGB) and ODD/EVEN have setup and
hold-time constraints to the port-B clock (CLKB). These
COMMERCIAL TEMPERATURE RANGE
timing constraints only apply for a rising clock edge used to
read a new word to the FIFO output register.
The circuit used to generate parity for the mail1 data is
shared by the port-B bus (B0-B35) to check parity and the
circuit used to generate parity for the mail2 data is shared by
the port-A bus (A0-A35) to check parity. The shared parity
trees of a port are used to generate parity bits for the data in
a mail register when the port write/read select (W/RA, W/RB)
input is LOW, the port mail select (MBA, MBB) input is HIGH,
chip select (CSA, CSB) is LOW, enable (ENA, ENB) is HIGH,
and port parity generate select (PGA, PGB) is HIGH. Generating parity for mail register data does not change the contents
of the register.
12
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
tRSTH
CLKB
tRSTS
tFSS
tFSH
RST
FS1,FS0
0,1
tWFF
tWFF
FFA
tREF
EFA
tWFF
FFB
tWFF
tREF
EFB
tPAE
AEA
tPAF
AFA
MBF1,
MBF2
AEB
AFB
tRSF
tPAE
tPAF
3136 drw 04
Figure 1. Device Reset Loading the X Register with the Value of Eight
13
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKA
FFA
HIGH
tENH1
tENS1
CSA
tENS1
tENH1
tENS3
tENH3
tENS2
tENH2
W/RA
MBA
tENS2
tENH2
tENS2
tENH2
ENA
tDH
tDS
A0 - A35
W1(1)
W2(1)
No Operation
ODD/
EVEN
PEFA
tPDPE
Valid
tPDPE
Valid
3136 drw 05
Note:
1. Written to FIFO1
Figure 2. Port-A Write Cycle Timing for FIFO1
14
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
FFB
HIGH
tENS1
tENH1
CSB
tENS1
tENH1
tENS3
tENH3
tENS2
tENH2
W/RB
MBB
tENS2
tENH2
tENS2
tENH2
ENB
tDH
tDS
B0 - B35
W1(1)
No Operation
W2(1)
ODD/
EVEN
PEFB
tPDPE
Valid
tPDPE
Valid
3136 drw 06
Note:
1. Written to FIFO2
Figure 3. Port-B Write Cycle Timing for FIFO2
15
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
EFB
HIGH
CSB
W/RB
tENS2
MBB
tENH2
tENS2
tENH2
ENB
tMDV
tA
tEN
B0 - B35
Data(1)
Previous
tPGS
tPGH
tA
(1)
Word 1
tPGS
tENH2
tENS2
No
Operation
tDIS
(1)
Word 2
tPGH
PGB,
ODD/
EVEN
3136 drw 07
Note:
1. Read from FIFO1
Figure 4. Port-B Read Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKA
EFA
HIGH
CSA
W/RA
tENS2
MBA
tENH2
tENS2
tENH2
tENS2
tENH2
ENA
tMDV
A0 - A35
tEN
tA
Previous
tPGS
Data(1)
tPGH
tA
(1)
Word 1
tPGS
No
Operation
tDIS
(1)
Word 2
tPGH
PGA,
ODD/
EVEN
3136 drw 08
Note:
1. Read from FIFO2
Figure 5. Port-A Read Cycle Timing for FIFO2
16
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH tCLKL
CLKA
CSA
LOW
WRA
HIGH tENS3
tENH3
tENS2
tENH2
MBA
ENA
FFA
HIGH tDS
A0 - A35
tDH
W1
(1)
tSKEW1
CLKB
tCLK
tCLKH tCLKL
1
2
tREF
EFB
tREF
FIFO1 Empty
CSB
LOW
W/RB
LOW
MBB
LOW
tENS2
tENH2
ENB
tA
B0 -B35
W1
3136 drw 09
Note:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the
next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the
transition of EFB HIGH may occur one CLKB cycle later than shown.
Figure 6. EFB Flag Timing and First Data Read when FIFO1 is Empty
17
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH tCLKL
CLKB
CSB
LOW
WRB
HIGH tENS3
tENH3
tENS2
tENH2
MBB
ENB
FFB
HIGH tDS
B0 - B35
tDH
W1
(1)
tSKEW1
CLKA
tCLK
tCLKH tCLKL
1
2
tREF
EFA
tREF
FIFO2 Empty
CSA
LOW
W/RA
LOW
MBA
LOW
tENS2
tENH2
ENA
tA
W1
A0 -A35
3136 drw 10
Note:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the
next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the
transition of EFA HIGH may occur one CLKA cycle later than shown.
Figure 7. EFA Flag Timing and First Data Read when FIFO2 is Empty
18
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
W/RB
LOW
MBB
LOW
tENS2
tENH2
ENB
EFB
B0 - B35
HIGH
tA
Previous Word in FIFO1 Output Register
Next Word From FIFO1
(1)
tSKEW1
tCLK
tCLKH
1
CLKA
tCLKL
2
tWFF
tWFF
FFA
FIFO1 Full
CSA
LOW
WR A
HIGH
tENH3
tENS3
MBA
tENS2
tENH2
ENA
tDS
tDH
A0 - A35
To FIFO1
3136 drw 11
Note:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the
next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may
transition HIGH one CLKA cycle later than shown.
Figure 8. FFA Flag Timing and First Available Write when FIFO1 is Full.
19
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
W/RA
LOW
MBA
LOW
tENS2
tENH2
ENA
EFA
A0 - A35
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
(1)
tSKEW1
tCLK
tCLKH
1
CLKB
tCLKL
2
tWFF
tWFF
FFB
FIFO2 Full
CSB
LOW
WRB
HIGH
tENH3
tENS3
MBB
tENS2
tENH2
ENB
tDS
tDH
B0 - B35
To FIFO2
3136 drw 12
Note:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the
next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then FFB may
transition HIGH one CLKB cycle later than shown.
Figure 9. FFB Flag Timing and First Available Write when FIFO2 is Full
20
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
tENS2
tENH2
ENA
(1)
tSKEW2
1
CLKB
2
tPAE
tPAE
AEB
X Word in FIFO1
(X+1) Words in FIFO1
tENS2
tENH2
ENB
3136 drw 13
Notes:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the
next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may
transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
Figure 10. Timing for AEB when FIFO1 is Almost Empty
CLKB
tENS2
tENH2
ENB
(1)
tSKEW2
1
CLKA
2
tPAE
tPAE
AEA
X Words in FIFO2
(X+1) Words in FIFO2
tENS2
tENH2
ENA
3136 drw 14
Notes:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the
next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may
transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 11. Timing for AEA when FIFO2 is Almost Empty
21
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
(1)
tSKEW2
1
CLKA
tENS2
2
tENH2
ENA
tPAF
AFA
[64-(X+1)] Words in FIFO1
tPAF
(64-X) Words in FIFO1
CLKB
tENS2
tENH2
ENB
3136 drw 15
Notes:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the
next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may
transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
Figure 12. Timing for AFA when FIFO1 is Almost Full
(1)
tSKEW2
1
CLKB
tENS2
2
tENH2
ENB
tPAF
AFB
[64-(X+1)] Words in FIFO2
tPAF
(64-X) Words in FIFO2
CLKA
tENS2
tENH2
ENA
3136 drw 16
Notes:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the
next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may
transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 13. Timing for AFB when FIFO2 is Almost Full
22
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
CLKA
COMMERCIAL TEMPERATURE RANGE
tENH1
tENS1
CSA
W/RA
MBA
ENA
tDH
tDS
W1
A0 - A35
CLKB
tPMF
MBF1
tPMF
CSB
W/RB
MBB
tENS2
tENH2
ENB
tEN
tMDV
tDIS
tPMR
W1 (Remains valid in Mail1 Register after read)
B0 - B35
FIFO1 Output Register
3136 drw 17
Note:
1. Port-B parity generation off (PGB = LOW)
Figure 14. Timing for Mail1 Register and MBF1 Flag
23
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
tENH1
tENS1
CSB
W/RB
MBB
ENB
tDH
tDS
W1
B0 - B35
CLKA
tPMF
MBF2
tPMF
CSA
W/RA
MBA
tENS2
tENH2
ENA
tEN
tMDV
tDIS
tPMR
W1 (Remains valid in Mail2 Register after read)
A0 - A35
FIFO2 Output Register
3136 drw 18
Note:
1. Port-A parity generation off (PGA = LOW)
Figure 15. Timing for Mail2 Register and MBF2 Flag
24
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ODD/
EVEN
W/RA
MBA
PGA
PEFA
Valid
tPEPE
tPOPE
tPOPE
Valid
Valid
tPEPE
Valid
3136 drw 19
Note:
1. ENA is HIGH, and CSA is LOW
Figure 16. ODD/EVEN W/RA, MBA, and PGA to PEFA Timing
ODD/
EVEN
W/RB
MBB
PGB
tPOPE
PEFB
Valid
tPEPE
tPOPE
Valid
Valid
tPEPE
Valid
3136 drw 20
Note:
1. ENB is HIGH, and CSB is LOW
Figure 17. ODD/EVEN W/RB, MBB, and PGB to PEFB Timing
25
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ODD/
EVEN
CSA
LOW
W/RA
MBA
PGA
tEN
tPEPB
tMDV
A8, A17,
A26, A35
tPOPB
Generated Parity
tPEPB
Generated Parity
Mail2
Data
Mail2 Data
3136 drw 21
Note:
1. ENA is HIGH
Figure 18. Parity Generation Timing when Reading from Mail2 Register
ODD/
EVEN
CSB
LOW
W/RB
MBB
PGB
tEN
B8, B17,
B26, B35
tPEPB
tMDV
tPOPB
Generated Parity
tPEPB
Generated Parity
Mail1 Data
Mail1
Data
3136 drw 22
Note:
1. ENB is HIGH
Figure 19. Parity Generation Timing when Reading from Mail1 Register
26
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
VCC = 5.5 V
350
f data = 1/2 f s
T A = 25° C
C L = 0 pF
300
I CC(f) – Supply Current – mA
VCC = 5.0 V
250
200
VCC = 4.5 V
150
100
50
0
0
10
20
30
40
50
60
70
80
f s – Clock Frequency – MHz
3136 drw 23
Figure 20
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 20 was taken while simultaneously reading and writing the FIFO on the
IDT723612 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to
consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load.
Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from Figure 28, the maximum power dissipation (PD) of the IDT723612 may be calculated by:
PD = VCC x ICC(f) + ∑(CL x VCC x (VOH - VOL) x fo)
where:
CL
fo
VOH
VOL
=
=
=
=
output capacitance load
switching frequency of an output
output HIGH level voltage
output LOW level voltage
When no reads or writes are occurring on the IDT723612, the power dissipated by a single clock (CLKA or CLKB)
input running at frequency fS is calculated by:
PT = VCC x fS x 0.290 mA/MHz
27
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5V
1.1 k Ω
From Output
Under Test
30 pF
680 Ω
(1)
LOAD CIRCUIT
3V
Timing
Input
1.5 V
High-Level
Input
GND
tS
1.5 V
th
3V
1.5 V
1.5 V
GND
tW
3V
Data,
Enable
Input
Low-Level
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
GND
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5 V
tPLZ
1.5 V
tPZL
GND
≈3 V
1.5 V
Low-Level
Output
tPZH
1.5 V
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Input
VOL
VOH
High-Level
Output
3V
1.5 V
≈ OV
3V
1.5 V
1.5 V
tPD
tPD
GND
VOH
In-Phase
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3136 drw 24
Note:
1. Includes probe and jig capacitance
Figure 21. Load Circuit and Voltage Waveforms
28
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
BLANK
Commercial (0°C to +70°C)
PF
PQF
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
15
20
30
L
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Low Power
723612 64 x 36 x 2 SyncBiFIFO
3136 drw 25
29