Preliminary PT4456 PLL-based FSK Transmitter IC DESCRIPTION FEATURES PT4456 is a high performance FSK transmitter for the Remote Keyless Entry (RKE) systems. It consists of a power amplifier, one-shot circuit and phase-locked loop with internal voltage controlled oscillator and loop filter. The one-shot circuit control the phase-locked loop and power amplifier to have fast start-up time in operation. Highly integrated FSK transmitter High output power, 3 V /+11 dBm / 17 mA Low supply voltage, 2.2 V to 3.6 V operation range Low external component cost. PLL-based transmitter with frequency range from 300MHz to 450MHz On-chip one-shot circuit SOT23-6 package APPLICATIONS Keyless entry systems Remote control systems Garage door openers Alarm systems Security systems Wireless sensors BLOCK DIAGRAM XIN VDD DIN 6 5 4 Vreg Oneshot P L L PA 1 2 3 XOUT VSS PAOUT Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145, Taiwan PT4456 APPLICATION CIRCUIT X1 C1 C2 R5 VDD C3 R3 C7 XOUT 2 VSS L1 L2 C6 C5 C4 XIN PT4456 6 VDD 5 DIN 4 VDD 1 R4 3 PAOUT R1 DIN R2 BILL OF MATERIALS Part X1 R1 R2 R3 R4 R5 C1 C2 C3 C4 C5 C6 C7 L1 L2 Value 315MHz 9.84175M 10K 100K 0 10 560K 10p 10p 1μ 220p 8.2p 18p 2.2μ 180n 33n 433.92MHz 13.558M 10K 100K 0 10 560K 10p 10p 1μ 220p 4.7p 10p 2.2μ 180n 27n Unit Notes Hz Ω Ω Ω Ω Ω F F F F F F F H H 3,4,5 3 1,5 1,5 2 2 2 Notes: 1. C1/C2 can be used to trim the transmitted signal frequency for matching the specified value. 2. L2/C5/C6 value will depend on PCB layout. 3. The recommend maximum ESR value of X1 is 40Ω. To populate R5 over XIN will help to maintain good oscillation in high X1 ESR. 4. For FSK application to have adequate frequency deviation, and accurate carrier frequency, the crystal resonator frequency will be lower than the specified value. The recommended crystal resonator frequency is 9.84175MHz and 13.558MHz. 5. For higher X1 ESR, load capacitor C2 can be reduced or removed to maintain good oscillation. In narrowband application with accurate frequency requirement, trimming the C1 capacitor or change the crystal resonator frequency is suggested. 6. The PCB layout is scaled to get good reading. The actual PCB size is about 1.1x1.3 cm PRE1.1 2 September 2014 PT4456 ORDER INFORMATION Valid Part Number Package Type Top Code PT4456 6 Pins, SOT23 PT4456 PIN CONFIGURATION XOUT 1 VSS 2 PAOUT 3 PT4456 6 XIN 5 VDD 4 DIN PIN DESCRIPTION PRE1.1 Pin Name I/O Description XOUT VSS PAOUT DIN VDD XIN O G O I P I Oscillator output Ground connection Power amplifier output Data input Power supply Oscillator input 3 Pin No. 1 2 3 4 5 6 September 2014 PT4456 FUNCTION DESCRIPTION PA OUTPUT MATCHING The PA output is an open-drain structure. Its output connects a large choke inductor to supply voltage and follows by a DC block capacitor. After the DC block capacitor, a C-L-C -type matching network is used to tune with the antenna impedance. The inductor and capacitor values may be different from the suggestion value depending on PCB material, PCB thickness, ground configuration, and the layout traces length. For the open-drain structure in PA, the HBM (Human Body Mode) and MM (Machine Mode) ESD strength is 4KV and 400V. REFERENCE OSCILLATOR For a quartz crystal to oscillate in the specified frequency, it should work with vendor provided load capacitor value, called CL . The load capacitor is about 8.2pF to 12pF in general. In PT4456, the Pierce type crystal oscillator is used, and the shunt capacitor over XIN and XOUT is in series together equivalently. The shunt capacitor should be placed as 2x CL to oscillate with specified frequency. The temperature coefficient of quartz crystal will cause the VCO output frequency drift in high/low temperature range. With a fixed divided-by-32 PLL, the fREFOSC = fTX / 32. The following table list fREFOSC for some common transmit frequencies Transmit Frequency fTX Reference Oscillator Frequency fREFOSC 315 MHz 433.92 MHz 9.84175 MHz 13.558 MHz The recommend maximum ESR value of reference oscillator is 40Ω. PHASE-LOCKED LOOP (PLL) The PT4456 own a fixed divided-by-32 PLL to generate the transmitter signal. The PLL consists of the voltage-controlled oscillator (VCO), crystal oscillator, asynchronous ÷ 32 divider, charge pump, loop filter and phase-frequency detector (PFD). All these circuits are integrated on-chip. The PFD compares two signals and produces an error signal which is proportional to the difference between the input phases. The error signal passes through a loop filter with an approximately 180 KHz bandwidth, and is used to control the VCO. A frequency divider placed after the VCO and it will feedback the divided signal to PFD. In the final the VCO will get locked to reference signal as fVCO = fREFOSC * 32. The block diagram below shows the basic elements of the PLL. PFD CP LF XOSC DIV32 VCO The PLL chain circuit is supplied by internal voltage regulator to ease the PA pulling and crystal spur issue PRE1.1 4 September 2014 PT4456 ONE-SHOT CIRCUIT AND POWER-DOWN CONTROL During the signal transmission, the crystal oscillator start-up time will limit its wake-up time to work. A one-shoot circuit is used to solve this problem by turning on/off the power amplifier and PLL circuit separately. When apply “HIGH” and “LOW” signal to DIN, it will pull the VCO to higher or lower frequency. The CE pin is saved for power-down control. DIN stay in “LOW” about 50ms will put chip into power-down mode and each state change in DIN will re-trigger the timer. To calculate the re-triggerable one-shot delay time, it can be counted as 688128 / fREFOSC . For fREFOSC = 9.84175MHz and 13.558MHz, the delay time is about 69.9ms and 50.7ms. ANTENNA DESIGN AND PCB LAYOUT CONSIDERATION For a λ/4 dipole antenna and operating frequency, f (in MHz), the required antenna length, L (in cm), may be calculated by using the formula 7132 L f For example, if the frequency is 315 MHz, then the length of a λ/4 antenna is 22.6 cm. If the calculated antenna length is too long for the application, then it may be reduced to λ/8, λ/16, etc. without degrading the input return loss. Usually, when designing a λ/4 dipole antenna, it is better to use a single conductive wire (diameter about 0.8 mm to 1.6 mm) rather than a multiple core wire. If the antenna is printed on the PCB, ensure there is neither any component nor ground plane underneath the antenna on the backside of PCB. For an FR4 PCB (εr = 4.7) and a strip-width of 30 mil, the length of the antenna, L (in cm), is calculated by 10 c where “c” is the speed of light (3 x10 cm/s) L 4 f r Proper PCB layout is extremely critical in achieving good RF performance. At the very least, using a two-layer PCB is strongly recommended, so that one layer may incorporate a continuous ground plane. A large number of via holes should connect the ground plane areas between the top and bottom layers. Careful consideration must also be paid to the supply power and ground at the board level. The larger ground area plane should be placed as close as possible to all the VSS pins. Grounding the metal case of quartz crystal and isolate the XIN/XOUT trace to other can suppress the crystal spur signal over PA output. PRE1.1 5 September 2014 PT4456 ABSOLUTE MAXIMUM RATINGS (VSS=0V) Parameter Supply Voltage Range I/O Voltage Operating Temperature Range Storage Temperature Range Symbol VDD VI/O TA TSTG Min. -0.3 -0.3 -40 -40 Max. 5 5 +85 +150 Unit V V °C °C RECOMMENDED OPERATING CONDITIONS (VSS=0V) Parameter Supply Voltage Range Operating Temperature Range Symbol VDD TA Min. -0.3 -40 Max. 3.6 +85 Unit V °C ELECTRICAL CHARACTERISTICS Nominal conditions: VDD = 3.0 V, VSS = 0 V, TA = +27°C. Parameter Symbol Conditions General Characteristics VDD Supply Voltage DIN=High(CW mode); POUT =12dBm, fRF = 315MHz (Note) IDD Operating Current DIN=High(CW mode); POUT =10dBm, fRF = 434MHz Istandby DIN=Low; TDELAY>50ms Standby Current RF fRF Frequency Range fRF = 315MHz (Note) Pout Power Amplifier Output Power fRF = 434MHz PNOISE Phase Noise 315MHz, 10KHz offset (Note) PHARM Harmonics 2x/3x fRF fRF = 315MHz PSPUR Crystal Spur fRF = 434MHz Data Input and One-shot DRATE Data Rate TON Crystal Oscillator Start-up Time TDELAY One-shot Delay Time Frequency Deviation FDEV FSK mode, C1 C2=10pF Min. Typ. Max. Unit 2.2 3.0 3.6 V 17 mA 19 mA 1 A 450 MHz dBm dBm dBc/Hz dBc dBc dBc 2 1 10 110 150 Kbps ms ms KHz 300 11 10 -75 -40 -40 -40 0.5 50 Note: Depend on power amplifier output matching PRE1.1 6 September 2014 PT4456 PACKAGE INFORMATION 6 Pins, SOT23-6 Symbol Min. Nom. Max A A1 A2 0.00 0.90 1.15 1.45 0.15 1.30 b c D E E1 e e1 0.30 0.080 0.130 2.90 BSC 2.80 BSC 1.60 BSC 0.95 BSC 1.90 BSC 0.50 0.220 L 0° - 8° 0.30 0.45 0.60 Notes; 1. Refer to JEDEC MO-178 2. All dimensions are in millimeter PRE1.1 7 September 2014 PT4456 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian Dist., New Taipei City 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw PRE1.1 8 September 2014