PT4302 Ultra-Low Power OOK/ASK Receiver DESCRIPTION FEATURES The PT4302 is an ultra-low power OOK/ASK super heterodyne receiver for the 315/434 MHz frequency bands. It offers a high level of integration and requires only few external components. The PT4302 consists of a low-noise amplifier (LNA), a down-conversion mixer, an on-chip phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) and loop filter, an OOK/ASK demodulator, a data filter, a data slicing comparator and an on-chip regulator. • Ultra-low power consumption: 2.7 mA for fully operation (315 MHz) • Few external components • Excellent Sensitivity of the order of –111 dBm (peak ASK signal level) • Supply voltage range from 2.4 V to 5.5 V • 250 MHz to 500 MHz frequency range • Data rate up to 10 Kb/s The PT4302 is available in 16-pin SSOP package and is specified over the extended temperature range (-40 to +85°C). APPLICATIONS • • • • Automotive Remote Keyless Entry (RKE) Remote Control Garage door and gate openers Suitable for circuit applications that meet either the European ETSI-300-220 or the North American FCC (Part 15) regulatory standards BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan For:Natertech PT4302 APPLICATION CIRCUIT BILL OF MATERIALS Part Value Unit Description 315 MHz 433.92 MHz L1 82 n 47 n H L2 39 n 27 n H Antenna ESD protection, coil inductor (option). Antenna input matching, coil inductor. C1 1.8 p 1.0 p F Antenna input matching. C2, C3, C4 100 n 100 n F Power supply de-coupling capacitor. C5 470 n 470 n F C6 220 p 220 p F R1 10 10 Ω CTH, affect coding type and start-up time. Depend on crystal oscillator vendor, for frequency fine tuning. Power supply de-coupling resistor (option). R2, R3, R4, R5 10 K 10 K Ω MCU interface resistor (option). R6 8.2 M 8.2 M Ω For reducing data output noise (option). F1 10.7 10.7 MHz Band-pass filter. X1 9.509 13.226 MHz Reference crystal oscillator. U1 PT4302 IC PT4302 IC U1 Receiver chip. Notes: 1. L1 and C1 are the components for input matching network. They may have to be adjusted with different PCB layout and antenna requirement. 2. The value of C5 depends upon the data rate and coding pattern. 3. F1 is the 10.7 MHz ceramic filter. The recommended part number is Murata SFELA10M7HA00-B0. 4. The “option” components are based on application requirements. V1.1 2 For:Natertech February 2010 PT4302 ORDER INFORMATION Valid Part Number PT4302-X Package Type 16 Pins, SSOP, 150 mil Top Code PT4302-X PIN CONFIGURATION PIN DESCRIPTION Pin Name VSSLO VSSRF ANT VRF MIXOUT VBB IFIN VDD5 VSSBB SELB SELA CE DO CTH VLO REFOSC V1.1 I/O G G I P O P I P G I I I O I/O P I Description Ground for LO portion Ground for RF portion RF input connected to antenna by a matching network Supply voltage for RF portion Mixer IF output Supply voltage for baseband chain IF stage input 5 V voltage regulator input Ground for baseband chain Data filter bandwidth select (Pin B) Data filter bandwidth select (Pin A) Chip enable pin. Pull high to enable the chip Data output Connect to data slicing threshold capacitor Supply voltage for LO portion Reference oscillator input pin 3 For:Natertech Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 February 2010 PT4302 FUNCTION DESCRIPTION POWER SUPPLY PT4302 provides an internal voltage regulator to the whole receiver blocks, so that all the supply voltage pins, except VDD5, have to be connected together and put the bypass capacitors against these pins as possible. Only leave the VDD5 pin (pin 8) to connect with the external supply voltage, and incorporate with series-R, shunt-C filtering. The PT4302 chip can operate in the supply voltage range from 2.4 V to 5.5 V. RF FRONT-END The RF front-end of the receiver part is a superheterodyne configuration that converts the input radio frequency (RF) signal into an intermediate frequency (IF) signal. The used IF in PT4302 chip is 10.7 MHz. According to the block diagram, the RF front-end consists of a LNA and a down-conversion mixer, and the local oscillator (LO) signal for the mixer is generated by the PLL frequency synthesizer. As the receiver constitutes a superheterodyne architecture, there is no inherent suppression of the image frequency. It depends upon the particular application and the system's environment conditions whether an RF front-end filter should be added or not. If image rejection or good blocking immunity is relevant system parameter, a band-pass filter must be placed in front of the LNA. This filter can be a SAW (surface acoustic wave) or LC-based filter (e.g. helix type). The RF front-end provides the good performance of low noise which is smaller than 5 dB, high voltage conversion gain of over 40 dB, and excellent reversion isolation. The preferred LO rejection type is low side for saving the power consumption. The IF output impedance of mixer is about 330 Ohm in order to match the IF channel selection filter. The ANT pin can be matched to 50 Ohm with an L-type circuit. That is, a shunt inductor from the RF input to ground and another in series from the RF input to the antenna pin. Inductor and capacitor values may be different from table depending on PCB material, PCB thickness, ground configuration, and how long the traces are in the layout. Example of the input matching network is shown in the following figure and the input impedance of the PT4302 for 315/434 MHz frequency bands are listed in the right-hand side table. The component values given in the BOM for the application circuit shown in Page 2 are nominal values only. RF Frequency fRF 315 MHz 340 MHz 390 MHz 433.92 MHz ANT Input Impedance (Pin 3) 1.328 － j213.91 1.602 － j195.74 2.469 － j170.92 2.086 － j152.17 ANTENNA PART ESD PROTECTION PT4302 IC provides the ESD level (Human Body Mode) better than 3 KV at ANT pin. However, the higher ESD protection level would be required in system level for some applications. The extra ESD protection level could rely on the external components. Changing L1 from SMD type to coil type could enhance ESD protection level of around 1 KV, and adding a shunt coil inductor L2 in the front of C1 could gain more ESD protection enhancement. RF Frequency fRF 315 MHz 340 MHz 390 MHz 433.92 MHz V1.1 4 For:Natertech Suggestion value of L2 39nH 39nH 33nH 27nH February 2010 PT4302 REFERENCE OSCILLATOR All timing and tuning operations on the PT4302 are derived from the internal one-pin Colpitts reference oscillator. Timing and tuning is controlled through the REFOSC pin in one of two ways: 1. Connect a crystal 2. Drive this pin with an external timing signal When a crystal is used, the minimum oscillation voltage swing is 300 mVPP. If using an externally applied signal it should be AC-coupled and limited to the operating range of 0.3 VPP to 1.5 VPP. As with any superheterodyne receiver, the mixing between the internal LO (local oscillator) frequency fLO and the incoming transmit frequency fTX ideally must equal the IF center frequency (10.7 MHz). The following equation may be used to compute the appropriate fLO for a given fTX fLO = fTX ± 10.7 Frequencies fTX and fLO are in MHz. Note that two values of fLO exist for any given fTX, distinguished as “high-side mixing” and “low-side mixing”. High-side mixing results in an image frequency above the frequency of interest and low-side mixing results in a frequency below. We recommend to use low-side mixing for saving the receiver power. After choosing one of the two acceptable values of fLO, to compute the reference oscillator frequency fREFOSC fREFOSC = fLO / 32 = (fTX － 10.7) / 32 The following table identifies fREFOSC for some common transmit frequencies when the PT4302 chip is operated with low-side mixing. Transmit Frequency fTX 315 MHz 340 MHz 390 MHz 433.92 MHz Reference Oscillator Frequency fREFOSC 9.509 MHz 10.29 MHz 11.853 MHz 13.226 MHz The reference oscillator frequency is close to 10.7 MHz intermediate frequency. It is necessary to avoid signal trace coupling between the reference oscillator and intermediate frequency. Otherwise, it would degrade receiver performance. PHASE-LOCKED LOOP (PLL) The PT4302 utilizes a fixed divided-by-32 PLL to generate the receiver LO. The PLL consists of the voltage-controlled oscillator (VCO), crystal oscillator, asynchronous ÷32 divider, charge pump, loop filter and phase-frequency detector (PFD). All these components are integrated on-chip. The PFD compares two signals and produces an error signal which is proportional to the difference between the input phases. The error signal passes through a loop filter with an approximately 200 KHz bandwidth, and is used to control the VCO which generates an LO frequency. The VCO frequency is also fed through a frequency divider back to one input of the PFD, producing a feedback loop. Thus, the output is locked to the reference frequency at the other input, which is derived from a crystal oscillator (i.e. fREFOSC = (fRF – fIF) / 32). The block diagram below shows the basic elements of the PLL. V1.1 5 For:Natertech February 2010 PT4302 ASK DEMODULATOR The OOK/ASK demodulation is done by comparing the RSSI signal level. The RSSI signal is decimated and filtered in the data filter and the data decision is then completed by the slicing comparator. The RSSI is implemented as a successive compression log amplifier following by the external IF channel filtering. The log amplifier achieves ±3 dB log linearity, and the RSSI output level has the dynamic range of around 80 dB and the slope of approximately 12 mV /dB. The IFIN pin presents a differential 330 Ohm load to provide a good matching for the off-chip ceramic filter. Data Filter The data filter (post-demodulator filter) is utilized here to remove other unwanted spurious signals after the OOK/ASK demodulator, which is implemented as a 2nd-order low-pass Sallen-Key filter. The data filter bandwidth (BWDF) must be selected according to the applications, and should be set according to equation BWDF = 0.65 / Shortest pulse-width The input pins of SELA and SELB control the data filter bandwidth in four binary steps, see the table below. It should be noted that the values indicated in this table are nominal values. The filter bandwidth scales linearly with frequency so the exact value will depend on the operating frequency. SELA SELB 1 1 0 0 1 0 1 0 Data Filter Bandwidth BWDF fRF = 315 MHz fRF = 433.92 MHz 900 Hz 1250 Hz 1800 Hz 2500 Hz 3600 Hz 5000 Hz 7200 Hz 10000 Hz DATA SLICER The purpose of the data slicer is to take the analog output of the data filter and convert it to a digital signal. Extraction of the DC value of the demodulated signal for purposes of logic-level data slicing is accomplished using the external threshold capacitor CTH and the on-chip resistor RTH, shown in the block diagram. Slicing level time constant values vary somewhat with decoder type, data pattern, and data rate, but typically values range from 2 ms to 20 ms. Optimization of the value of CTH is required to maximize range. The first step in the process is selection of a data-slicing-level time constant. This selection is strongly dependent on system issues including system decode response time and data code structure. The effective resistance of RTH is 25 KΩ and τ of 3x the period of longest “LOW” or “HIGH” bit stream is recommended. Assuming that a slicing level time constant τ has been established, capacitor CTH may be computed using equation CTH = τ / RTH A standard ±20% X7R ceramic capacitor is generally sufficient. DATA SQUELCHING During quiet periods (no signal) the data output (DO pin) transitions randomly with noise. Most decoders can discriminate between this random noise and actual data, but for some system it does present a problem. There are two possible approaches to reducing this output noise: 1. Analog squelch to raise the demodulator threshold. 2. Output filter to filter the (high frequency) noise glitches on the data output pin. V1.1 6 For:Natertech February 2010 PT4302 The simplest solution is add analog squelch by introducing a small offset, or squelch voltage, on the CTH pin so that noise does not trigger the internal slicer. Usually 20 mV to 30 mV is sufficient, and may be achieved by connecting a several mega-ohm resistor from the CTH pin to either VSS or internal supply voltage, depending on the desired offset polarity. The squelch offset requirement does not change as the local noise strength changes from installation to installation. Introducing squelch will reduce sensitivity and also reduce the receiving dynamic range. Only introduce an amount of offset sufficient to quiet the output. Typical squelch resistor values range from 5.1 MΩ to 8.2 MΩ. The circuit drawn below shows an application example of analog squelch, where R6 is the squelch resistor. The demodulated data then enters into a quasi-mute state as the RF input signal becomes very small (when there is no RF signal received or the RF signal is too small) and the DO output remains mostly at a logic “LOW” level. If the environment is very noisy, the R6 value may be reduced to achieve better immunity against noise, but at the cost of less sensitivity. SENSITIVITY AND SELECTIVITY In digital radio systems, sensitivity is often defined as the lowest signal level at the receiver input that will achieve a specified bit error ratio (BER) at the output. The sensitivity of the PT4302 receiver, when used in the 315 MHz application, is typically –112 dBm (ASK modulated with 2 Kb/s, 50% duty cycle square wave) to achieve a 0.1% BER. The input was matched for a 50 Ω signal source. At 433.92 MHz, –111 dBm sensitivity is typically achievable. The selectivity is governed by the response of the receiver front-end circuitry, the channel filter (off-chip 10.7 MHz IF filter), and the data filter. Note the IF filter provides not only channel selectivity but also the interference rejection. Within the pass band of the receiver, no rejection for interfering signals is provided. POWER-DOWN CONTROL The chip enable (CE) pin controls the power on/off behavior of the PT4302. Connecting CE to “HIGH” sets the PT4302 to its normal operation mode; connecting CE to “LOW” sets the PT4302 to standby mode. The chip consumption current will be lower than 1 μA in standby mode. Once enabled, the PT4302 requires < 10 ms to recover received data with minimum received RF input level. The following figure exhibits the system start-up time in the conditions of Temp=27ºC, fRF=315 MHz, PRF=–110 dBm, CTH=100 nF and DRATE=2 Kb/s. The CE pin is triggered every 200 mS. V1.1 7 For:Natertech February 2010 PT4302 ANTENNA DESIGN For a λ/4 dipole antenna and operating frequency, f (in MHz), the required antenna length, L (in cm), may be calculated by using the formula L= 7132 f For example, if the frequency is 315 MHz, then the length of a λ/4 antenna is 22.6 cm. If the calculated antenna length is too long for the application, then it may be reduced to λ/8, λ/16, etc. without degrading the input return loss. However, the RF input matching circuit may need to be re-optimized. Note that in general, the shorter the antenna, the worse the receiver sensitivity and the shorter the detection distance. Usually, when designing a λ/4 dipole antenna, it is better to use a single conductive wire (diameter about 0.8 mm to 1.6 mm) rather than a multiple core wire. If the antenna is printed on the PCB, ensure there is neither any component nor ground plane underneath the antenna on the backside of PCB. For an FR4 PCB (εr = 4.7) and a strip-width of 30 mil, the length of the antenna, L (in cm), is calculated by L= c 4× f × εr where “c” is the speed of light (3 x1010 cm/s) PCB LAYOUT CONSIDERATION Proper PCB layout is extremely critical in achieving good RF performance. At the very least, using a two-layer PCB is strongly recommended, so that one layer may incorporate a continuous ground plane. A large number of via holes should connect the ground plane areas between the top and bottom layers. Note that if the PCB design incorporates a printed loop antenna, there should be no ground plane beneath the antenna. Careful consideration must also be paid to the supply power and ground at the board level. The larger ground area plane should be placed as close as possible to all the VSS pins. To reduce supply bus noise coupling, the power supply trace should be incorporate series-R, shunt-C filtering as shown below. V1.1 8 For:Natertech February 2010 PT4302 APPLICATION EXAMPLE 315 MHz Receiver/Decoder Application The following schematic illustrates a typical application at 315MHz frequency band for the PT4302 receiver IC. This receiver operates continuously (not duty cycled) in the enable (active) mode, and features 6-bit address decoding. The value of C5 may need to be increased if the idle time is too long between each data frame. Changes from the 1 kb/s data rate may require a change in the value of R2. A bill of materials accompanies the schematic. U1 PT4302 1 C1 1.8 pF C2 100 nF L1 82 nH F1 2 3 4 X1 9.509 MHz 6-bit address U2 PT2272 REFOSC 16 VSSRF VLO 15 2 ANT CTH 14 3 VRF DO 13 4 CE 12 5 VSSLO 1 C4 100 nF C5 660 nF VCC 18 A1 VT 17 A2 OSC1 16 A3 OSC2 15 A4 DIN 14 A0 5 MIXOUT 6 VBB SELA 11 6 A5 A11 13 7 IFIN SELB 10 7 A6 A10 12 VSSBB 9 8 A7 A9 11 9 VSS A8 10 8 VDD5 5V R3 1K D1 R2 680 K C3 4.7 uF V1.1 Part Part Number Manufacturer Description U1 PT4302-X Princeton Technology Corp. UHF OOK/ASK receiver U2 PT2272 Princeton Technology Corp. Remote control decoder F1 SFELA10M7HA00-B0 Murata L1 - - 82 nH SMD inductor C1 - - 1.8 pF SMD capacitor C2 - - 100 nF SMD capacitor C3 - - 4.7 μF SMD capacitor C4 - - 100 nF SMD capacitor C5 - - 660 nF SMD capacitor R1 - - 1 KΩ SMD resistor with 5% tolerance R2 - - 680 KΩ SMD resistor with 5% tolerance X1 - - 9.509 MHz crystal with maximum 80 Ω ESR D1 - - Red LED 10.7 MHz ceramic filter with 180 KHz BW 9 For:Natertech February 2010 PT4302 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Range Analog I/O Voltage Digital I/O Voltage Operating Temperature Range Storage Temperature Range Symbol Min. Max. Unit VDD5 – – TA TSTG -0.3 -0.3 -0.3 -40 -55 6 3 6 +85 +125 V V V °C °C PACKAGE THERMAL CHARACTERISTIC Parameter From Chip Conjunction Dissipation to External Environment From Chip Conjunction Dissipation to Package Surface V1.1 Symbol Condition Rja Rjc TA=27°C Min. Typ. Max. – 37.15 – – 1 1.8 Unit °C/W 10 For:Natertech February 2010 PT4302 ELECTRICAL CHARACTERISTICS Nominal conditions: VDD5 = 5.0 V, VSS = 0 V, CE = “High”, TA = +27°C, fRF= 315 MHz, fREFOSC = 9.509 MHz. Parameter Symbol Conditions Min. Typ. Max. General Characteristics Connect the supply voltage 2.4 5.0 5.5 Supply Voltage VDD5 to VDD5 pin only – 2.7 3.0 fRF=315 MHz Current Consumption IDD5 fRF=434 MHz – 2.9 3.2 Standby Current ISTBY CE=”Low” – – 1 Operating Frequency Range fRF 250 – 500 Maximum Receiver Input Level PRF,MAX -20 -15 – ASK2, DRate = 2 Kb/s, – -112 -109 Peak power level @ 315 MHz OOK, DRate = 2 Kb/s, – -106 -103 Peak power level @ 315 MHz 1 Sensitivity SIN 2 ASK , DRate = 2 Kb/s, – -111 -108 Peak power level @ 434 MHz OOK, DRate = 2 Kb/s, – -105 -102 Peak power level @ 434 MHz Data Rate DRATE – 2 10 LO Leakage LLO Measured at antenna input – – -80 System Start-Up Time TSTUP RF input power = -60 dBm – 5 8 RF Front-End 40 43 46 Matched to 50 Ω @ 315 MHz Voltage Conversion Gain GVRF 39 42 45 Matched to 50 Ω @ 434 MHz – 5.7 6.3 Matched to 50 Ω @ 315 MHz Noise Figure NFRF – 6.1 6.7 Matched to 50 Ω @ 434 MHz Mixer Output Impedance ZOUT,MIXER Measured at MIXOUT pin 300 330 360 IF Section IF Frequency fIF – 10.7 – Depends on the external IF Bandwidth BWIF – 180 – ceramic filter IF Input Impedance ZIN,IF 300 330 360 RSSI Slope SLRSSI 9.5 11.5 13.5 Demodulator SELA = SELB = ”High” – 0.9 – SELA = ”High”; SELB = ”Low” – 1.8 – Post-Demodulator Filter BWDF Bandwidth SELA = ”Low”; SELB = ”High” – 3.6 – SELA = SELB = ”Low” – 7.2 – ±100 CTH Leakage Current IZCTH TA = +85°C – – Phase-Locked Loop Reference Frequency fREFOSC 7 – 16 Reference Signal Voltage Swing VREF Peak-to-peak voltage (VPP) 0.3 – 1.5 VCO Frequency Range fVCO 220 – 550 Divider Ratio DIV – 32 – Digital/Control Interface Input-High Voltage VIN,High CE, SELA, SELB pins 0.8 – – Input-Low Voltage VIN,Low CE, SELA, SELB pins – – 0.2 Output Current IOUT DO pin, push-pull – 20 – Output-High Voltage VOUT,High DO pin, IOUT = -1 μA 0.9 – – Output-Low Voltage VOUT,Low DO pin, IOUT = +1 μA – – 0.1 Output Rise/Fall Times tR/ tF DO pin, CLOAD = 15 pF – 10 – Notes: 1. BER = 1e-3 2. AM 99% with square-wave modulation V1.1 11 For:Natertech Unit V mA μA MHz dBm dBm dBm Kb/s dBm ms dB dB Ω MHz KHz Ω mV/dB KHz nA MHz V MHz – VDD5 VDD5 μA VDD5 VDD5 μs February 2010 PT4302 Figure 1. Supply Current vs. Supply Voltage Figure 2. Voltage Regulator Characteristic Figure 3. Current Consumption vs. RF Frequency Figure 4. Current Consumption vs. Temperature Figure 5. Smith Plot of ANT Figure 6. Sensitivity vs. Temperature Figure 7. Selectivity Response for fRF = 315 MHz Figure 8. Selectivity Response for fRF = 434 MHz V1.1 12 For:Natertech February 2010 PT4302 TEST BOARD LAYOUT <Top Side> <Bottom Side> V1.1 13 For:Natertech February 2010 PT4302 PACKAGE INFORMATION 16 Pins, SSOP Symbol A A1 A2 b C D E E1 e L L1 y Min. 1.34 0.10 1.24 0.20 0.10 4.80 5.79 3.81 0.38 Max. 1.75 0.25 1.52 0.30 0.25 5.00 6.19 3.98 1.27 - Nom. 1.60 0.25 5.99 3.91 0.63 0.041REF - 0º - θ 8º 0.10 Notes: 1. Refer to JEDEC MO-137. 2. Unit: mm V1.1 14 For:Natertech February 2010 PT4302 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.1 15 For:Natertech February 2010