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PT4330
Low Power ISM Band FM/FSK Receiver
DESCRIPTION
The PT4330 is a low power 315/433/868/915MHz
FM/FSK receiver IC which is suitable for use in the
North American 315/915MHz and the European
433/868MHz ISM bands. The PT4330 chip consists of
a low-noise amplifier (LNA), a down-conversion mixer,
a 10.7MHz intermediate frequency limiting amplifier
stage with received-signal-strength indicator (RSSI), a
quadrature demodulator, and a selectable audio
amplifier/slicing comparator. It also integrates a VCO
with fixed ÷ 64 prescaler, phase/frequency detector,
and
reference
oscillator
forming
complete
phase-locked loop.
The PT4330 is available in 32-pin TQFP package, and
is specified over the extended temperature range
from –10°C to +70°C.
FEATURES
• Supply voltage range from 2.4V to 3.6V
• Low power consumption of 7.5mA for fully
operation at 915MHz
• Excellent FSK sensitivity of the order of –100dBm
(180KHz channel bandwidth and 0.1% BER)
• Reduced peripheral components
• Fixed RSSI response with 64dB dynamic range in
both FM and FSK modes
• Receiver enable pin for power saving (1μA current
consumption in stand-by mode)
• TQFP 32L package (5mm x 5mm)
APPLICATIONS
• Wireless mouse / joystick
• Wireless voice transmission
• Wireless car alarm system
BLOCK DIAGRAM
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT4330
APPLICATION CIRCUIT
VDD
R7
C24
C12
C23
R8
R3
X1
VDD
C22
C21
C13
C11 C10
L4
R2
D1
C14
VDD
R4
C9
L1
VDD
L2
C18
30
29
28
27
26
25
PLL
QVSS
QVDD
RESP
RESN
1
BVDD
2
LNI
QUAD
24
IF2O
23
C25
3
LVSS
4
FMOUT
22
LNO
RSSI
21
5
BVSS
MUTE
20
6
MXI
AVDD
19
7
AVSS
IF2DECN
18
8
MXO
IF2DECP
17
D2
C8
C6
C7
IF1DECN
IF1O
VERFIF
AVSS
IF2I
F1
IF1DECP
R9
IF1P
R6
IF1IN
R5
C17
C3
31
XI
C2
R1
32
XO
U1
C15
EN
C16
C1
L3
9
10
11
12
13
14
15
16
C20
VDD
C19
C4
C5
F2
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September 2011
PT4330
BILL OF MATERIALS
Value
Part
Unit
315MHz
434MHz
868MHz
915MHz
C1
3.9p
1.5p
1.5p
1.0p
F
C2
33p
22p
18p
15p
F
C3
4.7p
3.9p
1.8p
1.5p
F
―
―
―
F
10n
10n
10n
F
C4
C4/C5/C8
C6
Note1
10n
10n
10n
10n
10n
F
180p
4.7p
180p
180p
F
C9
180p
8.2p
3.3p
3.9p
F
C10
3.3n
3.3n
3.3n
3.3n
F
47n
47n
47n
47n
F
―
―
―
―
F
C13/C14
39p
39p
39p
39p
F
C15/C17/C19/C21/C23
10n
10n
10n
10n
F
C16/C18/C20/C22/C24
47p
47p
27p
22p
F
L1
33n
39n
10n
10n
H
L2
47n
68n
12n
8.2n
H
L3/L4
27n
18n
4.7n
3.3n
H
R1
5.6K
5.6K
5.6K
5.6K
Ω
R2
10K
10K
10K
10K
Ω
R3
2.7K
2.7K
2.7K
2.7K
Ω
C7
C11
C12/C25
Note1
R4/R5/R6/ R7
10
10
10
10
Ω
R8
27
27
27
27
Ω
R9
560
—
—
—
Ω
F1/F2
Note2
X1 (crystal)
D1
Note3
D2
Note4
10.7MHz Ceramic Filter
—
4.755
6.613
13.41
14.15
MHz
BB833
BB833
SMV1233
SMV1233
—
10.7MHz FM Discriminator
—
PT4330 IC
—
U1
Notes:
1. C6 (RSSI bypassing capacitor), C12 (crystal trimming capacitor) and C25 (quadrature detector trimming capacitor) are not the necessary
components for practical applications. Customers can consider to use or to tune these components by their applications.
2. F1 is the 10.7MHz ceramic filter. The recommended part number is Murata SFELA10M7HA00-B0.
3. D1 is varactor. The recommended part number is Alpha SMV1133-011
4. D2 is 10.7MHz FM Discriminator. The recommended part number is Murata CDALA10M7GA001-B0.
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September 2011
PT4330
ORDER INFORMATION
Valid Part Number
PT4330-TQ
Package Type
32 Pins, TQFP
Top Code
PT4330-TQ
V1.0
EN
XO
XI
PLL
QVSS
QVDD
RESP
RESN
32
31
30
29
28
27
26
25
PIN CONFIGURATION
BVDD
1
24
QUAD
LNI
2
23
IF2O
LVSS
3
22
FMOUT
LNO
4
21
RSSI
BVSS
5
20
MUTE
MXI
6
19
AVDD
AVSS
7
18
NC
MXO
8
17
NC
9
10
11
12
13
14
15
16
IF1IN
IF1IP
NC
NC
IF1O
VREFIF
AVSS
IF2I
PT4330-TQ
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September 2011
PT4330
PIN DESCRIPTION
V1.0
Pin Name
BVDD
LNI
LVSS
LNO
BVSS
MXI
AVSS
MXO
I/O
P
I
G
O
G
I
G
O
IF1IN
I
IF1IP
NC
NC
IF1O
I
―
―
O
VREFIF
I
AVSS
G
IF2I
I
NC
NC
AVDD
―
―
P
MUTE
I
RSSI
FMOUT
IF2O
QUAD
RESN
RESP
QVDD
QVSS
PLL
XI
XO
O
O
O
I/O
I
I
P
G
I/O
I
O
EN
I
Description
Nominal 3.6V supply for receiver front-end
Low noise amplifier input
Ground for low noise amplifier
Low noise amplifier output
Ground for receiver front-end
Mixer input
Ground for baseband strip
Mixer output
Complementary IF amplifier input (330Ω input impedance; requires
bypassing)
IF amplifier input (330Ω input impedance; requires ac-coupling)
Non-connection pin
Non-connection pin
IF amplifier output
Complementary limiting amplifier input (330Ω input impedance;
requires bypassing)
Ground for baseband strip
Limiting amplifier input (330Ω input impedance; requires
ac-coupling)
Non-connection pin
Non-connection pin
Nominal 3.6V supply for baseband strip
Tri-state logic input to control FMOUT output (MUTE = high = output
off; MUTE = low = FSK output; MUTE = floating = FM output)
Received signal strength indicator voltage
FM amplifier/FSK comparator output
Limiting amplifier output
Quadrature demodulator input
Complementary open collector VCO output
Open collector VCO output
Nominal 3.6V supply for phase-locked loop
Ground for phase-locked loop
PLL charge pump output
Oscillator input (base)
Oscillator output (emitter)
Chip enable control (RXEN = high = normal operation; RXEN = low =
stand-by mode)
5
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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September 2011
PT4330
FUNCTION DESCRIPTION
The PT4330 is a low power FM/FSK receiver IC which is suitable for use in sub-1GHz ISM bands. As shown in the block
diagram of PT4330 chip, the low noise amplifier (LNA) receives the input signal from the antenna and provides a nominal
gain of 16dB. For improved sensitivity, a reactive matching circuit may be inserted between the antenna and LNA input.
After the LNA, the RF signal is down-converted by the mixer to a lower intermediate frequency (IF). The mixer’s local
oscillator is supplied by the on-chip VCO. The VCO output frequency, fVCO, is phase-locked to a crystal oscillator
reference at frequency, fXOSC, by the integrated phase-locked loop (PLL) consisting of a divide-by-64 prescaler,
phase/frequency detector, and charge pump. The relation between fVCO and fXOSC is given by fVCO = fXOSC × 64.
The receiver IF section consists of two multiple-stage gain sections which provide nearly 74dB voltage gain to hard-limit
the received FM/FSK-modulated signal. To improve receiver selectivity, external bandpass filters may be inserted
before and after the first IF gain section. The input and output impedances of the IF gain strip are well-suited to interface
with low cost 10.7MHz ceramic filters. A received signal strength indicator (RSSI) signal is also provided.
Following the IF gain strip, an external tank-based quadrature demodulator extracts the FM or FSK data from the
hard-limited IF signal. A tri-level MUTE input is used to select among FM (audio), FSK (data), or a completely disabled
output.
ANTENNA AND LNA MATCHING
To improve input return loss, a series resonant matching circuit may be inserted between the antenna and the receiver
input, LNI. An example network suitable for 915MHz is illustrated below (note that the LNI pin requires an external dc
blocking capacitor). At the LNA output, the LNO pin requires dc bias through an inductor to power supply. In conjunction
with the blocking capacitor between LNO and MXI, this inductor may be used for impedance matching.
Figure 1. Antenna/LNA matching
For a λ/4 dipole antenna and operating frequency, f (in MHz), the required antenna length, L (in cm), may be calculated
by using the formula
7132
L=
f
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September 2011
PT4330
For example, if the frequency is 915MHz, then the length of a λ/4 antenna is 7.8cm. If the calculated antenna length is
too long for the application, then it may be reduced to λ/8, λ/16, etc. without degrading the input return loss. However,
the RF input matching circuit may need to be re-optimized. Note that in general, the shorter the antenna, the worse the
receiver sensitivity and the shorter the detection distance. Usually, when designing a λ/4 dipole antenna, it is better to
use a single conductive wire (diameter about 0.8mm to 1.6mm) rather than a multiple core wire.
If the antenna is printed on the PCB, ensure there is neither any component nor ground plane underneath the antenna
on the backside of PCB. For an FR4 PCB (εr = 4.7) and a strip-width of 30mil, the length of the antenna, L (in cm), is
calculated by
c
L=
where “c” is the speed of light (3 x1010 cm/s)
4× f × εr
CRYSTAL OSCILLATOR
f RF + f IF
, where fRF is the
64
receiving frequency of interest and fIF is the intermediate frequency (normally 10.7MHz). For low-side LO injection, use
f + f IF
f − f IF
and for high-side LO injection, use f XOSC = RF
.
f XOSC = RF
64
64
The appropriate crystal oscillator frequency, fXOSC, is calculated according to f XOSC =
For example, if the receiving frequency is 915MHz, then for low-side LO injection for an IF frequency of 10.7MHz,
f XOSC =
915−10.7
= 14.13MHz.
64
Figure 2. Crystal oscillator connections
In the figure above, the trimmer capacitor is used to fine tune the crystal reference frequency.
The following table lists the specifications for a representative crystal resonator.
Holder Type
Crystal Cut
Mode of Oscillation
Frequency Tolerance
HC-49/US
AT-cut
Fundamental
±30ppm
Frequency Stability
±50ppm
Maximum Series Resistance
80Ω maximum
Shunt Capacitance
7pF maximum
Load Capacitance
20pF
Drive Level
0.5mW maximum
±5ppm per year
Aging
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September 2011
PT4330
VCO AND PLL
The PT4330’s on-chip VCO and PLL, together with an external loop filter, form a complete frequency synthesizer. Since
the VCO is followed by a fixed divide-by-64 prescaler, the VCO frequency, fVCO, is calculated according to fVCO = fXOSC ×
64. For example, if fXOSC = 14.13MHz, then fVCO = 14.13 × 64 = 904.32MHz.
Figure 3. VCO connections
SETTING THE VCO CENTER FREQUENCY
Referring to the figure shown above, a simple procedure for setting the center frequency of the VCO is as follows:
1 Disconnect the 10KΩ isolation resistor so that the PLL is no longer operating in its normal closed-loop mode. Apply
a DC voltage of VDD / 2 at point A.
2 Adjust the values of L3, L4, and C9 to tune the oscillation frequency. For example, fix the values of L3 and L42 and
change the value of C9 such that the VCO frequency falls within ±2MHz of the desired range. If C9 is larger than
10pF, then it is recommended to change the values of L3 and L4 and readjust the value of C9. For values of C9
below 10pF, the component variation should not vary by more than ±0.25pF.
Typical L3, L4, and C9 values for different VCO frequencies are listed in the table below for reference. Also included
are recommended varactors for each VCO frequency.
Component
L3, L4
C9
D1 (Varactor)
315MHz
27
10
BB833
(Siemens)
434MHz
18
4.7
BB833
(Siemens)
868MHz
4.7
3.3
SMV1233-011
(Alpha)
915MHz
3.3
3.9
SMV1233-011
(Alpha)
Unit
nH
pF
—
3 Remove the applied voltage and re-connect the 10KΩ resistor to restore the operation of the feedback loop. The
voltage at point A should now be VDD / 2 ± 30%. Make sure the VCO frequency is locked to the desired frequency.
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September 2011
PT4330
MINIMIZING PLL LOCK TIME
In the on-chip PLL, a phase/frequency detector (PFD) compares the divided-down VCO signal with the reference crystal
oscillator signal to drive a charge pump which produces either source or sink current pulses at the PLL pin. These
current pulses, which have widths that are proportional to the phase or frequency difference between the VCO and
reference oscillator signals, are integrated by an external loop filter to feedback a tuning voltage which adjusts the VCO’s
frequency to achieve phase lock with the reference. The response time (lock time) of the PLL is primarily set by the
bandwidth of the external loop filter (although the slew rate set by the magnitude of the charge pump output current also
has a contribution). In the figure above, the two shunt capacitors and resistor connected to the PLL pin implement a
passive, second-order loop filter.
To minimize the response time of the loop, the total capacitance connected to the PLL pin should be minimized. For
minimum lock time, a rule of thumb is to design the loop filter for the highest bandwidth and minimum phase margin to
keep the loop stable.
MIXER
At the mixer output, a blocking capacitor is required between MXO and the IF amplifier input, IF1IP. To improve overall
receiver selectivity, this blocking capacitor may be replaced by a ceramic bandpass filter. Therefore, the MXO pin
provides an appropriate impedance about VSWR of 1.3 (at 10.7MHz, 330Ω reference) in order to match either the
10.7MHz IF ceramic filter or the IF amplifier input.
Figure 4. Mixer connections
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September 2011
PT4330
IF STRIP AND QUADRATURE DEMODULATOR
Because of the high gain of the IF amplifier strip, special consideration must be taken to minimize the possibility of
unwanted oscillation. All bypassing capacitors should be placed as close to the IC’s pins as possible.
Figure 5. IF strip and demodulator connections
The external ceramic bandpass filter shown in the figure is centered at 10.7MHz and has 330Ω input and output
impedances and is well-suited to interface directly with the IF amplifier sections. The inclusion of this filter is critical in
achieving superior receiver sensitivity and adjacent channel selectivity. Although such filters from various vendors will
have different center frequency tolerances and bandwidths, a nominal –6dB full-bandwidth of 180KHz should be
adequate for most applications.
A received signal strength indicator output is provided at the RSSI pin. This RSSI signal is supplied as a source current
which is proportional to the signal level at the IF1IP pin. To convert the signal to a voltage, a built-in resistor of 45KΩ is
placed between the RSSI pin and AVSS. Then, a typical RSSI curve is plotted below. Note that a 10nF capacitor may
be placed in parallel with this built-in resistor to provide filtering.
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September 2011
PT4330
RSSI Response vs. I F Input Power
2.2
RSSI Level (V)
2
1.8
1.6
1.4
1.2
FSK Mode
FM Mode
1
0.8
-110
-90
-70
-50
-30
-10
10
IF Input Power (dBm)
Figure 6. RSSI Curve
The parallel resonator tank of the quadrature demodulator may be implemented as either a ceramic discriminator or a
discrete L-C resonator. For applications where the temperature range is limited, a ceramic discriminator would work well.
However, since the temperature coefficient of a typical ceramic discrminator is ±50ppm/°C, for applications which have a
wide temperature range, the L-C resonator may be better suited. Note that since the QUAD pin is internally biased, it
must be DC blocked externally.
The table below summarizes the function of the MUTE pin.
MUTE Pin State
FMOUT Mode
Low
(< 0.1 VDD)
FSK
Floating
FM
High
(> 0.9 VDD)
Disable
FMOUT Waveform
“Low” (< 0.1 VDD)
STANDBY MODE
The EN pin controls the power-up/down of the PT4330 IC. When EN is high, the PT4330 is in normal operation mode;
when EN is low, the PT4330 is in standby mode. Note that when EN transitions from low-to-high, a finite time on the
order of 10ms is required before the received data at FMOUT becomes valid.
V1.0
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September 2011
PT4330
PCB LAYOUT CONSIDERATION
Proper layout of the PCB is extremely critical in achieving good RF performance. At the minimum, use of a two-layer
PCB is recommended so that one layer may incorporate a continuous ground plane. A large number of via holes should
connect the top layer ground areas to the bottom layer ground plane. Note that for PCB designs incorporating a printed
loop antenna, there should be no ground plane beneath the antenna.
Within the PT4330, the power and ground supply lines are partitioned so that individual blocks are biased separately to
improve isolation and minimize noise coupling effects. Careful attention must also be paid to supplying power and
ground to the IC at the board level. All ground connections between the IC and the ground plane should be made as
close as possible to the xVSS pins. To reduce supply line noise coupling, sensitive blocks such as the LNA, BVDD (bias
for RF front-end), and PLL should all be biased thru separate power supply traces incorporating series-R, shunt-C
filtering as shown below. These supply lines should be bypassed as close as possible to the IC’s xVDD pins. In addition,
improved filtering for the VCO supply line (also shown below) will reduce the phase noise of the VCO and help to
improve the overall sensitivity of the receiver. This is particularly important when low loop bandwidths (on the order of
5KHz) are used.
Figure 7. Power supply filtering
By the way, large voltage swing control lines and digital data traces should be routed away from the PLL loop filter and
VCO resonator components.
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September 2011
PT4330
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage Range
Operating Temperature Range
Storage Temperature Range
Symbol
VDD
TA
TSTG
Min.
-0.3
-10
-40
Max.
5.0
+70
+125
Unit
V
°C
°C
PACKAGE THERMAL CHARACTERISTIC
Parameter
From Chip Conjunction Dissipation to
External Environment
From Chip Conjunction Dissipation to
Package Surface
V1.0
Symbol
Condition
Rja
Rjc
TA = 27°C
13
Min.
Typ.
Max.
–
37.15
–
–
1
1.8
Unit
°C/W
September 2011
PT4330
ELECTRICAL CHARACTERISTICS
Nominal conditions: VDD = 3.3V, VSS = 0V, CE = “High”, TA = +27°C, fRF= 915MHz, fREFOSC = 14.15MHz.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
General Characteristics
Supply Voltage
VDD
2.4
3.3
3.6
Current Consumption
IDD
6.75
7.5
8.25
Standby Current
ISTBY
CE = ”Low”
–
–
1
Operating Frequency Range
fRF
300
–
1000
Note
Sensitivity
SIN
–
-100
-97
Maximum Receiver Input Level
PRF,MAX
-20
-15
–
LO Leakage
LLO
Measured at antenna input
–
-60
-57
From CE = "High" to valid
–
8
10
System Turn-On Time
TTurn-On
data out, current EVB
FM Mode
0.6
1
20
Demodulated Signal Frequency
fDemod
(Data Rate)
FSK Mode
–
2
50
LNA
Input Return Loss (S11)
-6
Power Gain (S21)
PGLNA
14
16
18
Noise Figure
NFLNA
2.5
3
Mixer
Mixer Voltage Conversion Gain
GMIX
12
15
18
Mixer Output VSWR
VSWRMXO Measured at MXO pin
1.1
1.3
1.5
IF Section
IF Frequency
fIF
–
10.7
–
Voltage Gain
Noise Figure
IF1 Input Impedance
RSSI Dynamic Range
Demodulator
FM Output DC Level
FM Output AC Level
FM Output S/N Ratio
FSK Output Duty Ratio
FSK Output Driving Current
FSK Data Output “High” Level
FSK Data Output “Low” Level
Phase-Locked Loop
GIF
NFIF
ZIN,IFX
DRRSSI
VDC,FMOUT TA = +85°C
Depend on the quality factor
VAC,FMOUT
of discriminator
for 1KHz demodulated signal
SNR FMOUT
frequency
DutyFSKOUT
IOUT,FSK
VH,FSKOUT
VL,FSKOUT
VCO Gain
GVCO
LO SSB Phase Noise
PNLO
Charge Pump Curent
ICP
Crystal Oscillator Frequency Range
Form IF1IP to IF2O, 10.7MHz
ceramic filter is inserted
between IF amplifier and limiter
μA
MHz
dBm
dBm
dBm
ms
KHz
Kb/s
dB
dB
dB
dB
–
MHz
74
300
58
12
330
64
360
70
Ω
dB
2.0
2.3
2.6
V
–
200
–
mV
30
–
40
50
±100
60
%
–
–
1
0.1
μA
VDD
VDD
Depend on the external
components in VCO tank
at 10KHz offset
at 100KHz offset
fXOSC
V
mA
68
0.9
0
80
Unit
dB
dB
30
–
dB
MHz/V
-70
-90
±40
-67
-87
dBc/Hz
dBc/Hz
–
16
μA
MHz
Note: fRF = 915MHz; Channel BW = 180KHz; BER = 1e-3; Data Rate = 2Kb/s and Frequency Deviation = ±75KHz in FSK mode.
V1.0
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September 2011
PT4330
PT4330 Current Consumption
9
Current Consumption (mA)
8
7
6
5
4
3
Enable
2
Disable
1
0
1.8
2.1
2.4
2.7
3
3.3
3.6
Supply Voltage (V)
Figure 8. Supply Current vs. Supply Voltage
Figure 9. Smith Plot of LNA Input
Sensitivity vs. Temperature
-96
Sensitivity (dBm)
-98
-100
-102
-104
916 MHz
-106
868 MHz
434 MHz
-108
315 MHz
-110
-10
0
10
20
30
40
50
60
70
Temperature (degrees C)
Figure 11. System Start-Up Time with fRF = 905MHz,
PRF = –97dBm, fDemod = 1KHz and frequency
deviation = 40KHz
Figure 10. Sensitivity vs. Temperature
S-Curve and Detuning Curve
2.85
30
S-Curve
120
Detuning Curve
2.8
100
20
10
DC Level (V)
Charge Pump Current (uA)
40
Source Current
0
Sink Current
-10
-20
2.75
80
2.7
60
2.65
40
2.6
-30
20
2.55
-40
2.5
10.60
-50
0
0.6
1.2
1.8
2.4
3
3.6
10.65
10.70
10.75
0
10.80
IF Frequency (MHz)
Voltage at PLL Pin (V)
V1.0
140
2.9
AC Level (mV)
Charge Pump DC Characteristic
50
Figure 12. Charge Pump DC Characteristic
Figure 13. S-Curve and Detuning Curve
Figure 14. VCO Phase Noise at 10KHz offset
Figure 15. VCO Phase Noise at 100KHz offset
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September 2011
PT4330
TEST BOARD LAYOUT
<Top Side>
<Bottom Side>
V1.0
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September 2011
PT4330
PACKAGE INFORMATION
32 Pins, TQFP
Symbol
A
A1
A2
b
c
D
D1
E
E1
e
L
L1
Min.
–
0.05
0.95
0.17
0.09
θ
0°
0.45
Nom.
–
–
1.00
0.22
–
7.00 BSC.
5.00 BSC.
7.00 BSC.
5.00 BSC.
0.50 BSC.
0.60
1.00 REF.
Max.
1.20
0.15
1.05
0.27
0.20
3.5°
7°
0.75
Notes:
1. Refer to JEDEC MS-026
2. Unit: mm
V1.0
17
September 2011
PT4330
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V1.0
18
September 2011