IDT74ALVC1G04 3.3V CMOS SINGLE INVERTER GATE EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74ALVC1G04 3.3V CMOS SINGLE INVERTER GATE FEATURES: DESCRIPTION: – – 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – 0.65mm pitch PSOP package – Extended commercial range of – 40°C to + 85°C – VCC = 3.3V ± 0.3V, Normal Range – VCC = 1.65V to 3.6V, Extended Range – VCC = 2.5V ± 0.2V – CMOS power levels (0.4µ W typ. static) – Rail-to-Rail output swing for increased noise margin Drive Features for ALVC1G04: – High Output Drivers: ±24mA – Suitable for heavy loads This single inverter gate is built using advanced dual metal CMOS technology. The ALVC1G04 contains one inverter gate designed for 1.65V to 3.6V VCC operation and performs the Boolean function Y = A. The ALVC1G04 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: • 3.3V High Speed Systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM A 2 4 PIN CONFIGURATION Y NC 1 A 2 GND 3 5 V CC 4 Y SO5-1 PSOP TOP VIEW FUNCTION TABLE (1) PIN DESCRIPTION Pin Names Description Input Output A Data Input A Y Y Data Output H L No Internal Connection L H NC NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level EXTENDED COMMERCIAL TEMPERATURE RANGE FEBRUARY 2000 1 c 1999 Integrated Device Technology, Inc. DSC-4528/- IDT74ALVC1G04 3.3V CMOS SINGLE INVERTER GATE EXTENDED COMMERCIAL TEMPERATURE RANGE (1) ABSOLUTE MAXIMUM RATING Symbol VTERM(2) CAPACITANCE (TA = +25oC, f = 1.0MHz) Max. – 0.5 to + 4.6 Unit V –0.5 to VCC + 0.5 – 65 to + 150 V TSTG Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature °C IOUT DC Output Current – 50 to + 50 mA IIK ± 50 mA IOK Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 – 50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA VTERM(3) Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 5 Max. 7 Unit pF COUT Output Capacitance I/O Port Capacitance VOUT = 0V 7 9 pF VIN = 0V 7 9 pF CI/O ALVC 1G Link NOTE: 1. As applicable to the device type. ALVC 1G Link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = – 40°C to +85°C, VCC = 2.3V to 3.6V Symbol VIH VIL Parameter Input HIGH Voltage Level Input LOW Voltage Level Min. 0.65 x VCC Typ.(1) — Max. — VCC = 2.3V to 2.7V 1.7 — — VCC = 2.7V to 3.6V 2 — — VCC = 1.65V to 1.95V — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 ±5 VCC Test Conditions = 1.65V to 1.95V 0.35 x VCC Unit V V IIH Input HIGH Current VCC = 3.6V VI = VCC — — µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ± 10 µA IOZL (3-State Output pins) VO = GND — — ± 10 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ICCZ ∆ICC Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC — 0.1 10 µA Quiescent Power Supply Current Variation One input at VCC − 0.6V, other inputs at VCC or GND — — 750 µA ALVC 1G Link NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2 IDT74ALVC1G04 3.3V CMOS SINGLE INVERTER GATE EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 1.65V to 3.6V IOH = – 0.1mA Min. VCC – 0.2 VCC = 1.65V IOH = – 4mA VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3.0V Output LOW Voltage Unit V 1.2 VCC = 2.7V VOL Max. — 2.4 — VCC = 3.0V IOH = – 24mA 2 — VCC = 1.65V to 3.6V IOL = 0.1mA — 0.2 VCC = 1.65V IOL = 4mA VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 V 0.45 ALVC 1G Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25oC Symbol CPD Parameter Power Dissipation Capacitance VCC = 1.8V ± 0.15V VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Typical Typical Typical Test Conditions CL = 0pF, f = 10Mhz Unit pF SWITCHING CHARACTERISTICS(1) VCC = 1.8V ± 0.15V Symbol Parameter tPLH Propagation Delay tPHL A to Y Min. 1 VCC = 2.5V ± 0.2V Max. 6 Min. 1 NOTE: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 3 Max. 3.8 VCC = 2.7V Min. Max. 3.6 VCC = 3.3V ± 0.3V Min. 1 Max. 3.2 Unit ns IDT74ALVC1G04 3.3V CMOS SINGLE INVERTER GATE EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ± 0.3V VCC(1) = 2.7V 6 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 VCC(2)= 2.5V ± 0.2V Unit 2 x Vcc V 50 30 SAME PHASE INPUT TRANSITION tPLH tPHL tPLH tPHL OUTPUT ALVC 1G Link V OH VT V OL V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF V IH VT 0V ALVC 1G Link ENABLE AND DISABLE TIMES TEST CIRCUITS FOR ALL OUTPUTS V LOAD V CC 500 Ω (1, 2) V IN CONTROL INPUT GND tPZL V OUT Pulse Generator OUTPUT SW ITCH NORMALLY CLO SED LOW tPZH OUTPUT SW ITCH NORMALLY OPE N HIGH D.U.T. 500 Ω RT DISABLE ENABLE Open CL ALVC 1G Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. tPLZ 0V V LOAD/2 V LOAD/2 VT V LZ V OL tPHZ V OH V HZ VT 0V 0V ALVC 1G Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION SET-UP, HOLD, AND RELEASE TIMES Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD DATA INPUT tSU tH TIMING INPUT GND tREM ASYNCHRONOUS CONTROL Open ALVC 1G Link SYNCHRONOUS CONTROL tSU tH V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V ALVC 1G Link PULSE WIDTH LOW -HIGH-LOW PULSE VT tW HIGH-LOW -HIGH PULSE V IH VT VT ALVC 1G Link 4 IDT74ALVC1G04 3.3V CMOS SINGLE INVERTER GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 1.8V ± 0.15V TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 1.8V ± 0.15V 2 x VCC Unit V VIH VCC V V IH VT 0V SA M E PHA SE INPU T TRA NSITIO N t PLH t PHL t PLH t PHL V OH VT VOL O UTPUT VT VCC / 2 V VLZ 150 mV VHZ 150 mV CL 30 V IH VT 0V O PPO SITE PHA SE INPU T TRA NSITIO N pF ALVC 1G Link ALVC 1G Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC (1) CO NTRO L INPU T G ND 1000 Ω V IN t PZL O UTPUT SW ITCH NO RMA LLY CLO SED LO W t PZH O UTPUT SW ITCH NO RMA LLY OPEN HIG H D.U.T. RT CL 1000 Ω DEFINITIONS: ALVC 1G Link CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTE: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. V IH VT V OUT Pulse G enerator DISA BLE ENA BLE O pen t PLZ 0V V LOAD/2 V LOAD/2 VT V LZ V OL t PHZ V OH V HZ VT 0V 0V ALVC 1G Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SET-UP, HOLD, AND RELEASE TIMES SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD SY NCHRO NOUS CO NTRO L V IH VT 0V t SU tH TIM ING INPU T GND t REM Open ALVC 1G Link PULSE WIDTH t SU tH ALVC 1G Link LO W -HIG H-LO W PULSE VT tW HIG H-LO W -HIGH PULSE AS YNCHRO NOUS CO NTRO L V IH VT 0V V IH VT 0V V IH VT 0V DATA INPU T VT ALVC 1G Link 5 IDT74ALVC1G04 3.3V CMOS SINGLE INVERTER GATE EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION ID T XX Tem p. Range ALVC XXX XX Device Type Package DY Plastic Sm all O utline Package (SO5-1) 1G 04 Single Inverter Gate, ±24m A – 40°C to +85°C 74 PICOGATE-LOGIC (DY) PACKAGES Due to their small size, PicoGate-Logic packages require more complex symbolization guidelines. IDT’s 5-pin PSOP (DY) packaged devices utilize a three-symbol name rule. The first symbol denotes device technology, the second symbol denotes device function, and the third symbol denotes a wafer fab/assembly site code for internal tracking. EXAMPLES: 1. A PicoGate-Logic device with package code LR* is an IDT74LVC1G79A. 2. A PicoGate-Logic device with package code GC* is an IDT74ALVC1G04. PICOGATE-LOGIC (DY) PACKAGE SYMBOLIZATION GUIDELINES TECHNOLOGY ALVC ALVCH LVC LVCH(1) CODE G J L FUNCTION 00 02 04 U04 06 07 08 14 32 79 86 125 126 132 CODE A B C D T V E F G R H M N Y NOTE: 1. Code to be determined. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6