APW8825

APW8825
3A 5V 1MHz Synchronous Buck Converter
Features
General Description
•
APW8825 is a 3A synchronous buck converter with integrated 110mΩ high side and 80mΩ low side power
High Efficiency up to 95%
- Automatic Skip/PWM Mode Operation
•
Adjustable Output Voltage from 0.6V to VIN
•
Integrated 110mΩ High side 80mΩ Low Side
MOSFETs. The APW8825 design with a current-mode
control scheme, can convert wide input voltage of 2.6V to
5.5V to the output voltage adjustable from 0.6V to 5.5V to
provide excellent output voltage regulation.
MOSFET
•
Low Dropout Operation : 100% Duty cycle
•
Stable with Low ESR Ceramic Capacitors
•
Power-On-Reset Detection on VIN
•
Integrate Soft Start and Soft-Stop
•
Over-Temperature Protection
•
Over Voltage Protection
•
Under Voltage Protection
•
High/ Low Side Current Limit
•
Power Good Indication
•
Enable/Shutdown Function
•
Small SOT-23-6 and TDFN2x2-8 packages
•
Lead Free and Green Devices Available (RoHS
The APW8825 is equipped with an automatic Skip/PWM
mode operation. At light load, the IC operates in the Skip
mode to reduce the switching losses. At heavy load, the
IC works in PWM mode. At PWM mode, the switching
frequency is set by the external resistor.
The APW8825 is also equipped with Power-on-reset, soft
start, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature and current-limit) into a
single package.
This device, available TDFN2X2-8 and SOT-23-6 provide
a very compact system solution external components and
PCB area.
Applications
compliant)
•
Notebook Computer & UMPC
•
LCD Minitor/TV
•
Set-Top Box
•
DSL, Switch HUB
•
Portable Instrument
Simplified Application Circuit
VIN
VIN
L1
APW8825
R3
NC
C1
(option)
ON
R1
COUT
FB
R2
POK
OFF
VOUT
LX
CIN
PGND
EN
AGND
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
1
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APW8825
Pin Configurations
APW8825
APW8825
EN 1
6 FB
GND 2
FB
POK
VIN
PGND
5 POK
LX 3
4 VIN
1
8 AGND
2
7 EN
3
6 LX
4
5 NC
TDFN2x2-8
(Top View)
SOT23-6
(Top View)
Ordering and Marking Information
APW8825
Package Code
QB : TDFN-2x2-8
Assembly Material
C: SOT23-6
Operating Ambient Temperature Range
I : -40 to 85oC
Handling Code
Temperature Range
Handling Code
TR : Tape & Reel
Package Code
Assembly Material
G: Halogen and Lead Free Device
APW8825QB :
W25
X
APW8825C :
X - Date Code
W25X
X - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
Unit
-0.3 ~ 6.5
V
< 30ns pulse width
-3 ~ 8
V
> 30ns pulse width
-1 ~VIN+0.3
V
POK, FB, EN to PGND Voltage
-0.3 ~ 6.5
V
AGND to PGND Voltage
-0.3 ~ 0.3
VIN
Input Supply Voltage to PGND
VLX
LX to GND Voltage
V
TJ
Junction Temperature
150
o
TSTG
Storage Temperature
-65 ~ 150
o
260
o
TSDR
Maximum Lead Soldering Temperature(10 Seconds)
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
2
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APW8825
Thermal Characteristics
Symbol
Parameter
Typical Value
Junction-to-Ambient Resistance in free air (Note 2)
θJA
TDFN2x2-8
75
TSOT23-6
250
Unit
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol
VIN
VOUT
(Note 3)
Parameter
Range
Unit
Control and Driver Supply Voltage
2.6 ~ 5.5
V
Converter Output Voltage
0.6 ~ VIN
V
1 ~ 2.2
µH
Inductance
L
IOUT
Converter Output Current
0~3
Ambient Temperature
TA
Junction Temperature
TJ
A
-40 ~ 85
o
-40 ~ 125
o
C
C
Note 3 : Refer to the typical application circuit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=3.7V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Pa ra mete r
Symbol
APW8 825
Test Conditions
Unit
Min
Typ
Max
Supply Current
I DD
I SHDN
VIN Supp ly Curre nt
VFB=0.66 V
-
65
-
µA
VIN Shutdown Su pply Cu rrent
EN=GND
-
-
1
µA
VIN Risi ng
2 .3
2.4
2 .5
V
0 .1
0.2
0 .3
V
-
0 .6
-
V
-1
-
+1
%
-1.5
-
+1.5
%
0.85
1
1.15
MHz
-
70
-
ns
Power- On-Reset (POR)
VIN POR Vo ltag e Thr eshold
VIN POR Hyste resis
Reference Volta ge
VREF
Referen ce Voltage
o
T A=25 C
Ou tp ut Accu racy
IOUT =1 0mA~3A,
VIN=2.6~5.5V
Os cillator
F OSC
Oscillator Frequ ency
Minimum on Time
Copyright  ANPEC Electronics Corp.
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APW8825
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=3.7V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Pa ra mete r
APW8 825
Test Conditions
Symbol
Unit
Min
Typ
Max
Power MOSFET
o
High Si de P-MOS FET Resistance
VIN=5V, I LX=0.5A, T A=25 C
-
110
-
mΩ
Lo w Sid e N-MOSFET Resistance
VIN=5V, I LX=0.5A, T A=25oC
-
80
-
mΩ
-
-
10
µA
4
5
6
A
-
1 60
-
°C
High/Lo w
Curre nt
S ide
MOSFET
Leakage
Protect ions
I LIM
High Si de MOSFET cur rent-limit
T OTP
Over- tem perature Trip Po int
(Resoft start after OTP)
Pea k Curre nt, VIN=2.6 ~5.5V
o
T A= -40 ~125 C
-
50
-
°C
12 0
1 25
13 0
%V REF
57
66
75
%V REF
20
25
30
µs
-
-1
-
A
So ft Sta rt time
-
0.8
-
ms
EN Ena ble threshold
-
-
1 .4
V
0 .5
-
-
V
-
0.5
2
µA
82.5
87.5
92.5
%VOUT
-
5
-
%VOUT
12 0
1 25
13 0
%VOUT
-
5
-
%VOUT
-
1 00
-
Ω
-
20
-
us
Over- tem perature Hyster esis
Over- Voltage Protectio n thre sh old
VOUT Rising
Unde r-Vol tag e Protecti on th reshold
Over- Voltage Protectio n debo unce time
Lo w Sid e Switch Curre nt-Limit
From Dra in to S ource
Soft-Sta rt, Enable a nd POK
EN shutdown th reshold
EN Pull L ow Curre nt
PO K th reshold
PO K i n from Lo wer
(PO K Goes High)
PO K L ow Hyster esis
(PO K Goes Low)
PO K i n from Highe r
(PO K Goes High)
PO K Hig h Hyste resis
(PO K Goes Low)
Po we r Good pu ll low re si stance
Po we r Good Debo unce
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
High to low
4
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APW8825
Pin Description
PIN
Function
TDFN2x2-8
TSOP23-6
Name
1
6
FB
Output Feedback Input. The APW8825 senses the feedback voltage via FB and regulates
the voltage at 0.6V. Connecting FB with a resistor-divider from the converter’s output sets
the output voltage.
2
5
POK
Power Good Output. This pin is open-drain logic output that is pulled to ground when the
output voltage is not within 10% of regulation point.
3
4
VIN
The control circuitry and converter supply input. Connecting a ceramic bypass capacitor
from VIN to GND to eliminate switching noise and voltage ripple on the input to the IC.
4,
Exposed pad
-
PGND
5
-
NC
No internal connection.
6
3
LX
Power Switching Output. LX is the Junction of the high-side and low-side Power
MOSFETs to supply power to the output LC filter.
7
1
EN
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on
the regulator, drive it low to turn it off.
8
-
AGND
-
2
GND
Power ground. Connect this pin to AGND.
Analog ground. Connect this pin to PGND.
Power and signal ground.
Block Diagram
VIN
Current
Sense
Amplifier
LOC
Over
Temperature
Protection
PowerOnReset
Current
Limit
Zero Crossing
Comparator
POR
125%VREF
OTP
OVP
Fault
Logics
66%VREF
UVP
Inhibit
POK
LX
Gate
Driver
Current
Compartor
Error
Amplifier
90%VREF
FB
Gate
Control
Gat
e
Gm
Slope
Compensation
VREF
0.6V
Shutdown
Oscillator
LOC
Current
Sense
Amplifier
GND
ISS
EN
POK
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APW8825
Typical Application Circuit
VIN
L1
1uH
VIN
CIN
22uF
APW8825
R3
100k
NC
C1
(option)
ON
R1
24K
FB
COUT
22uFx2
R2
12K
POK
OFF
VOUT
LX
PGND
EN
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
AGND
6
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APW8825
Function Description
VCC and VIN Power-On-Reset (POR)
The thermal sensor allows the converters to start a start-
TThe APW8825 keeps monitoring the voltage on VIN pin
to prevent wrong logic operations which may occur when
up process and to regulate the output voltage again after
the junction temperature cools by 50oC. The OTP is de-
VIN voltage is not high enough for internal control circuitry
to operate. The VIN POR rising threshold is 2.4V with
signed with a 50 oC hysteresis to lower the average TJ
during continuous thermal overload conditions, increas-
0.2V hysteresis.
During startup, the VIN voltage must exceed the POR
ing lifetime of the APW8825.
Current-Limit Protection
threshold. Then the IC starts a starts-up process and
ramps up the output voltage to the voltage target.
The APW8825 monitors the output current, flows through
the high-side and low-side power MOSFETs, and limits
the current peak at current-limit level to prevent the IC
Output Under-Voltage Protection (UVP)
from damaging during overload, short-circuit and overvoltage conditions. Typical high side power MOSFET cur-
In the operational process, if a short-circuit occurs, the
rent limit is 5A, and low side MOSFET current limit is 1A.
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the re-
Soft-Start
quired regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
The APW8825 has a built-in soft-start to control the rise
rate of the output voltage and limit the input current surge
during start-up. During soft-start, an internal voltage ramp
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC shuts down
connected to one of the positive inputs of the error
converter’s output.
amplifier, rises up to replace the reference voltage until
the voltage ramp reaches the reference voltage. During
The under-voltage threshold is 66% of the nominal output voltage. The APW8825 will be latched after under-
soft-start without output over-voltage, the APW8825
converter’s sinking capability is disabled until the output
voltage protection.
voltage reaches the voltage target.
Soft-Stop
At the moment of shutdown controlled by EN signal, under-voltage event or over-voltage event, the APW8825 ini-
Over-Voltage Protection (OVP)
The over-voltage function monitors the output voltage by
tiates a soft-stop process to discharge the output voltage
in the output capacitors. Certainly, the load current also
FB pin. When the FB voltage increases over 125% of the
reference voltage due to the high-side MOSFET failure or
discharges the output voltage. During soft-stop, the internal voltage ramp (VRAMP) falls down to replace the refer-
for other reasons, the over-voltage protection comparator
will trigger soft-stop function and shutdown the converter
output.
ence voltage. The low side MOSFET turns on each cycle
to discharge the output voltage. Therefore, the output volt-
Over-Temperature Protection (OTP)
age falls down slowly at the light load. After the soft-stop
interval elapses, the soft-stop process ends and the IC
The over-temperature circuit limits the junction temperature of the APW8825. When the junction temperature ex-
turns off.
Enable and Shutdown
ceeds TJ =160 oC, a thermal sensor turns off the both
power MOSFETs, allowing the devices to cool.
Driving EN to ground places the APW8825 in shutdown.
In shutdown mode, the internal power MOSFETs turns
off, all internal circuitry shuts down and the quiescent
supply current reduces to less than 1µA.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
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APW8825
Function Description (Cont.)
Power Good Indicator
POK is actively held low in shutdown and soft-start status.
In the soft-start process, the POK is an open-drain. When
the soft-start is finished, the POK is high. In normal
operation, the POK window is from 85% to 125% of the
converter reference voltage. When the output voltage stays
within this window, POK signal will become high after 0.
5ms internal delay. When the output voltage outruns 80%
or 120% of the target voltage, POK signal will be pulled
low immediately. In order to prevent false POK drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. The POK
pin, if used, needs an axternal pull high resistor, the recommended resistor should be in the range of 30KΩ to
100KΩ.
Copyright  ANPEC Electronics Corp.
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APW8825
Application Information
Input Capacitor Selection
shown in “Typical Application Circuits”. A suggestion of
Because buck converters have a pulsating input current,
a low ESR input capacitor is required. This results in the
maximum value of R2 is 20kΩ to keep the minimum current that provides enough noise rejection ability through
best input voltage filtering, minimizing the interference
with other circuits caused by high input voltage spikes.
the resistor divider. The output voltage can be calculated
as below:
R1 
R1 


VOUT = VREF ⋅  1 +
 = 0.6 ⋅ 1 +

R2 
R2 


Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For
good input voltage filtering, usually a 22µF input capacitor
is sufficient. It can be increased without any limit for better
VOUT
input-voltage filtering. Ceramic capacitors show better
performance because of the low ESR value, and they are
R1≤80kΩ
less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input capacitor as
FB
R2 ≤ 20kΩ
APW8825
close as possible to the input and GND pin of the device
for better performance.
GND
Inductor Selection
Output Capacitor Selection
For high efficiencies, the inductor should have a low DC
The current-mode control scheme of the APW8825 allows the use of tiny ceramic capacitors. The higher ca-
resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a
pacitor value provides the good load transients response.
higher impact on efficiency. When using small chip
inductors, the efficiency is reduced mainly due to higher
Ceramic capacitors with low ESR values have the lowest
output voltage ripple and are recommended. If required,
inductor core losses. This needs to be considered when
selecting the appropriate inductor. The inductor value de-
tantalum capacitors may be used as well. The output
ripple is the sum of the voltages across the ESR and the
termines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the
ideal output capacitor.
lower the conduction losses of the converter. Conversely,
larger inductor values cause a slower load transient
∆VOUT
response. A reasonable starting point for setting ripple
current, ∆IL, is 40% of maximum output current. The rec-

V
VOUT ⋅ 1 − OUT
VIN

≅
FSW ⋅ L


 
1
 ⋅  ESR +

8 ⋅ FSW ⋅ COUT





When choosing the input and output ceramic capacitors,
ommended inductor value can be calculated as below:
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-


V
VOUT 1 − OUT 
V
IN


L≥
FSW ⋅ ∆IL
acteristics of all the ceramics for a given value and size.
IL(MAX) = IOUT(MAX) + 1/2 x ∆IL
VIN
IIN
To avoid the saturation of the inductor, the inductor should
IP-FET
be rated at least for the maximum output current of the
converter plus the inductor ripple current.
IL
CIN
IOUT
P-FET
VOUT
SW
Output Voltage Setting
N-FET
In the adjustable version, the output voltage is set by a
resistive divider. The external resistive divider is con-
ESR
COUT
nected to the output, allowing remote voltage sensing as
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
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APW8825
Application Information (Cont.)
Output Capacitor Selection (Cont.)
IL
ILIM
IPEAK
∆IL
IOUT
IP-FET
Power Sequencing
At start-up, it is necessary to ensure that the VIN (the
voltage supplied to MOSFET drain) and VEN are sequenced correctly to avoid erroneous latch-off. To avoid
UVP latch-off happened at start-up due to sequencing
issues, the key method is the VIN should be larger than
the output under-voltage threshold plus the drop through
the pass MOSFET when that output is enabled.
Figure 1 shows the VIN comes up before the VEN. Recommended power on sequence is shown in Figure1.
VIN
VEN
VUV(TH)
VEN(TH)
VOUT
VEN(TH) occurs after
VUV(TH) is reached
Figure 1. APW8825 power on sequence.
Copyright  ANPEC Electronics Corp.
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APW8825
Package Information
TDFN2x2-8
A
b
E
D
D2
A1
A3
NX
aaa c
E2
SEATING PLANE
L
K
Pin 1 Corner
e
S
Y
M
B
O
L
TDFN2*2-8
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.012
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.007
D
1.90
2.10
0.075
0.083
D2
1.00
1.60
0.039
0.063
E
1.90
2.10
0.075
0.083
E2
0.60
1.00
0.024
0.039
e
0.50 BSC
0.020 BSC
L
0.30
0.45
0.012
0.018
K
0.20
0.30
0.008
0.012
aaa
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
0.08
0.003
11
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APW8825
Package Information
SOT-23-6
D
e
E
E1
SEE
VIEW A
b
c
0.25
A
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
e1
VIEW A
S
Y
M
B
O
L
SOT-23-6
INCHES
MILLIMETERS
MAX.
MIN.
A
MIN.
MAX.
1.45
0.057
A1
0.00
0.15
0.000
0.006
A2
0.90
1.30
0.035
0.051
b
0.30
0.50
0.012
0.020
c
0.08
0.22
0.003
0.009
D
2.70
3.10
0.106
0.122
E
2.60
3.00
0.102
0.118
E1
1.40
1.80
0.055
0.071
e
0.95 BSC
e1
1.90 BSC
0.037 BSC
0.075 BSC
L
0.30
0.60
0.012
0
0°
8°
0°
0.024
8°
Note : 1. Follow JEDEC TO-178 AB.
2. Dimension D and E1 do not include mold flash, protrusions or
gate burrs. Mold flash, protrusion or gate burrs shall not exceed
10 mil per side.
Copyright  ANPEC Electronics Corp.
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APW8825
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.20
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
2.35±0.20
2.35±0.20
1.00±0.20
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
TDFN2x2-8
Application
SOT-23-6
4.0±0.10
4.0±0.10
1.0
MIN.
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOT-23-6
Tape & Reel
3000
TDFN2x2-8
Tape & Reel
3000
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APW8825
Taping Direction Information
TDFN2x2-8
USER DIRECTION OF FEED
SOT-23-6
USER DIRECTION OF FEED
AAAX
AAAX
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
AAAX
AAAX
14
AAAX
AAAX
AAAX
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APW8825
Classification Profile
Copyright  ANPEC Electronics Corp.
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APW8825
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
16
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APW8825
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
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Tel : 886-2-2910-3838
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Copyright  ANPEC Electronics Corp.
Rev. A.3 - Feb., 2016
17
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