APW8713CA

APW8713CA
High Input Voltage 10A PWM Converter With Adj. Soft Start
Features
General Description
•
Adjustable Output Voltage from +0.8V to +12V
The APW8713CA is a 10A, synchronous, step-down con-
- 0.8V Reference Voltage
verter with integrated 30mΩ N-channel High-Side
MOSFET and 9mΩ Low-Side MOSFET. The APW8713CA
- +1% Accuracy over Temperature
•
steps down high voltage to generate low-voltage chipset
or RAM supplies in notebook computers.
Operates from An Input Battery Voltage Range of
+2.7V to +28V
•
Power-On-Reset Monitoring on VCC pin
•
Excellent line and load transient responses
•
PFM mode for increased light load efficiency
•
Programmable PWM Frequency from 100kHz to
The APW8713CA provides excellent transient response
and accurate DC voltage output in either PFM or PWM
Mode. In Pulse Frequency Mode (PFM), the APW8713CA
provides very high efficiency over light to heavy loads with
loading-modulated switching frequencies. In PWM Mode,
the converter works nearly at constant frequency for low-
1000kHz
•
Integrated 30mΩ at VCC=5V N-Channel MOSFET
noise requirements.
The APW8713CA is equipped with accurate current-limit,
For High Side
•
output under-voltage, and output over-voltage protections,
perfect for various applications. A Power-On-Reset func-
Integrated 9mΩ at VCC=5V N-Channel MOSFET For
Low Side
•
Integrated Bootstrap Forward P-CH MOSFET
•
External Adjustable Soft-Start and Soft-Stop
•
Selectable Forced PWM or automatic PFM/PWM
tion monitors the voltage on VCC to prevent wrong
operation during power-on. The APW8713CA has external adjustable soft-start and built-in an integrated output
discharge method for soft stop. A soft-start ramps up the
mode
•
output voltage with programmable timing to reduce the
start-up current. A soft-stop function actively discharges
Power Good Monitoring
•
70% Under-Voltage Protection
•
125% Over-Voltage Protection
the output capacitors.
The APW8713CA is available in TQFN4x4-23 (Power
•
Current-Limit Protection
PAK).
- Using Sense Low-Side MOSFET’s RDS(ON)
•
Over-Temperature Protection
•
TQFN-23 4mmx4mm package
•
Lead Free and Green Device Available (RoHS
Applications
Compliant)
•
•
Notebook
•
Table PC
•
Hand-Held Portable
•
AIO PC
•
Set-top boxes
•
LCD TV
Mother Board
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
1
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APW8713CA
Simplified Application Circuit
VCC
EN
RPOK
VIN
POK
VIN
H/L
LOUT
PFM
VOUT
LX
CSS
SS
COUT
APW8713CA
Ordering and Marking Information
Package Code
QB: TQFN4x4-23
Operating Ambient Temperature Range
I : -40 to 85 °C
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device G : Halogen and Lead Free Device
APW8713CA
Assembly Material
Handling Code
Temperature Range
Package Code
APW8713CA QB :
XXXXX - Date Code
APW8713
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
18 LX
19 PGND
20 BOOT
21VCC
22 VIN
23 SS
Pin Configuration
POK 1
17 LX
EN 2
16 LX
PFM 3
VIN
15 PGND
LX
12 PGND
LX 11
TON 6
LX 10
13 PGND
VIN 9
FB 5
VIN 8
14 PGND
NC 7
AGND 4
TQFN 4x4 -23 (TOP VIEW)
= Exposed and Thermal Pad
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
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APW8713CA
Absolute Maximum Ratings (Note 1)
Symbol
VV CC
VIN
VTON
Parameter
VCC Supply Voltage (VCC to AGND)
Rating
Unit
-0.3 ~ 7
V
VIN Supply Voltage (VIN to AGND)
-0.3 ~ 30
V
TON Supply Voltage (TON to AGND)
-0.3 ~ 30
V
VBOOT-GND
BOOT Supply Voltage (BOOT to AGND)
-0.3 ~ 37
V
VBOOT
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 7
V
VGND
AGND to PGND
-0.3 ~ +0.3
V
-0.3 ~ 7
V
-7 ~ 32
-0.3 ~ 30
V
All Other Pins (POK, EN, FB, SS and PFM to AGND)
LX Voltage (LX to PGND)
VLX
TJ
TSTG
TSDR
<50ns pulse width
>50ns pulse width
Junction Temperature
Storage Temperature
Maximum Lead Soldering Temperature(10 Seconds)
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Typical Value
Junction-to-Ambient Resistance in free air (Note 2)
Unit
o
50
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)
Symbol
Range
Unit
VCC Supply Voltage
4.5 ~ 5.5
V
VIN
Converter Input Voltage
2.7 ~ 28
V
VOUT
Converter Output Voltage
0.8 ~ 13.2
V
IOUT
Converter Output Current
0 ~ 10
A
CIN
PWM1/2 Converter Input Capacitor (MLCC)
10 ~
µF
VCC Output Capacitor (MLCC)
1.0 ~
µF
VVCC
CVCC
Parameter
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
C
C
Note 3: Refer to the application circuit for further information.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
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APW8713CA
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=12V,VEN=5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Sym bol
Pa ramete r
AP W871 3CA
Te st Condition
Min.
Typ.
Max.
Unit
1 3.2
V
VO UT AND VFB VOLTAG E
VOUT
Ou tp ut Voltage
VREF
Referen ce Voltage
IFB
T STOP
Adj ustab le output range
0.8
0.8
o
o
Regu lation A ccu racy
T A = - 40 C ~ 85 C
FB Input B ias Cu rrent
FB=0 .7 5V
Ou tp ut Discharge Time
EN go low to outpu t remai n b elow
0.1V
- 1.0
V
-
+1.0
%
0.02
-
µA
-
5*Tss
-
-
SUP PLY CURRENT
I VCC_N OR MAL
VCC Qui escen t Sup ply
Curre nt
EN=5 V, FB =0.835 V, VCC=5V
-
0.7
1
mΑ
I VCC _SHDN
VCC Shutdo wn Curre nt
EN=G ND, VCC=5V
-
-
25
µA
200
2 50
300
ns
100 0
kHz
ON-TIME TIMER AND INTERNAL SO FT START
TON
Nomin al on time
F SW
Freq uency a djustable
ran ge
T OFF(MIN)
ISS
VIN=12V, VOUT =1V , R TON=100kΩ
100
Minimu m off time
VFB=0.75 V, V PHASE=-0.1V
-
2 50
-
ns
Interna l S oft Start Curr ent
Vss=0V ，Css=0.001 uF to 0.1uF
8
10
12
µA
High S ide MOSFET On
Resista nce
VIN=12 V，VCC=5V
-
27
41
mΩ
Lo w Sid e MO SFET On
Resista nce
VIN=12 V，VCC=5V
-
7
11
mΩ
G ATE DRIV ER
BOO TS TRAP SWITCH
VF
Ron
VPVCC – VBOOT-GN D, I F = 10mA
-
0.5
0.7
V
IR
Reverse Lea ka ge
VBOOT-GND = 30V, VPHASE = 25V,
VPVCC = 5 V
-
-
0.5
µA
4.25
4.35
4 .45
V
-
1 00
-
mV
2.5
-
-
V
-
-
0.5
V
-
0.1
-
µA
PFM High-L eve l Inp ut
Voltage
2.5
-
-
V
PFM Low-Le vel Inpu t
Voltage
-
-
0.5
V
-
0.1
-
µA
VCC POR THRES HOLD
V LCC _THF
Falli ng VCC P OR
Thre sh old Volta ge
LDO P OR Hyste resis
CONTROL INPUTS
EN High-L evel In put
Voltage
EN Low-Le ve l Inp ut Voltage
EN Lea kage
PFM Leaka ge
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
E N=0V
P FM=0V
4
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APW8713CA
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=12V,VEN=5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Sym bol
Param eter
AP W871 3CA
Te st Condition
Min.
Typ.
Max.
Unit
PO K i n from Lo wer (POK Go es
High)
87
90
93
%
PO K o ut from No rmal (PO K G oes
Low)
120
1 25
130
%
-
0.1
-
µA
1.25
7.5
-
mA
PO WER-OK INDICATOR
V POK
I POK
PO K Thre shold
PO K L eakage Cur rent
VPOK=5V
PO K S ink Cu rrent
VPOK=0.5V，
PO K O ut Deb ounce Time2
When ru n awa y 90 %
-
20
-
µs
PO K E nab le De lay Tim e
From EN High to POK Hig h
-
Tss
-
ms
CURRE NT SE NS E
I OC P
OCP Th reshold
Va lley Cu rrent of IL
11
-
-
A
Zero Crossing Compara to r
Offset
VGND-L X Voltage, PFM=0V
-5
0
5
mV
65
70
75
%
PRO TE CTION
VUV
UVP Th reshold
UVP Debou nce Interval
UVP Ena ble Delay
EN high to UV P worka ble
V OVR
OV P Rising Thresho ld1
OVP Occur
OV P P ropag ation Delay
VFB Rising , Over Voltage=10mV
TOTR
OTP Risin g Th reshold (Note
5)
OTP Hysteresis ( No te 5 )
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
µs
16
Tss
1 25
130
%
-
3
-
µs
-
1 45
-
o
-
o
-
5
ms
120
45
C
C
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APW8713CA
Typical Operating Characteristics
Reference Voltage vs. Junction
Temperature
Switching Frequency vs. Output
Current
1000
Switching Frequency (kHz)
Reference Voltage (V)
0.804
0.802
0.8
0.798
0.796
100
10
1
Automatic PFM/PWM Mode
Force PWM Mode
0.794
-50
-25
0
25
50
75
0.1
0.001
100
0.01
o
0.1
1
10
Output Current(A)
Junction Temperature ( C)
Output Voltage vs Output Current
Output Voltage vs Input Voltage
1.090
1.10
Automatic PFM/PWM Mode
Force PWM Mode
1.085
Output Voltage (V)
Output Voltage (V)
1.09
1.08
1.07
1.080
1.075
1.070
1.065
1.060
1.06
1.055
1.05
PFM Operation
PWM Operation
1.050
0
2
4
6
8
10
0
Output Current(A)
5
10
15
20
25
30
Input Voltage(V)
Switching Frequency vs. Input
Voltage
Switching Frequency (kHz)
340
330
320
310
300
290
280
0
5
10
15
20
25
30
Input Voltage(V)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
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APW8713CA
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
Enable Without Loading
Enable With Loading
V EN
V EN
1
1
VLX
VLX
2
2
V OUT
V OUT
3
3
4
V POK
4
CSS=10nF
V POK
CSS=10nF
CH1: VEN, 5V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: VOUT , 500mV/Div, DC
CH4: VPOK , 5V/Div, DC
TIME: 1ms/Div
CH1: VEN, 5V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: VOUT , 500mV/Div, DC
CH4: VPOK , 5V/Div, DC
TIME:1ms/Div
Soft- Stop Function
Shutdown With Loading
CSS=10nF
V EN
VEN
1
1
VLX
VLX
2
2
V OUT
VOUT
V POK
VPOK
3
3
4
4
CH1: VEN, 5V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: VOUT , 500mV/Div, DC
CH4: VPOK , 5V/Div, DC
TIME:5ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
CH1: VEN, 5V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: VOUT , 500mV/Div, DC
CH4: VPOK , 5V/Div, DC
TIME:500µs/Div
7
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APW8713CA
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
PWM Switching Waveform
PFM Switching Waveform
V OUT
VOUT
1
1
VLX
2
VLX
2
IL
IL
3
3
CH1: VOUT , 50mV/Div, AC
CH2: VLX, 10V/Div, DC
CH3: IL, 2A/Div, DC
TIME: 2µs/Div
CH1: VOUT , 50mV/Div, AC
CH2: VLX, 5V/Div, DC
CH3: IL, 2A/Div, DC
TIME: 1µs/Div
Load Transient 2
Load Transient 1
1
V OUT
VOUT
1
V LX
VLX
2
2
IL
IL
3
3
CH1: VOUT , 100mV/Div, AC
CH2: VLX, 10V/Div, DC
CH3: IL, 5A/Div, DC
TIME: 20µs/Div
CH1: VOUT , 100mV/Div, AC
CH2: VLX, 10V/Div, DC
CH3: IL, 5A/Div, DC
TIME: 20µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
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APW8713CA
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
Current LImit and UVP Function
Short Circuit Protection
VOUT
VOUT
1
1
VLX
VLX
2
2
IL
3
3
CH1: VOUT , 1V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: IL, 10A/Div, DC
TIME: 500µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
IL
CH1: VOUT , 1V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: IL, 10A/Div, DC
TIME: 20µs/Div
9
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APW8713CA
Pin Description
PIN
FUNCTION
NO.
NAME
1
POK
2
EN
3
PFM
4
AGND
5
FB
6
TON
7
NC
No connect.
8, 9, 22
VIN
Battery Voltage Input Pin. VIN powers linear regulators and is also used for the constant on-time PWM
on-time one-shot circuits. Connect VIN to the battery input and bypass with a 1µF capacitor for noise
interference.
10, 11,
16~18
LX
Junction Point of The High-Side MOSFET Source, Output Filter Inductor and The Low-Side MOSFET Drain
for PWM. Connect this pin to the Source of the high-side MOSFET. LX serves as the lower supply rail for the
UGATE high-side gate driver. LX is the current-sense input for the PWM.
12~15,
19
PGND
Power Ground of The LGATE Low-Side MOSFET Drivers.
20
BOOT
Supply Input for The UGATE Gate Driver and an internal level-shift circuit. Connect to an external capacitor
to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.
21
VCC
Supply Voltage Input Pin for Control Circuitry, Connect +5V from the VCC pin to the GND pin. Decoupling at
least 1µF of a MLCC capacitor from the VCC pin to the AGND pin.
23
SS
Power-Good Output Pin of PWM. POK is an open-drain output used to indicate the status of the PWM
output voltage. Connect the POK in to +5V through a pull-high resistor.
PWM Enable. PWM is enabled when EN=1. When EN=0, PWM is in shutdown.
PFM Selection Input. When the PFM is above high logic level, the Device is in force PWM mode. When the
PFM is below low logic level, the device is in automatic PFM/PWM Mode.
Signal Ground for The IC.
Output Voltage Feedback Pin. This pin is connected to the resistive divider that set the desired output
voltage. The POK, UVP, and OVP circuits detect this signal to report output voltage status.
This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor RTON from TON pin to VIN pin.
Soft Start Output. Connect a capacitor to GND to set the soft start interval.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
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APW8713CA
Block Diagram
POK
LX
TON
PFM
GND
125% VREF
Mean Value
Circuit
Delay
Current
Limit
Reference
90% VREF
OV
UV
70% VREF
FB
VIN
Fault
Latch
Logic
VCC
BOOT
PWM Signal Controller
125% VREF
Thermal
Shutdown
On-Time
Generator
LDO
ZC
Error
Comparator
PFM
UG
Gate
Driver
LX
VCC
LX
VREF
EN
POR
VLX
LG
Soft-Start
Gate
Driver
PGND
VCC
SS
Copyright  ANPEC Electronics Corp.
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APW8713CA
Typical Application Circuit
When Vin=19V, Dual Power Input :
19V
VIN
EN
CIN
10uF /25V X 4
(MLCC)
Mode
Selection
PFM
100K
TON
5V
VCC
VOUT
LOUT
1.0uH
APW8713CA
1.058V, 10A
LX
CVCC
1uF
CBOOT
0.1uF
RPOK
RTOP
20k
100k
BOOT
COUT1
150uF
COUT2
22uFx4
POK
FB
RGND
62k
SS
AGND
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
PGND
12
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APW8713CA
Typical Application Circuit
When Vin=5V, Single Power Input :
5V
VIN
EN
CIN
10uF /12V X 4
(MLCC)
PFM
100K
Mode
Selection
TON
VCC
VOUT
LOUT
1.0uH
1.058V, 10A
LX
CVCC
1uF
CBOOT
0.1uF
APW8713CA
RPOK
RTOP
20k
100k
BOOT
COUT1
150uF
COUT2
22uFx4
POK
FB
RGND
62k
SS
AGND
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
PGND
13
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APW8713CA
Function Description
Constant-On-Time PWM Controller with Input Feed-
Where FSW is the nominal switching frequency of the
Forward
converter in PWM mode.
The load current at handoff from PFM to PWM mode is
The constant on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This ar-
given by:
chitecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resistor,
1 VIN - VOUT
×
× TON-PFM
2
L
V -V
V
1
= IN OUT ×
× OUT
2L
FSW
VIN
ILOAD (PFM to PWM) =
so the output ripple voltage provides the PWM ramp signal.
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input
Forced-PWM Mode
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
The Forced-PW M mode disables the zero-crossing
comparator, which truncates the low-side switch on-time
at the inductor current zero crossing. This causes the
a switching frequency control circuit in the on-time generator block.
low-side gate-drive waveform to become the complement
of the high-side gate-drive waveform. This in turn causes
The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulat-
the inductor current to reverse at light loads while UG
maintains a duty factor of VOUT/VIN. The benefit of Forced-
ing it at a constant frequency in PWM mode. The design
improves the frequency variation and is more outstand-
PWM mode is to keep the switching frequency fairly
constant. The Forced-PWM mode is most useful for re-
ing than a conventional constant on-time controller, which
has large switching frequency variation over input voltage,
ducing audio frequency noise, improving load-transient
response, and providing sink-current capability for dy-
output current and temperature. Both in PFM and PWM,
the on-time generator, which senses input voltage on
VIN pin, provides very fast on-time response to input line
namic output voltage adjustment.
When V PFM is above the PFM high threshold (2.5V,
minimum), the converter is in forced-PWM mode. When
transients.
Another one-shot sets a minimum off-time (typical:
VPFM is below the PFM low threshold (0.5V, maximum),
the chip is in automatic PFM/PWM Mode.
250ns). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time oneshot has timed out.
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
Over-Current Protection of the PWM Converter
In PFM mode, an automatic switchover to pulse-frequency
wrong logic controls when the VCC voltage is low. The
POR function continually monitors the bias supply volt-
modulation (PFM) takes place at light loads. This
switchover is affected by a comparator that truncates the
age on the VCC pin if at least one of the enable pins is set
high. When the rising VCC voltage reaches the rising
low-side switch on-time at the inductor current zero
crossing. This mechanism causes the threshold between
POR voltage threshold (4.35V, typical), the POR signal
goes high and the chip initiates soft-start operations.
PFM and PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
Should this voltage drop lower than 4.25V (typical), the
POR disables the chip.
operation (also known as the critical conduction point).
The on-time of PFM is given by:
En Pin Control
W hen V EN is above the EN high threshold (2.5V,
TON -PFM =
1
FSW
×
minimum), the converter is enabled. When VEN is below
the EN low threshold (0.5V, maximum), the chip is in the
VOUT
VIN
shutdown and only low leakage current is taken from
VCC.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
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APW8713CA
Function Description (Cont.)
Soft-Start
Under-Voltage Protection (UVP)
The APW8713CA provides the programmed soft-start
In the process of operation, if a short circuit occurs, the
function to limit the inrush current. The soft-start time can
be programmed by the external capacitor between SS
output voltage will drop quickly. When load current is bigger than current limit threshold value, the output voltage
and GND. Typical charge current is 10uA, and the softstart time can be calculated by the following formula:
will fall out of the required regulation range. The undervoltage protection circuit continually monitors the FB voltage after soft-start is completed. If a load step is strong
enough to pull the output voltage lower than the under
TSS (µs) = 330 × CSS (nF)
voltage threshold, the under voltage threshold is 70% of
the nominal output voltage, the internal UVP delay counter
The APW8713CA integrates soft-start circuits to ramp up
the output voltage of the converter to the programmed
starts to count. After 16ms de-bounce time, the device
turns off both high side and low-side MOSEFET with
regulation set point at a predictable slew rate. The slew
rate of output voltage is internally controlled to limit the
latched. Toggling enable pin to low, or recycling VIN, will
clear the latch and bring the chip back to operation.
inrush current through the output capacitors during softstart process. When the EN pin is pulled above the rising
EN threshold voltage, the device initiates a soft-start process to ramp up the output voltage.
Over-Voltage Protection (OVP)
The over voltage function monitors the output voltage by
FB pin. Should the FB voltage increase over 125% of the
During soft-start stage before the PGOOD pin is ready,
the under voltage protection is prohibited. The over volt-
reference voltage due to the high-side MOSFET failure or
for other reasons, the over voltage protection comparator
age and current limit protection functions are enabled. If
the output capacitor has residue voltage before startup,
designed with a 3µs noise filter will force the low-side
both low-side and high-side MOSFETs are in off-state
until the soft start voltage equal the VFB voltage. This will
MOSFET gate driver fully turn on and latch high. This action actively pulls down the output voltage.
ensure the output voltage starts from its existing voltage
level.
This OVP scheme only clamps the voltage overshoot,
and does not invert the output voltage when otherwise
In the event of under-voltage, over-voltage, over-temperature or shutdown, the chip enables the soft-stop function.
activated with a continuously high output from low-side
MOSFET driver. It’s a common problem for OVP schemes
The soft-stop function discharges the output voltages by
low side turns MOSFET on linearly.
with a latch. Once an over-voltage fault condition is set, it
can only be reset by toggling EN or VIN power-on-reset
signal.
Power Good Indicator
POK is actively held low in shutdown and soft-start status.
Current Limit
In the soft-start process, the POK is an open-drain. When
the soft-start is finished, the POK is released. In normal
The current limit circuit employs a "valley" current-sensing algorithm (See Figure 1). The APW8713CA uses the
low-side MOSFET’s RDS(ON) of the synchronous rectifier
operation, the POK window is from 90% to 125% of the
converter reference voltage. When the output voltage has
as a current-sensing element. If the magnitude of the
current-sense signal at LX pin is above the current-limit
to stay within this window, POK signal will become high.
When the output voltage outruns 90% or 125% of the
threshold 11A(minimum), the PWM is not allowed to initiate a new cycle. The actual peak current is greater than
target voltage, POK signal will be pulled low immediately.
In order to prevent false POK drop, capacitors need to
the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit char-
parallel at the output to confine the voltage deviation with
severe load step transient.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
acteristic and maximum load capability are a function of
the sense resistance, inductor value, and input voltage.
15
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APW8713CA
Function Description (Cont.)
Programming the On-Time Control and PWM Switch-
Current Limit( Cont.)
ing Frequency
INDUCTOR CURRENT
IPEAK
IOUT
The APW8713CA does not use a clock signal to produce
PWM. The device uses the constant on-time control architecture to produce pseudo-fixed frequency with input
voltage feed-forward. The on-time pulse width is propor-
ΔI
tional to output voltage VOUT and inverse proportional to
input voltage VIN. In PWM, the on-time calculation is writ-
ILIMIT
ten as below equation.
0
Time
TON =
Figure 1. Current Limit algorithm
26.3 × 10-12 × RTON(Ω)
VIN(V)
Where:
RTON is the resistor connected from TON pin to VIN pin.
The PWM controller uses the low-side MOSFETs on-re-
Furthermore, The approximate PWM switching frequency
is written as:
sistance R DS(ON) to monitor the current for protection
against shorted outputs. The MOSFET’s RDS(ON) is varied
by temperature and gate to source voltage, the user
should determine the maximum RDS(ON) in manufacture’s
TON =
datasheet.
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at LX.
Place the hottest power MOSEFTs as close to the IC as
D
，FSW =
FSW
VOUT
VIN
TON
Where:
FSW is the PWM switching frequency.
possible for best thermal coupling. When combined with
the under-voltage protection circuit, this current-limit
method is effective in almost every circumstance.
Over-Temperature Protection (OTP)
When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the over
temperature protection state that suspends the PWM,
which forces the UG and LG gate drivers output low. The
thermal sensor allows the converters to start a start-up
process and regulate the output voltage again after the
junction temperature cools by 45oC. The OTP designed
with a 45oC hysteresis lowers the average TJ during continuous thermal overload conditions, which increases lifetime of the APW8713CA.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
16
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APW8713CA
Application Information
Output Inductor Selection
A good starting point is to choose the ripple current to be
The output voltage is adjustable from 0.8V to 12V with a
approximately 30% of the maximum output current. Once
the inductance value has been chosen, selecting an in-
resistor-divider connected with FB, GND, and converterˇ¦s
output. Using 1% or better resistors for the resistor-di-
ductor that is capable of carrying the required peak current without going into saturation.In some types of
vider is recommended. The output voltage is determined
by:
VOUT = 0.8 × (1 +
inductors, especially core that is made of ferrite, the ripple
current will increase abruptly when it saturates. This results in a larger output ripple voltage. Besides, the inductor needs to have low DCR to reduce the loss of efficiency.
R TOP
)
R GND
Where 0.8 is the reference voltage, RTOP is the resistor
connected from converter¡¦s output to FB, and RGND is the
Output Capacitor Selection
resistor connected from FB to GND. Suggested RGND is in
the range from 1k to 20kΩ. To prevent stray pickup, locate
are factors that have to be taken into consideration when
selecting an output capacitor. Higher capacitor value and
resistors RTOP and RGND close to APW8713CA.
lower ESR reduce the output ripple and the load transient
drop. Therefore, selecting high performance low ESR
Output voltage ripple and the transient voltage deviation
capacitors is recommended for switching regulator
applications. In addition to high frequency noise related
Output Inductor Selection
The duty cycle (D) of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
to MOSFET turn-on and turnoff, the output voltage ripple
includes the capacitance voltage drop ∆VCOUT and ESR
is fixed, it can be written as:
D=
voltage drop ∆V ESR caused by the AC peak-to-peak
inductor’s current. These two voltages can be represented
VOUT
VIN
by:
∆COUT =
The inductor value (L) determines the inductor ripple
current, IRIPPLE, and affects the load transient response.
Higher inductor value reduces the inductorˇ¦s ripple cur-
∆VESR = IRIPPLE × RESR
rent and induces lower output ripple voltage. The ripple
current and ripple voltage can be approximated by:
IRIPPLE =
IRIPPLE
8 × COUT × FSW
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
VIN - VOUT VOUT
×
FSW × L
VIN
ESR value. If the output of the converter has to support
another load with high pulsating current, more capacitors
Where FSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased
are needed in order to reduce the equivalent ESR and
suppress the voltage ripple to a tolerable level. A small
and the ripple current and voltage are reduced, a tradeoff
exists between the inductor’s ripple current and the regu-
decoupling capacitor (1µF) in parallel for bypassing the
noise is also recommended, and the voltage rating of the
lator load transient response time.
A smaller inductor will give the regulator a faster load
output capacitors are also must be considered.
To support a load transient that is faster than the switch-
transient response at the expense of higher ripple current.
Increasing the switching frequency (FSW ) also reduces
ing frequency, more capacitors are needed for reducing
the voltage excursion during load step change. Another
the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipa-
aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the
tion of the converter. The maximum ripple current occurs
at the maximum input voltage.
rated RMS current specified on the capacitors in order to
prevent the capacitor from over-heating.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
17
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APW8713CA
Application Information (Cont.)
Input Capacitor Selection
Layout Consideration
The input capacitor is chosen based on the voltage rating
In any high switching frequency converter, a correct layout is important to ensure proper operation of the
and the RMS current rating. For reliable operation, selecting the capacitor voltage rating to be at least 1.3 times
regulator. W ith power devices switching at higher
frequency, the resulting current transient will cause volt-
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2,
age spike across the interconnecting impedance and
parasitic circuit elements. As an example, consider the
where IOUT is the load current. During power-up, the input
capacitors have to handle great amount of surge current.
turn-off transition of the PWM MOSFET. Before turn-off
condition, the MOSFET is carrying the full load current.
For low-duty notebook applications, ceramic capacitor is
recommended. The capacitors must be connected be-
During turn-off, current stops flowing in the MOSFET and
is freewheeling by the low side MOSFET and parasitic
tween the drain of high-side MOSFET and the source of
low-side MOSFET with very low-impedance PCB layout.
diode. Any parasitic inductance of the circuit generates a
large voltage spike during the switching interval. In
Thermal Consideration
Because the APW8713CA build-in high-side and lowside MOSFET, the heat dissipated may exceed the maxi-
general, using short and wide printed circuit traces should
minimize interconnecting impedances and the magnitude of voltage spike. Besides, signal and power grounds
are to be kept separate and finally combined using ground
mum junction temperature of the part in applications. If
the junction temperature reaches approximately 150oC,
plane construction or single point grounding. The best
tie-point between the signal ground and the power ground
both power switches will be turned off and the LX node
will become high impedance. To avoid the APW8713CA
from exceeding the maximum junction temperature, the
is at the negative side of the output capacitor on each
channel, where there is less noise. Noisy traces beneath
user will need to do some thermal analysis. The goal of
the thermal analysis is to determine whether the power
the IC are not recommended. Below is a checklist for
your layout:
- Keep the switching nodes (BOOT and LX) away from
dissipated exceeds the maximum junction temperature
of the part. The main power dissipated by the part is
sensitive small signal nodes since these nodes are
fast moving signals. Therefore, keep traces to these
approximated:
nodes as short as possible and there should be no
other weak signal traces in parallel with theses traces
2
PUPPER = IOUT
(1 + TC)(RDS(ON) )D + 0.5(IOUT )(VIN )(tSW )FSW
on any layer.
- The large layout plane between the drain of the MOSFETs
2
PLOWER = IOUT
(1 + TC)(RDS(ON) )(1- D)
IOUT is the load current
(VIN and LX nodes) can get better heat sinking.
- The current sense resistor should be close to OCSET
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
pin to avoid parasitic capacitor effect and noise coupling.
- Decoupling capacitors, the resistor-divider, and boot
tSW is the switching interval
capacitor should be close to their pins.
- The output bulk capacitors should be close to the loads.
D is the duty cycle
Note that both internal MOSFETs have conduction losses
The input capacitor’s ground should be close to the
grounds of the output capacitors.
while the upper MOSFET include an additional transition
loss. The switching internal, t SW , is the function of the
- Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces
reverse transfer capacitance CRSS. The (1+TC) term factors in the temperature dependency of the RDS(ON) and can
can’t be close to the switching signal traces (BOOT and
LX).
be extracted from the "RDS(ON) vs. Temperature" curve
of the power MOSFET. In APW8713CA case, the RDS(ON) is
about 30mW from specification table.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
18
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APW8713CA
Application Information (Cont.)
Recommended Minimum Footprint
TQFN4x4-23
Unit:mm
4mm
ThermalVia
diameter
0.3mm X 12
0.4 *
0.4
0.25
-
1.35
0.25
0.95
0.25
0.3
0.4
2.7
2.95
4mm
0.5
0.25
0.5
0.2
* Just Recommend
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
19
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APW8713CA
Package Information
TQFN4x4-23
D
b
E
A
Pin 1
A1
A3
E1
NX
aaa C
L K E2
e
Pin 1 Corner
D1
D2
S
Y
M
B
O
L
A
TQFN4x4-23
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
0.70
0.80
0.028
0.032
A1
0.00
0.05
0.000
0.002
A3
b
0.20 REF
0.20
0.30
0.008 REF
0.008
0.012
D
3.90
4.10
0.154
0.161
D1
2.58
2.78
0.102
0.109
D2
E
2.95
3.15
0.116
0.124
3.90
4.10
0.154
0.161
E1
1.24
1.44
0.049
0.057
E2
0.85
1.05
0.033
0.041
e
L
0.50 BSC
0.35
0.45
0.020 BSC
0.014
0.018
K
0.20
0.008
aaa
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
0.003
0.08
20
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APW8713CA
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN4x4
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.50±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.00±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±0.20
4.30±0.20
1.00±0.20
4.00±0.10
8.00±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TQFN4x4
Tape & Reel
3000
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
21
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APW8713CA
Taping Direction Information
TQFN4x4
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
22
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APW8713CA
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
23
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW8713CA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2016
24
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