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ispLSI 2096/A
In-System Programmable High Density PLD
Features
Functional Block Diagram
• ENHANCEMENTS
Output Routing Pool (ORP)
—
—
—
—
—
4000 PLD Gates
96 I/O Pins, Six Dedicated Inputs
96 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
Output Routing Pool (ORP)
C4
C3
S
B7
A1
A2
C0
GLB
Logic
Array
D Q
Global Routing Pool
(GRP)
D Q
D Q
A3
A5
A6
A7
D
B0
B1
B2
B6
B5
B4
B3
Output Routing Pool (ORP)
0919/2096
Description
EW
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
R
N
The ispLSI 2096 and 2096A are High Density Programmable Logic Devices. The devices contain 96 Registers,
96 Universal I/O pins, six Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2096 and 2096A feature 5V insystem programmability and in-system diagnostic
capabilities. The ispLSI 2096 and 2096A offer nonvolatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
FO
• IN-SYSTEM PROGRAMMABLE
C1
D Q
Output Routing Pool (ORP)
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
C2
A0
A4
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—
—
—
—
—
—
—
C5
Output Routing Pool (ORP)
• HIGH DENSITY PROGRAMMABLE LOGIC
C6
ES
IG
N
Output Routing Pool (ORP)
C7
96
E
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
20
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…C7
(Figure 1). There are a total of 24 GLBs in the ispLSI 2096
and 2096A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
U
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— Complete Programmable Device Can Combine
Glue Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2096_09
1
August 2006
Select devices have been discontinued.
See Ordering Information section for product status.
— ispLSI 2096A is Fully Form and Function Compatible
to the ispLSI 2096, with Identical Timing
Specifcations and Packaging
— ispLSI 2096A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
Specifications ispLSI 2096/A
Functional Block Diagram
C7
C4
C5
C3
C2
A2
S
IN 5
IN 4
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
B5
Output Routing Pool (ORP)
RESET
R
A7
A6
Input Bus
B0
FO
A5
I/O 59
I/O 58
I/O 57
I/O 56
Input Bus
B6
EW
A1
Output Routing Pool (ORP)
Global
Routing
Pool
(GRP)
A4
SDO
C0
C1
B7
A3
SDI/IN 0
MODE/IN 1
I/O 71
I/O 70
I/O 69
I/O 68
I/O 75
I/O 74
I/O 73
I/O 72
I/O 79
I/O 78
I/O 77
I/O 76
I/O 83
I/O 82
I/O 81
I/O 80
I/O 87
I/O 86
I/O 85
I/O 84
C6
N
I/O 12
I/O 13
I/O 14
I/O 15
Output Routing Pool (ORP)
I/O 8
I/O 9
I/O 10
I/O 11
Output Routing Pool (ORP)
A0
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
Output Routing Pool (ORP)
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
B4
B1
B3
B2
Output Routing Pool (ORP)
CLK 0
CLK 1
CLK 2
I/O 0
I/O 1
I/O 2
I/O 3
Input Bus
Input Bus
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
0917
Y0
Y1
Y2
I/O 44
I/O 45
I/O 46
I/O 47
I/O 40
I/O 41
I/O 42
I/O 43
I/O 36
I/O 37
I/O 38
I/O 39
I/O 32
I/O 33
I/O 34
I/O 35
IN 2
SCLK/IN 3
E
I/O 28
I/O 29
I/O 30
I/O 31
96
I/O 24
I/O 25
I/O 26
I/O 27
20
I/O 20
I/O 21
I/O 22
I/O 23
I/O 16
I/O 17
I/O 18
I/O 19
ispEN
is
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The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
U
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Clocks in the ispLSI 2096 and 2096A devices are selected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096 and 2096A device contains three Megablocks.
2
Select devices have been discontinued.
See Ordering Information section for product status.
Generic Logic
Blocks (GLBs)
Input Bus
D
ES
IG
N
Megablock
I/O 91
I/O 90
I/O 89
I/O 88
I/O 95
I/O 94
I/O 93
I/O 92
GOE 1
GOE 0
Figure 1. ispLSI 2096/A Functional Block Diagram
Specifications ispLSI 2096/A
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
S
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
PARAMETER
VIL
VIH
Input Low Voltage
Input High Voltage
MAX.
UNITS
TA = 0°C to + 70°C
4.75
5.25
V
Industrial
TA = -40°C to + 85°C
4.5
5.5
V
0
0.8
V
2.0
Vcc+1
V
Table 2 - 0005/2096
96
E
Capacitance (TA=25°C, f=1.0 MHz)
MIN.
Commercial
N
Supply Voltage
FO
Vcc
R
SYMBOL
EW
DC Recommended Operating Condition
SYMBOL
PARAMETER
UNITS
8
pf
VCC = 5.0V, VI/O, IN = 2.0V
Clock Capacitance
15
pf
VCC = 5.0V, VY = 2.0V
is
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20
C1
C2
TYPICAL
I/O and Dedicated Input Capacitance
TEST CONDITIONS
Table 2-0006a
Data Retention Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
20
–
Years
10000
–
Cycles
Data Retention
U
SE
Erase/Reprogram Cycles
Table 2-0008A-isp
3
Select devices have been discontinued.
See Ordering Information section for product status.
D
ES
IG
N
Storage Temperature ................................ -65 to 150°C
Specifications ispLSI 2096/A
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
Input Rise and Fall Time
10% to 90%
-125
≤ 2 ns
Others
≤ 3 ns
Input Timing Reference Levels
+ 5V
R1
1.5V
Device
Output
See Figure 2
Table 2-0003/2096
3-state levels are measured 0.5V from
steady-state active level.
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
A
B
C
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
*CL includes Test Fixture and Probe Capacitance.
0213/2096
EW
R2
N
R1
R
TEST CONDITION
CL*
R2
Output Load Conditions (see Figure 2)
Test
Point
FO
Table 2-0004/2096
DC Electrical Characteristics
SYMBOL
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
Output Low Voltage
ICC2, 4
Output High Voltage
20
PARAMETER
96
E
Over Recommended Operating Conditions
CONDITION
3
MIN.
TYP.
IOL= 8 mA
–
–
MAX. UNITS
0.4
V
IOH = -4 mA
2.4
–
–
V
-10
μA
0V ≤ VIN ≤ VIL (Max.)
–
–
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
–
–
10
μA
ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-150
μA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
μA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
Commercial
–
150
295
mA
fCLOCK
Industrial
–
150
–
mA
= 1 MHz
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Input or I/O Low Leakage Current
Table 2-0007/2096
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at VCC = 5V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I CC .
4
Select devices have been discontinued.
See Ordering Information section for product status.
Output Load
D
ES
IG
N
Output Timing Reference Levels
S
1.5V
Specifications ispLSI 2096/A
External Timing Parameters
Over Recommended Operating Conditions
4
7.5
–
125
2
Data Propagation Delay
A
3
Clock Frequency with Internal Feedback 3
–
4
Clock Frequency with External Feedback ( tsu2 + tco1)
100
–
5
Clock Frequency, Max. Toggle
125
–
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
5.0
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
9
GLB Reg. Setup Time before Clock
6.0
–
10 GLB Reg. Clock to Output Delay
–
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
N
15 Product Term OE, Disable
R
14 Product Term OE, Enable
–
15.0
10.0
–
–
100
13.0
–
18.5
ns
–
81.0
MHz
–
77.0
–
57.0
–
MHz
–
100
–
83.0
–
MHz
–
6.5
–
9.0
–
ns
4.0
–
5.0
–
6.5
ns
–
0.0
–
0.0
–
ns
–
8.0
–
11.0
–
ns
–
6.0
–
8.0
ns
0.0
–
0.0
–
0.0
–
ns
–
10.0
–
13.5
–
17.0
ns
5.0
–
6.5
–
10.0
–
ns
–
12.0
–
15.0
–
18.0
ns
–
12.0
–
15.0
–
18.0
ns
–
7.0
–
9.0
–
12.0
ns
–
7.0
–
9.0
–
12.0
ns
–
ns
–
ns
B
16 Global OE, Enable
C
17 Global OE, Disable
–
18 External Synchronous Clock Pulse Duration, High
4.0
–
5.0
–
6.0
–
19 External Synchronous Clock Pulse Duration, Low
4.0
–
5.0
–
6.0
E
96
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
is
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5
–
ns
4.5
EW
1
10.0
D
ES
IG
N
A
–
UNITS
S
–
Data Propagation Delay, 4PT Bypass, ORP Bypass
B
-80
MIN. MAX. MIN. MAX. MIN. MAX.
1
C
-100
-125
1
A
20
1.
2.
3.
4.
DESCRIPTION
Table 2-0030/2096
Select devices have been discontinued.
See Ordering Information section for product status.
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
TEST
2
#
COND.
FO
PARAMETER
Specifications ispLSI 2096/A
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
-100
-125
DESCRIPTION
-80
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
Inputs
0.2
–
0.5
–
21 Dedicated Input Delay
–
1.5
–
2.2
–
22 GRP Delay
–
23 4 Product Term Bypass Comb. Path Delay
GRP
tgrp
–
2.6
ns
–
4.5
–
5.8
–
8.1
ns
24 4 Product Term Bypass Reg. Path Delay
–
5.0
–
5.8
–
6.8
ns
25 1 Product Term/XOR Path Delay
–
5.7
–
6.8
–
8.0
ns
26 20 Product Term/XOR Path Delay
–
6.0
–
7.3
–
8.8
ns
–
6.5
–
8.0
–
9.8
ns
–
0.5
–
0.5
–
1.3
ns
0.8
–
1.2
–
1.4
–
ns
3.0
–
4.0
–
6.0
–
ns
–
0.2
–
0.3
–
0.4
ns
–
1.1
–
1.3
–
1.6
ns
–
4.8
–
6.1
–
8.6
ns
N
29 GLB Register Setup Time before Clock
31 GLB Register Clock to Output Delay
FO
32 GLB Register Reset to Output Delay
R
30 GLB Register Hold Time after Clock
33 GLB Product Term Reset to Register Delay
–
7.3
–
8.6
–
9.0
ns
3.3
5.6
4.1
7.1
5.6
10.2
ns
–
0.8
–
1.4
–
2.0
ns
–
0.3
–
0.4
–
0.5
ns
38 Output Buffer Delay
–
1.2
–
1.6
–
2.0
ns
39 Output Slew Limited Delay Adder
–
10.0
–
10.0
–
10.0
ns
40 I/O Cell OE to Output Enabled
–
3.2
–
4.2
–
4.6
ns
41 I/O Cell OE to Output Disabled
–
3.2
–
4.2
–
4.6
ns
42 Global Output Enable
–
3.8
–
4.8
–
7.4
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. Clock)
2.3
2.3
2.7
2.7
3.6
3.6
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.3
2.3
2.7
2.7
3.6
3.6
ns
–
6.9
–
9.2
–
11.4
ns
34 GLB Product Term Output Enable to I/O Cell Delay
36 ORP Delay
20
37 ORP Bypass Delay
96
E
35 GLB Product Term Clock Delay
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tgy0
tgy1/2
EW
28 GLB Register Bypass Delay
Outputs
Clocks
ns
1.7
ORP
tob
tsl
toen
todis
tgoe
4.4
–
27 XOR Adjacent Path Delay 3
torp
torpbp
ns
1.3
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
1.8
S
–
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Table 2-0036/2096
Select devices have been discontinued.
See Ordering Information section for product status.
20 Input Buffer Delay
D
ES
IG
N
tio
tdin
Specifications ispLSI 2096/A
ispLSI 2096/A Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
#21
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
GLB Reg
Delay
D
#25, 26, 27
ORP
Delay
Q
RST
#45
Reset
#29, 30,
31, 32
#43, 44
Y0,1,2
R
N
#42
GOE 0,1
FO
Derivations of tsu, th and tco from the Product Term Clock
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3)
th
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0)
tco
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2)
96
is
pL
SI
=
=
=
9.3 ns =
20
=
=
=
2.6 ns =
E
tsu
=
=
=
3.5 ns =
Note: Calculations are based upon timing specifications for the ispLSI 2096/A-125L.
U
SE
Table 2-0042B/2096
7
#36
EW
Control RE
PTs
OE
#33, 34, CK
35
#38,
39
D
ES
IG
N
GRP
#40, 41
0491/2000
I/O Pin
(Output)
Select devices have been discontinued.
See Ordering Information section for product status.
I/O Pin
(Input)
I/O Delay
S
Ded. In
Specifications ispLSI 2096/A
Power Consumption
Power consumption in the ispLSI 2096 and 2096A devices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
ispLSI 2096/A
200
150
100
EW
ICC (mA)
250
50
20
40
60
80
100 120 140
N
0
fmax (MHz)
FO
R
Notes: Configuration of six 16-bit counters
Typical current at 5V, 25°C
ICC can be estimated for the ispLSI 2096/A using the following equation:
E
ICC(mA) = 20 + (# of PTs * 0.67) + (# of nets * Max freq * 0.011)
20
96
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
is
pL
SI
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
U
SE
0127/2096
8
Select devices have been discontinued.
See Ordering Information section for product status.
300
D
ES
IG
N
S
Figure 4. Typical Device Power Consumption vs fmax
Specifications ispLSI 2096/A
Pin Description
NAME
PQFP & TQFP PIN NUMBERS
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
26
32
39
45
57
63
71
77
90
96
103
109
122
128
7
13
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
GOE 0, GOE 1
64,
114
IN 2, IN 4, IN 5
51,
84,
ispEN
18
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
SDI/IN 02
20
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN0 also is used as one of the two control pins for the isp state
machine. When ispEN is high, it functions as a dedicated input pin.
MODE/IN 12
46
SDO
50
SCLK/IN 32
78
RESET
19
Y0, Y1, Y2
15
VCC
NC1
D
ES
IG
N
S
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Global Output Enables input pins.
EW
Dedicated input pins to the device.
FO
R
N
110
83,
20
96
E
Input - This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the isp state machine.
When ispEN is high, it functions as a dedicated input pin.
1,
97,
17,
112
33,
49,
16,
48,
82,
113
14,
47,
79,
111,
Output - When ispEN is logic low, it functions as an output pin to read
serial shift register data.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
80
is
pL
SI
GND
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
65,
81,
Ground (GND)
VCC
115,
116
No Connect.
U
SE
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
9
Table 2-0002-2096
Select devices have been discontinued.
See Ordering Information section for product status.
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
DESCRIPTION
Specifications ispLSI 2096/A
Pin Configuration
D
ES
IG
N
EW
N
R
ispLSI 2096/A
96
E
FO
Top View
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 4
Y1
VCC
GND
Y2
NC1
SCLK/IN 32
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
2MODE/IN 1
1NC
VCC
GND
SDO
IN 2
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GOE 0
U
SE
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
is
pL
SI
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
1NC
Y0
VCC
GND
ispEN
RESET
2SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
0124A-2096
10
Select devices have been discontinued.
See Ordering Information section for product status.
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
S
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
NC1
NC1
GOE 1
VCC
GND
NC1
IN 5
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
ispLSI 2096/A 128-pin PQFP and TQFP Pinout Diagram
Specifications ispLSI 2096/A
Part Number Description
ispLSI XXXXX – XXX
X
X
X
Device Family
Grade
Blank = Commercial
I = Industrial
Package
T = TQFP
Q = PQFP
TN = Lead-Free TQFP
QN = Lead-Free PQFP
Power
L = Low
EW
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
ispLSI 2096/A Ordering Information
N
Conventional Packaging
ORDERING NUMBER
PACKAGE
125
7.5
ispLSI 2096A-125LQ128
128-Pin PQFP
125
7.5
ispLSI 2096A-125LT128
128-Pin TQFP
ispLSI 2096A-100LQ128
128-Pin PQFP
ispLSI 2096A-100LT128
128-Pin TQFP
ispLSI 2096A-80LQ128
128-Pin PQFP
ispLSI 2096A-80LT128
128-Pin TQFP
10
10
81
15
81
15
125
125
E
100
100
FO
tpd (ns)
96
ispLSI
fmax (MHz)
20
FAMILY
R
COMMERCIAL
7.5
7.5
ispLSI
2096-125LQ1
128-Pin PQFP
ispLSI
2096-125LT1
128-Pin TQFP
2096-100LQ1
128-Pin PQFP
10
ispLSI
100
10
ispLSI 2096-100LT1
128-Pin TQFP
15
ispLSI
2096-80LQ1
128-Pin PQFP
ispLSI
2096-80LT1
128-Pin TQFP
is
pL
SI
100
81
81
15
U
SE
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
FAMILY
ispLSI
INDUSTRIAL
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
81
15
ispLSI 2096A-80LQ128I
128-Pin PQFP
81
15
ispLSI 2096A-80LT128I
128-Pin TQFP
81
15
ispLSI 2096-80LQI1
128-Pin PQFP
15
2096-80LTI1
128-Pin TQFP
81
ispLSI
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
11
Select devices have been discontinued.
See Ordering Information section for product status.
Speed
125 = 125 MHz fmax
100 = 100 MHz fmax
80 = 81 MHz fmax
D
ES
IG
N
S
Device Number
20961
2096A
Specifications ispLSI 2096/A
ispLSI 2096/A Ordering Information (Cont.)
Lead-Free Packaging
COMMERCIAL
tpd (ns)
ORDERING NUMBER
PACKAGE
125
7.5
ispLSI 2096A-125LQN128
Lead-Free 128-Pin PQFP
125
7.5
ispLSI 2096A-125LTN128
Lead-Free 128-Pin TQFP
Lead-Free 128-Pin PQFP
100
10
100
10
ispLSI 2096A-100LTN128
81
15
ispLSI 2096A-80LQN128
81
15
ispLSI 2096A-80LTN128
INDUSTRIAL
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
tpd (ns)
ORDERING NUMBER
81
15
ispLSI 2096A-80LQN128I
Lead-Free 128-Pin PQFP
81
15
ispLSI 2096A-80LTN128I
Lead-Free 128-Pin TQFP
ispLSI
EW
fmax (MHz)
N
FAMILY
Lead-Free 128-Pin TQFP
R
Revision History
Version
—
08
Previous Lattice release.
August 2006
09
Updated for lead-free package options.
U
SE
is
pL
SI
20
96
E
FO
Date
12
Change Summary
PACKAGE
Select devices have been discontinued.
See Ordering Information section for product status.
ispLSI
ispLSI 2096A-100LQN128
S
fmax (MHz)
D
ES
IG
N
FAMILY