® RT7274/79/80/81 2A, 18V, 700kHz ACOTTM Synchronous Step-Down Converter General Description Features The RT7274/79/80/81 is a synchronous step-down DC/ DC converter with Advanced Constant On-Time (ACOTTM) z mode control. It achieves high power density to deliver up to 2A output current from a 4.5V to 18V input supply. The proprietary ACOTTM mode offers an optimal transient response over a wide range of loads and all kinds of ceramic capacitors, which allows the device to adopt very low ESR output capacitor for ensuring performance stabilization. In addition, RT7274/79/80/81 keeps an excellent constant switching frequency under line and load variation and the integrated synchronous power switches with the ACOTTM mode operation provides high efficiency in whole output current load range. Cycle-by-cycle current limit provides an accurate protection by a valley detection of low-side MOSFET and external soft-start setting eliminates input current surge during startup. Protection functions include thermal shutdown for RT7274/79/80/81; output under voltage protection and output over voltage protection for RT7279/80 only. z z z z z z z z z z z z z ACOTTM Mode Enables Fast Transient Response 4.5V to 18V Input Voltage Range 2A Output Current High Efficient Internal N-MOSFET Optimized for Lower Duty Cycle Applications 105mΩ Ω Internal Low-Side N-MOSFET Advanced Constant On-Time Control Allows Ceramic Output Capacitor 700kHz Switching Frequency Adjustable Output Voltage from 0.765V to 8V Adjustable and Pre-biased Soft-Start Cycle-by-Cycle Current Limit Input Under Voltage Lockout Thermal Shutdown RoHS Compliant and Halogen Free Applications z z z z z Industrial and Commercial Low Power Systems Computer Peripherals LCD Monitors and TVs Green Electronics/Appliances Point of Load Regulation for High-Performance DSPs, FPGAs, and ASICs Simplified Application Circuit VIN RT7274/79/80/81 VIN SW VINR* Input Signal Power Good EN VOUT BOOT FB GND* PGOOD* PVCC SS VOUT* PGND* * : VINR pin for TSSOP-14 (Exposed Pad) only. VOUT pin for TSSOP-14 (Exposed Pad) only. PGND pin for TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 only. PGOOD pin for TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 only. GND pin for TSSOP-14 (Exposed Pad) and SOP-8 (Exposed Pad) only. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT7274/79/80/81 Ordering Information Marking Information Discontinuous Operating Mode RT7274GSP RT7274 RT7274GSP : Product Number RT7274 GSPYMDNN Package Type SP : SOP-8 (Exposed Pad-Option 2) Lead Plating System G : Green (Halogen Free and Pb Free) YMDNN : Date Code RT7280GCP RT7280GCP : Product Number RT7280 GCPYMDNN RT7280 Package Type CP : TSSOP-14 (Exposed Pad) QW : WDFN-10L 3x3 (W-Type) YMDNN : Date Code RT7280GQW 2Y= : Product Code Lead Plating System G : Green (Halogen Free and Pb Free) 2Y=YM DNN YMDNN : Date Code RT7279GCP Forced PWM Mode RT7279GCP : Product Number RT7279 RT7279 GCPYMDNN Package Type CP : TSSOP-14 (Exposed Pad) QW : WDFN-10L 3x3 (W-Type) YMDNN : Date Code RT7279GQW Lead Plating System G : Green (Halogen Free and Pb Free) 2Z= : Product Code 2Z=YM DNN YMDNN : Date Code RT7281 RT7281GSP Package Type SP : SOP-8 (Exposed Pad-Option 2) RT7281GSP : Product Number RT7281 GSPYMDNN Lead Plating System G : Green (Halogen Free and Pb Free) YMDNN : Date Code Pin Configurations VOUT FB PVCC SS GND PGOOD EN 14 2 13 3 4 12 PGND 11 5 10 6 9 7 15 8 VINR VIN BOOT SW SW PGND PGND EN FB PVCC SS PGOOD TSSOP-14 (Exposed Pad) Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 1 2 3 4 5 PGND (TOP VIEW) 11 10 9 8 7 6 VIN VIN BOOT SW SW WDFN-10L 3x3 EN 8 FB 2 PVCC 3 SS 4 GND 9 VIN 7 BOOT 6 SW 5 GND SOP-8 (Exposed Pad) is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 Functional Pin Description Pin No. Pin Name SOP-8 (Exposed Pad) Pin Function TSSOP-14 (Exposed Pad) WDFN-10L 3x3 1 -- -- VOUT Output Voltage Sense Input. This terminal is used for On-Time Adjustment. 2 2 2 FB Feedback Input Voltage. Connect with feedback resistive divider to the output voltage. 3 3 3 PVCC 5.1V Power Supply Output. PVCC is the output of the internal 5.1V linear regulator powered by VIN (WDFN-10L 3x3) or VINR (TSSOP-14L (Exposed Pad)). Connect a 1μF capacitor from this pin to GND. 4 4 4 SS Soft-Start Control. Connect an external capacitor between this pin and GND to set the soft- start time. 5 -- 6 5 -- PGOOD Open Drain Power Good Output. 7 1 1 EN Enable Control Input. -- PGND Power Ground. The exposed pad must be soldered to a large PCB and connected to PGND for maximum power dissipation. 8, 9, 11 15 (Exposed Pad) (Exposed Pad) 5, GND 9 (Exposed Pad) Analog Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 10, 11 6, 7 6 SW Switch Node. 12 8 7 BOOT Bootstrap Supply for High-Side Gate Driver. Connect a 0.1μF capacitor between the BOOT and SW pin. 13 9, 10 8 VIN Power Input. It is connected to the drain of the internal high-side MOSFET. Connect VIN to the input capacitor. For the WDFN-10L 3x3 package, VIN also supplies power to the internal linear regulator. 14 -- -- VINR Supply Input for Internal Linear Regulator to the Control Circuitry. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT7274/79/80/81 Function Block Diagram For TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 Package BOOT PVCC VIN (WDFN-10L 3x3) Internal Regulator Over Current Protection PVCC PVCC VIBIAS GND (TSSOP-14 (Exposed Pad)) VOUT (TSSOP-14 (Exposed Pad)) VIN VREF UGATE Under & Over Voltage Protection Discharge PVCC Switch Controller SW Driver LGATE PGND SW Ripple Gen. 2µA 0.9 VREF + FB - - SS FB On-Time FB Comparator PGOOD + - VINR (TSSOP-14 (Exposed Pad)) PGOOD Comparator EN EN For SOP-8 (Exposed Pad) Package BOOT PVCC Internal Regulator PVCC VIBIAS Over Current Protection VIN PVCC VREF UGATE GND Switch Controller PVCC 2µA SW Driver LGATE Ripple Gen. SW + - - SS FB On-Time FB Comparator EN EN Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 Detailed Description The RT7274/79/80/81 are high-performance 700kHz 2A step-down regulators with internal power switches and synchronous rectifiers. They feature an Advanced Constant On-Time (ACOTTM) control architecture that provides stable operation with ceramic output capacitors without complicated external compensation, among other benefits. The input voltage range is from 4.5V to 18V and the output is adjustable from 0.765V to 8V. The proprietary ACOTTM control scheme improves upon other constant on-time architectures, achieving nearly constant switching frequency over line, load, and output voltage ranges. The RT7274/79/80/81 are optimized for ceramic output capacitors. Since there is no internal clock, response to transients is nearly instantaneous and inductor current can ramp quickly to maintain output regulation without large bulk output capacitance. Constant On-Time (COT) Control The heart of any COT architecture is the on-time oneshot. Each on-time is a pre-determined “fixed” period that is triggered by a feedback comparator. This robust arrangement has high noise immunity and is ideal for low duty cycle applications. After the on-time one-shot period, there is a minimum off-time period before any further regulation decisions can be considered. This arrangement avoids the need to make any decisions during the noisy time periods just after switching events, when the switching node (SW) rises or falls. Because there is no fixed clock, the high-side switch can turn on almost immediately after load transients and further switching pulses can ramp the inductor current higher to meet load requirements with minimal delays. Traditional current mode or voltage mode control schemes typically must monitor the feedback voltage, current signals (also for current limit), and internal ramps and compensation signals, to determine when to turn off the high-side switch and turn on the synchronous rectifier. Weighing these small signals in a switching environment is difficult to do just after switching large currents, making those architectures problematic at low duty cycles and in less than ideal board layouts. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 Because no switching decisions are made during noisy time periods, COT architectures are preferable in low duty cycle and noisy applications. However, traditional COT control schemes suffer from some disadvantages that preclude their use in many cases. Many applications require a known switching frequency range to avoid interference with other sensitive circuitry. True constant on-time control, where the on-time is actually fixed, exhibits variable switching frequency. In a step-down converter, the duty factor is proportional to the output voltage and inversely proportional to the input voltage. Therefore, if the on-time is fixed, the off-time (and therefore the frequency) must change in response to changes in input or output voltage. Modern pseudo-fixed frequency COT architectures greatly improve COT by making the one-shot on-time proportional to VOUT and inversely proportional to VIN. In this way, an on-time is chosen as approximately what it would be for an ideal fixed-frequency PWM in similar input/output voltage conditions. The result is a big improvement but the switching frequency still varies considerably over line and load due to losses in the switches and inductor and other parasitic effects. Another problem with many COT architectures is their dependence on adequate ESR in the output capacitor, making it difficult to use highly-desirable, small, low-cost, but low-ESR ceramic capacitors. Most COT architectures use AC current information from the output capacitor, generated by the inductor current passing through the ESR, to function in a way like a current mode control system. With ceramic capacitors the inductor current information is too small to keep the control loop stable, like a current mode system with no current information. ACOTTM Control Architecture Making the on-time proportional to VOUT and inversely proportional to VIN is not sufficient to achieve good constant-frequency behavior for several reasons. First, voltage drops across the MOSFET switches and inductor cause the effective input voltage to be less than the measured input voltage and the effective output voltage to be greater than the measured output voltage. As the load is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT7274/79/80/81 changes, the switch voltage drops change causing a switching frequency variation with load current. Also, at light loads if the inductor current goes negative, the switch dead-time between the synchronous rectifier turn-off and the high-side switch turn-on allows the switching node to rise to the input voltage. This increases the effective ontime and causes the switching frequency to drop noticeably. One way to reduce these effects is to measure the actual switching frequency and compare it to the desired range. This has the added benefit eliminating the need to sense the actual output voltage, potentially saving one pin connection. ACOTTM uses this method, measuring the actual switching frequency and modifying the on-time with a feedback loop to keep the average switching frequency in the desired range. To achieve good stability with low-ESR ceramic capacitors, ACOTTM uses a virtual inductor current ramp generated inside the IC. This internal ramp signal replaces the ESR ramp normally provided by the output capacitor's ESR. The ramp signal and other internal compensations are optimized for low-ESR ceramic output capacitors. ACOTTM One-shot Operation The RT7274/79/80/81 control algorithm is simple to understand. The feedback voltage, with the virtual inductor current ramp added, is compared to the reference voltage. When the combined signal is less than the reference the on-time one-shot is triggered, as long as the minimum off-time one-shot is clear and the measured inductor current (through the synchronous rectifier) is below the current limit. The on-time one-shot turns on the high-side switch and the inductor current ramps up linearly. After the on-time, the high-side switch is turned off and the synchronous rectifier is turned on and the inductor current ramps down linearly. At the same time, the minimum offtime one-shot is triggered to prevent another immediate on-time during the noisy switching time and allow the feedback voltage and current sense signals to settle. The minimum off-time is kept short (230ns typical) so that rapidly-repeated on-times can raise the inductor current quickly when needed. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 Discontinuous Operating Mode (RT7274/80 Only) After soft start, the RT7279/81 operates in fixed frequency mode to minimize interference and noise problems. The RT7274/80 uses variable-frequency discontinuous switching at light loads to improve efficiency. During discontinuous switching, the on-time is immediately increased to add “hysteresis” to discourage the IC from switching back to continuous switching unless the load increases substantially. The IC returns to continuous switching as soon as an ontime is generated before the inductor current reaches zero. The on-time is reduced back to the length needed for 700kHz switching and encouraging the circuit to remain in continuous conduction, preventing repetitive mode transitions between continuous switching and discontinuous switching. Current Limit The RT7274/79/80/81 current limit is a cycle-by-cycle “valley” type, measuring the inductor current through the synchronous rectifier during the off-time while the inductor current ramps down. The current is determined by measuring the voltage between source and drain of the synchronous rectifier, adding temperature compensation for greater accuracy. If the current exceeds the upper current limit, the on-time one-shot is inhibited until the inductor current ramps down below the upper current limit plus a wide hysteresis band of about 1A and drops below the lower current limit level. Thus, only when the inductor current is well below the upper current limit is another ontime permitted. This arrangement prevents the average output current from greatly exceeding the guaranteed upper current limit value, as typically occurs with other valley-type current limits. If the output current exceeds the available inductor current (controlled by the current limit mechanism), the output voltage will drop. If it drops below the output under-voltage protection level (see next section) the IC will stop switching to avoid excessive heat. The RT7279/81 also includes a negative current limit to protect the IC against sinking excessive current and possibly damaging the IC. If the voltage across the synchronous rectifier indicates the negative current is too is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 high, the synchronous rectifier turns off until after the next high-side on-time. RT7274/80 does not sink current and therefore does not need a negative current limit. Output Over-voltage Protection and Under-voltage Protection The RT7279/80 include output over-voltage protection (OVP). If the output voltage rises above the regulation level, the high-side switch naturally remains off and the synchronous rectifier turns on. If the output voltage remains high the synchronous rectifier remains on until the inductor current reaches the negative current limit (RT7279) or until it reaches zero (RT7280). If the output voltage remains high, the IC's switches remain off. If the output voltage exceeds the OVP trip threshold for longer than 5μs (typical), the IC's OVP is triggered. The RT7279/80 include output under-voltage protection (UVP). If the output voltage drops below the UVP trip threshold for longer than 250μs (typical) the IC's UVP is triggered. There are two different behaviors for OVP and UVP events for the TSSOP-14 (Exposed Pad) packages. ` Latch-Off Mode (TSSOP-14 (Exposed Pad) Only) ` The RT7280GCP/RT7279GCP, use latch-off mode OVP and UVP. When the protection function is triggered the IC will shut down. The IC stops switching, leaving both switches open, and is latched off. To restart operation, toggle EN or power the IC off and then on again. ` Hiccup Mode (WDFN-10L 3x3 Only) ` The RT7279GQW/RT7280GQW, use hiccup mode OVP and UVP. When the protection function is triggered, the IC will shut down for a period of time and then attempt to recover automatically. Hiccup mode allows the circuit to operate safely with low input current and power dissipation, and then resume normal operation as soon as the overload or short circuit is removed. Between these 2 levels there are 2 thresholds (1.2V typical and 1.4V typical). When VEN exceeds the lower threshold the internal bias regulators begin to function and supply current increases above the shutdown current level. Switching operation begins when VEN exceeds the upper threshold. Unlike many competing devices, EN is a high voltage input that can be safely connected to VIN (up to 18V) for automatic start-up. Input Under-voltage Lock-out In addition to the enable function, the RT7274/79/80/81 feature an under-voltage lock-out (UVLO) function that monitors the internal linear regulator output (PVCC). To prevent operation without fully-enhanced internal MOSFET switches, this function inhibits switching when PVCC drops below the UVLO-falling threshold. The IC resumes switching when PVCC exceeds the UVLO-rising threshold. Soft-Start (SS) The RT7274/79/80/81 soft-start uses an external pin (SS) to clamp the output voltage and allow it to slowly rise. After VEN is high and PVCC exceeds its UVLO threshold, the IC begins to source 2μA from the SS pin. An external capacitor at SS is used to adjust the soft-start timing. The available capacitance range is from 2.7nF to 220nF. Do not leave SS unconnected. During start-up, while the SS capacitor charges, the RT7274/79/80/81 operate in discontinuous switching mode with very small pulses. This prevents negative inductor currents and keeps the circuit from sinking current. Therefore, the output voltage may be pre-biased to some positive level before start-up. Once the VSS ramp charges enough to raise the internal reference above the feedback voltage, switching will begin and the output voltage will smoothly rise from the pre-biased level to its regulated level. After VSS rises above about 2.2V output over-and under-voltage protections are enabled and the RT7279/81 begins continuous-switching operation. Shut-down, Start-up and Enable (EN) Internal Regulator (PVCC) The enable input (EN) has a logic-low level of 0.4V. When VEN is below this level the IC enters shutdown mode and supply current drops to less than 10μA. When VEN exceeds its logic-high level of 1.6V the IC is fully operational. An internal linear regulator (PVCC) produces a 5.1V supply from VIN that powers the internal gate drivers, PWM logic, reference, analog circuitry, and other blocks. If VIN is 6V or greater, PVCC is guaranteed to provide significant power for external loads. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT7274/79/80/81 PGOOD Comparator PGOOD is an open drain output controlled by a comparator connected to the feedback signal. If FB exceeds 90% of the internal reference voltage, PGOOD will be high impedance. Otherwise, the PGOOD output is connected to PGND. External Bootstrap Capacitor (C6) Connect a 0.1μF low ESR ceramic capacitor between BOOT and SW. This bootstrap capacitor provides the gate driver supply voltage for the high-side N-channel MOSFET switch. Over Temperature Protection The RT7274/79/80/81 includes an Over Temperature Protection (OTP) circuitry to prevent overheating due to excessive power dissipation. The OTP will shut down switching operation when the junction temperature exceeds 150°C. Once the junction temperature cools down by approximately 25°C the IC will resume normal operation with a complete soft-start. For continuous operation, provide adequate cooling so that the junction temperature does not exceed 150°C. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 Absolute Maximum Ratings z z z z z z z z z z z z (Note 1) Supply Input Voltage, VIN, VINR ------------------------------------------------------------------------------Switch Node, SW -------------------------------------------------------------------------------------------------Switch Node, SW (<10ns) ---------------------------------------------------------------------------------------BOOT to SW, PVCC ---------------------------------------------------------------------------------------------PVCC to VIN (WDFN-10L 3x3) or VINR (TSSOP-14 (Exposed Pad)) ---------------------------------Other Pins -----------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C TSSOP-14 (Exposed Pad) --------------------------------------------------------------------------------------WDFN-10L 3x3 -----------------------------------------------------------------------------------------------------SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) TSSOP-14 (Exposed Pad), θJA --------------------------------------------------------------------------------WDFN-10L 3x3, θJA -----------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC -----------------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJA --------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC -------------------------------------------------------------------------------------Junction Temperature Range ------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) --------------------------------------------------------------------------------------- Recommended Operating Conditions z z z −0.3V to 21V −0.8V to (VIN + 0.3V) −5V to 25V −0.3V to 6V −18V to 0.3V −0.3V to 21V 2.50W 1.67W 2.04W 40°C/W 60°C/W 7.5°C/W 49°C/W 15°C/W 150°C 260°C −65°C to 150°C 2kV (Note 4) Supply Input Voltage, VIN ---------------------------------------------------------------------------------------- 4.5V to 18V Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 12V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Current Supply Current (Shutdown) VEN = 0V -- 1 10 μA Supply Current (Quiescent) VEN = 3V, VFB = 1V -- 0.7 -- mA Logic Threshold EN Voltage Logic-High VIH 1.6 -- 18 Logic-Low VIL -- -- 0.4 220 440 880 EN Pin Resistance to GND (RT7274/81) VEN = 12V V kΩ VFB Voltage and Discharge Resistance Feedback Threshold Voltage VFB_TH 4.5V ≤ VIN ≤ 18V 0.757 Feedback Input Current IFB VFB = 0.8V −0.1 0 0.1 μA VOUT Discharge Resistance RDIS EN = 0V, VVOUT = 0.5V -- 50 100 Ω Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 0.765 0.773 V is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT7274/79/80/81 Parameter Symbol Test Conditions Min Typ Max Unit 4.7 5.1 5.5 V VPVCC Output VPVCC Output Voltage VPVCC 6V ≤ VIN ≤ 18V, 0 < IPVCC < 5mA Line Regulation 6V ≤ VIN ≤ 18V, IPVCC = 5mA -- -- 20 mV Load Regulation 0 < IPVCC < 5mA -- -- 100 mV VIN = 6V, VPVCC = 4V -- 110 -- mA Output Current I PVCC RDS(ON) High-Side RDS(ON) _H -- 150 -- Low-Side RDS(ON) _L -- 105 -- 2.5 3.5 4.7 A Thermal Shutdown Threshold TSD -- 150 -- °C Thermal Shutdown Hysteresis ΔTSD -- 25 -- °C -- 145 -- ns -- 230 -- ns Switch On-Resistance mΩ Current Limit Current Limit ILIM LSW = 2μH Thermal Shutdown On-Time Timer Control On-Time tON Minimum Off-Time tOFF(MIN) VIN = 12V, VOUT = 1.05V Soft-Start SS Charge Current VSS = 0V 1.4 2 2.6 μA SS Discharge Current VSS = 0.5V 0.05 0.1 -- mA Wake up VPVCC 3.55 3.85 4.15 Hysteresis -- 0.3 -- FB Rising 85 90 95 FB Falling -- 85 -- PGOOD = 0.5V -- 5 -- mA 115 120 125 % -- 5 -- μs UVP Detect 65 70 75 Hysteresis -- 10 -- -- 250 -- UVLO UVLO Threshold V Power Good (RT7279/80) PGOOD Threshold PGOOD Sink Current % Output Under Voltage and Over Voltage Protection (RT7279/80) OVP Trip Threshold OVP Detect OVP Delay Time UVP Trip Threshold UVP Delay Time % μs Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. The PCB copper area of exposed pad is 70mm2. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 Typical Application Circuit For TSSOP-14 (Exposed Pad) Package 13 VIN C1 10µF x 2 C2 0.1µF 14 RT7279/80 VIN SW 10, 11 12 BOOT 2 FB VINR Output Signal R3 100k PVCC 6 7 Input Signal 3 C4 1µF 4 C5 3.9nF GND PGOOD EN PVCC VOUT SS PGND L1 2µH C6 0.1µF C3 C7 22µF x 2 R1 8.25k VOUT 1.05V/2A R2 22k 5 1 8, 9, 15 (Exposed Pad) For WDFN-10L 3x3 Package VIN RT7279/80 9, 10 SW 6, 7 VIN C2 0.1µF 8 BOOT C1 10µF x 2 Output Signal PVCC FB R3 100k 5 3 C4 1µF 4 C5 3.9nF PGOOD EN PVCC PGND SS L1 2µH C6 0.1µF C3 C7 22µF x 2 R1 8.25k VOUT 1.05V/2A 2 1 R2 22k Input Signal 11 (Exposed Pad) For SOP-8 (Exposed Pad) Package VIN Enable C1 10µF x 2 C2 0.1µF RT7274/81 6 8 SW VIN 1 EN 5, 9 (Exposed Pad) GND C5 3.9nF 4 SS BOOT 7 FB L1 2µH C6 0.1µF C3 C7 22µF x 2 R1 8.25k VOUT 1.05V/2A 2 PVCC 3 C4 1µF VPVCC R2 22.1k Table 1. Suggested Component Values VOUT (V) R1 (kΩ) R2 (kΩ) C3 (pF) L1 (μH) C7 (μF) 1 6.81 22.1 -- 2 22 to 68 1.05 8.25 22.1 -- 2 22 to 68 1.2 12.7 22.1 -- 2 22 to 68 1.8 30.1 22.1 5 to 22 3.3 22 to 68 2.5 49.9 22.1 5 to 22 3.3 22 to 68 3.3 73.2 22.1 5 to 22 3.3 22 to 68 5 124 22.1 5 to 22 4.7 22 to 68 7 180 22.1 5 to 22 4.7 22 to 68 Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT7274/79/80/81 Typical Operating Characteristics Efficiency vs. Output Current 100 90 90 80 80 70 RT7274/80 Efficiency (%) Efficiency (%) Efficiency vs. Output Current 100 60 50 40 RT7279/81 30 20 RT7274/80 70 60 50 40 RT7279/81 30 20 10 10 VIN = 12V, VOUT = 1.05V, IOUT = 0 to 2A 0 0.001 0.01 0.1 1 VIN = 12V, VOUT = 5V, IOUT = 0 to 2A 0 0.001 10 0.01 Output Current (A) 1.07 0.775 VFB Threshold Voltage (V) Output Voltage (V) 0.780 1.06 1.05 1.04 RT7279 RT7274 RT7280 RT7281 1.01 0.770 0.765 0.760 0.755 0.750 0.745 VIN = 4.5V to 18V, VOUT = 1.05V, IOUT = 1A 0.740 1.00 4 6 8 10 12 14 16 -50 18 -25 Output Voltage vs. Output Current 25 50 75 100 125 Output Voltage vs. Output Current 1.070 5.10 1.065 5.08 1.060 Output Voltage (V) Output Voltage (V) 0 Temperature (°C) Input Voltage (V) RT7279/81 1.055 10 VFB Threshold Voltage vs. Temperature Output Voltage vs. Input Voltage 1.02 1 Output Current (A) 1.08 1.03 0.1 1.050 RT7274/80 1.045 1.040 1.035 5.06 RT7274/80 5.04 5.02 RT7279/81 5.00 4.98 4.96 4.94 VIN = 12V, VOUT = 1.05V, IOUT = 0 to 2A 1.030 VIN = 12V, VOUT = 5V, IOUT = 0 to 2A 4.92 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Output Current (A) Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Output Current (A) is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 Switching Frequency vs. Input Voltage Switching Frequency vs. Temperature 700 690 Switching Frequency (kHz)1 Switching Frequency (KHz)1 700 680 670 660 650 640 630 620 610 690 680 670 660 650 640 VIN = 12V, VOUT = 1.05V, IOUT = 0.7A VIN = 12V, VOUT = 1.05V, IOUT = 0.7A 630 600 -50 -25 0 25 50 75 100 4 125 6 8 4.5 4.5 Current Limit (A) Current Limit (A) 5.0 4.0 RT7281 RT7280 RT7279 RT7274 16 18 4.0 3.5 RT7281 RT7280 RT7279 RT7274 3.0 2.5 2.5 VIN = 12V, VOUT = 1.05V 2.0 -50 -25 0 25 50 75 100 VIN = 12V, VOUT = 1.05V 2.0 125 4 6 8 3.9 1.5 Enable Voltage (V) 1.6 Rising 3.7 3.6 Falling 3.5 12 14 16 18 Enable Voltage vs. Temperature UVLO Threshold vs. Temperature 4.0 3.8 10 Input Voltage (V) Temperature (°C) UVLO Threshold (V) 14 Current Limit vs. Input Voltage Current Limit vs. Temperature 5.0 3.0 12 Input Voltage (V) Temperature (°C) 3.5 10 Rising 1.4 1.3 Falling 1.2 1.1 3.4 1.0 3.3 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT7274/79/80/81 Shutdown Current vs. Temperature Quiescent Current vs. Temperature 10 0.90 0.85 Quiescent Current (mA) Shutdown Current (μA)1 9 8 7 6 5 4 3 2 1 VIN = 12V 0 0.80 0.75 0.70 0.65 0.60 0.55 VIN = 12V 0.50 -50 -25 0 25 50 75 100 125 -50 0 25 50 75 100 Temperature (°C) Temperature (°C) Load Transient Response Load Transient Response RT7279/81 125 RT7279/81 VOUT (20mV/Div) VOUT (20mV/Div) IOUT (1A/Div) IOUT (1A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 10mA to 2A VIN = 12V, VOUT = 1.05V, IOUT = 1A to 2A Time (100μs/Div) Time (100μs/Div) Load Transient Response Load Transient Response RT7274/80 RT7274/80 VOUT (50mV/Div) VOUT (20mV/Div) IOUT (1A/Div) IOUT (1A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 10mA to 2A Time (100μs/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 -25 VIN = 12V, VOUT = 1.05V, IOUT = 1A to 2A Time (100μs/Div) is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 Output Ripple Voltage Output Ripple Voltage VOUT (10mV/Div) VOUT (10mV/Div) VLX (10V/Div) VLX (10V/Div) VIN = 12V, VOUT = 1.05V, IOUT = 1A VIN = 12V, VOUT = 1.05V, IOUT = 2A Time (1μs/Div) Time (1μs/Div) Power On from VIN Power Off from VIN VIN (20V/Div) VLX (20V/Div) VIN (20V/Div) VLX (20V/Div) VOUT (1V/Div) VOUT (1V/Div) IOUT (1A/Div) IOUT (1A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 2A VIN = 12V, VOUT = 1.05V, IOUT = 2A Time (2.5ms/Div) Time (5ms/Div) Power On from EN Power Off from EN VEN (10V/Div) VLX (20V/Div) VEN (10V/Div) VLX (20V/Div) VOUT (1V/Div) VOUT (1V/Div) IOUT (1A/Div) IOUT (1A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 2A Time (1ms/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 VIN = 12V, VOUT = 1.05V, IOUT = 2A Time (25μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT7274/79/80/81 Power Good from EN On Power Good from EN Off RT7279/80 RT7279/80 VEN (5V/Div) VEN (5V/Div) VOUT (1V/Div) VOUT (1V/Div) VPGOOD (5V/Div) VPGOOD (5V/Div) VIN = 12V, VOUT = 1.05V, IOUT = 2A VIN = 12V, VOUT = 1.05V, IOUT = 2A Time (1ms/Div) Time (10μs/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 Application Information The RT7274/79/80/81 is a synchronous high voltage Buck converter that can support the input voltage range from 4.5V to 18V and the output current up to 2A. It adopts ACOTTM mode control to provide a very fast transient response with few external compensation components. the EN pin can also be externally pulled high by adding a REN resistor and CEN capacitor from the VIN pin (see Figure 1). EN VIN Figure 1. External Timing Control An external MOSFET can be added to implement digital control on the EN pin when no system voltage above 2V is available, as shown in Figure 2. In this case, a 100kΩ pull-up resistor, REN, is connected between the VIN and the EN pins. MOSFET Q1 will be under logic control to pull down the EN pin. VIN The RT7274/79/80/81 has a unique circuit which sets the on-time by monitoring the input voltage and SW signal. The circuit ensures the switching frequency operating at 700kHz over input voltage range and loading range. EN The RT7274/79/80/81 contains an external soft-start clamp that gradually raises the output voltage. The soft-start timing can be programmed by the external capacitor between the SS and GND pins. The chip provides a 2μA charge current for the external capacitor. If a 3.9nF capacitor is used, the soft-start will be 2.6ms (typ.). The available capacitance range is from 2.7nF to 220nF. t SS (ms) = C5 (nF) × 1.365 ISS (μ A) Chip Enable Operation The EN pin is the chip enable input. Pulling the EN pin low (<0.4V) will shut down the device. During shutdown mode, the RT7274/79/80/81 quiescent current drops to lower than 10μA. Driving the EN pin high (>1.6V, <18V) will turn on the device again. For external timing control, Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 GND Advanced Constant On-Time Control Soft-Start EN CEN PWM Operation It is suitable for low external component count configuration with appropriate amount of Equivalent Series Resistance (ESR) capacitors at the output. The output ripple valley voltage is monitored at a feedback point voltage. The synchronous high-side MOSFET is turned on at the beginning of each cycle. After the internal on-time expires, the MOSFET is turned off. The pulse width of this on-time is determined by the converter's input and output voltages to keep the frequency fairly constant over the entire input voltage range. REN REN 100k EN Q1 RT7274/79/80/81 GND Figure 2. Digital Enable Control Circuit To prevent enabling circuit when VIN is smaller than the VOUT target value, a resistive voltage divider can be placed between the input voltage and ground and connected to the EN pin to adjust IC lockout threshold, as shown in Figure 3. For example, if an 8V output voltage is regulated from a 12V input voltage, the resistor REN2 can be selected to set input lockout threshold larger than 8V. VIN REN1 REN2 EN RT7274/79/80/81 GND Figure 3. Resistor Divider for Lockout Threshold Setting is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT7274/79/80/81 Output Voltage Setting The resistive divider allows the FB pin to sense the output voltage as shown in Figure 4. VOUT R1 FB RT7274/79/80/81 R2 GND Figure 4. Output Voltage Setting highest efficiency operation. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value of ΔIL = 0.2(IMAX) will be a reasonable starting point. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : ⎡ VOUT ⎤ ⎡ VOUT ⎤ L =⎢ ⎥ × ⎢1 − VIN(MAX) ⎥ f I × Δ L(MAX) ⎣ ⎦ ⎣ ⎦ Input and Output Capacitors Selection The output voltage is set by an external resistive divider according to the following equation. It is recommended to use 1% tolerance or better divider resistors. R1 VOUT = 0.765 × (1+ ) R2 The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the high-side MOSFET. A low ESR input capacitor with larger ripple current rating should be used for the maximum RMS current. The RMS current is given by : Under Voltage Lockout Protection V IRMS = IOUT(MAX) OUT VIN The RT7274/79/80/81 has Under Voltage Lockout Protection (UVLO) that monitors the voltage of PVCC pin. When the VPVCC voltage is lower than UVLO threshold voltage, the RT7274/79/80/81 will be turned off in this state. This is non-latch protection. This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT / 2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Over Temperature Protection The RT7274/79/80/81 equips an Over Temperature Protection (OTP) circuitry to prevent overheating due to excessive power dissipation. The OTP will shut down switching operation when junction temperature exceeds 150°C. Once the junction temperature cools down by approximately 25°C the main converter will resume operation. To keep operating at maximum, the junction temperature should be prevented from rising above 150°C. Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and an output voltage. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. V V ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥ f × L VIN ⎦ ⎣ ⎦ ⎣ Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can achieve Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 VIN −1 VOUT Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For the input capacitor, two 10μF and 0.1μF low ESR ceramic capacitors are recommended. The selection of COUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for COUT selection to ensure that the control loop is stable. The output ripple, ΔVOUT , is determined by : 1 ⎤ ΔVOUT ≤ ΔIL ⎡⎢ESR + 8fCOUT ⎦⎥ ⎣ The output ripple will be highest at the maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may need to meet the ESR and RMS current handling requirements. Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 be taken when these capacitors are used at input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. A sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. External Bootstrap Diode Connect a 0.1μF low ESR ceramic capacitor between the BOOT and SW pins. This capacitor provides the gate driver voltage for the high-side MOSFET. It is recommended to add an external bootstrap diode between an external 5V and the BOOT pin for efficiency improvement when input voltage is lower than 5.5V or duty ratio is higher than 65%. The bootstrap diode can be a low cost one such as 1N4148 or BAT54. The external 5V can be a 5V fixed input from system or a 5V output of the RT7274/79/80/81. Note that the external boot voltage must be lower than 5.5V For the RT7279GCP/RT7280GCP, it provides Latch-Off Mode Under Voltage Protection (UVP). When the FB pin voltage drops below 70% of the feedback threshold voltage, UVP will be triggered and the RT7279GCP/RT7280GCP will shutdown in Latch-Off Mode. In shutdown condition, the RT7279GCP/RT7280GCP can be reset by the EN pin or power input, VIN. Latch-Mode VLX (10V/Div) VOUT (1V/Div) Time (1ms/Div) BOOT 0.1µF SW Figure 5. External Bootstrap Diode PVCC Capacitor Selection Decouple with a 1μF ceramic capacitor. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. Over Current Protection When the output shorts to ground, the inductor current decays very slowly during a single switching cycle. An over current detector is used to monitor inductor current to prevent current runaway. The over current detector monitors the voltage between SW and GND during the low-side MOS turn-on state. This is cycle-by-cycle protection. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 Latch-Off Mode (RT7279/80, TSSOP-14 Only) ILX (2A/Div) 5V RT7274/79/80/81 Under Voltage Protection Hiccup Mode (RT7279/80, WDFN-10L 3x3 Only) For the RT7279GQW/RT7280GQW, it provides Hiccup Mode Under Voltage Protection (UVP). When the FB pin voltage drops below 70% of the feedback threshold voltage, UVP will be triggered and the RT7279GQW/RT7280GQW will shutdown in Hiccup Mode. Hiccup mode allows the circuit to operate safely with low input current and power dissipation, and then resume normal operation as soon as overload or short circuit is removed. is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT7274/79/80/81 Thermal Considerations PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For TSSOP-14 (Exposed Pad) package, the thermal resistance, θJA, is 40°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WDFN-10L 3x3 package, the thermal resistance, θJA, is 60°C/W on a standard JEDEC 51-7 four-layer thermal test board. For SOP-8 (Exposed Pad) package, the thermal resistance, θJA, is 49°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formulas : Maximum Power Dissipation (W)1 For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : 3.0 P D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W for SOP-8 (Exposed Pad) package The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curves in Figure 6 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 2.4 1.8 SOP-8 (Exposed Pad) WDFN-10L 3x3 1.2 0.6 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 6. Derating Curve of Maximum Power Dissipation Layout Consideration Follow the PCB layout guidelines for optimal performance of the RT7274/79/80/81 ` Keep the traces of the main current paths as short and wide as possible. ` Put the input capacitor as close as possible to the device pins (VIN and GND). ` SW node is with high frequency voltage swing and should be kept at small area. Keep sensitive components away from the SW node to prevent stray capacitive noise pickup. ` Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT7274/79/80/81 FB pin. ` The GND and Exposed Pad should be connected to a strong ground plane for heat sinking and noise protection. P D(MAX) = (125°C − 25°C) / (40°C/W) = 2.50W for TSSOP-14 (Exposed Pad) package P D(MAX) = (125°C − 25°C) / (60°C/W) = 1.67W for WDFN-10L 3x3 package Four-Layer PCB TSSOP-14 (Exposed Pad) is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 Place the feedback components as close to the FB as possible for better regulation. VOUT PGND R1 VOUT 2 FB 3 PVCC R2 CVCC 4 PGND SS 5 GND 6 PGOOD 15 7 EN Place the input and output capacitors as close to the IC as possible. CIN VINR VIN BOOT SW SW PGND PGND 14 13 12 11 10 9 8 CBOOT L VOUT COUT SW should be connected to inductor by Wide and short trace. Keep sensitive components away from this trace. (a). For TSSOP-14 (Exposed Pad) Package Place the feedback components as close to the FB as possible for better regulation. Place the input and output capacitors as close to the IC as possible. PGND R2 CVCC EN FB PVCC SS PGOOD 1 2 3 PGND VOUT R1 4 5 11 10 9 8 7 6 CIN VIN VIN CBOOT BOOT SW SW L COUT SW should be connected to inductor by Wide and short trace. Keep sensitive components away from this trace. VOUT PGND (b). For WDFN-10L 3x3 Package The resistor divider must be connected as close to the device as possible. VOUT R1 R2 GND C4 C5 C1 C2 EN 8 FB 2 PVCC 3 SS 4 GND 9 7 6 5 Input capacitor must be placed as close to the IC as possible. SW should be connected to inductor by Wide and short trace. Keep sensitive VIN components away from this trace. BOOT C6 SW L1 GND C7 VOUT (c). For SOP-8 (Exposed) Package Figure 7. PCB Layout Guide Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT7274/79/80/81 Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 1.000 1.200 0.039 0.047 A1 0.000 0.150 0.000 0.006 A2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 D 4.900 5.100 0.193 0.201 e 0.650 0.026 E 6.300 6.500 0.248 0.256 E1 4.300 4.500 0.169 0.177 L 0.450 0.750 0.018 0.030 U 1.900 2.900 0.075 0.114 V 1.600 2.600 0.063 0.102 14-Lead TSSOP (Exposed Pad) Plastic Package Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 is a registered trademark of Richtek Technology Corporation. DS7274/79/80/81-02 April 2013 RT7274/79/80/81 D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7274/79/80/81-02 April 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT7274/79/80/81 H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 24 DS7274/79/80/81-02 April 2013