Lattice M4 / M4A3 / M4A5 Product Family Qualification Summary Lattice Document # 25 – 106901 June 2011 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com Dear Customer, Welcome to the Lattice Semiconductor Corp. M4 / M4A3 / M4A5 Product Family Qualification Report. This report reflects our continued commitment to product quality and reliability. The information in this report is drawn from an extensive qualification program of the wafer technology and packaging assembly processes used to manufacture our products. The program adheres to JEDEC and Automotive Industry standards for qualification of the technology and device packaging. This program ensures you only receive product that meets the most demanding requirements for Quality and Reliability. The information contained in this document is extensive, and represents the entire qualification effort for this device family. Our goal is to provide this information to support your decision making process, and to facilitate the selection and use of our products. As always, your feedback is valuable to Lattice. Our goal is to continuously improve our systems, including the generation of this report and the data included. Please feel free to forward your comments and suggestions to your local Lattice representative. We will use that feedback carefully and wisely in our effort to maximize customer satisfaction. Sincerely, Michael J. Gariepy VP – Reliability and Quality Assurance Lattice Semiconductor Corp. Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 2 INDEX 1.0 INTRODUCTION .................................................................................................................................................. 4 Table 1.1 Lattice ispMACH™ 4A Product Family Attributes ..................................................................................................... 4 2.0 LATTICE PRODUCT QUALIFICATION PROGRAM .......................................................................................... 5 Figure 2.1: ispM4A Product Qualification Process Flow ........................................................................................................... 6 Table 2.2: Standard Qualification Testing .................................................................................................................................. 8 3.0 SILICON QUALIFICATION DATA FOR ISPMACH™ 4A PRODUCT FAMILY ............................................... 10 3.1 PRODUCT FAMILY LIFE DATA.................................................................................................................................................... 10 Table 3.1.1: EE8 Product Family HTOL Results ...................................................................................................................... 10 3.2 HIGH TEMPERATURE DATA RETENTION (HTRX) ...................................................................................................................... 11 Table 3.2.1: ispMACH 4A High Temperature Data Retention Results ..................................................................................... 11 3.3 EXTENDED ENDURANCE (EE) .................................................................................................................................................... 12 Table 3.3.1: ispMACH 4A Extended Endurance Results........................................................................................................... 12 3.4 HIGH TEMPERATURE DATA RETENTION (HTDR) ...................................................................................................................... 13 Table 3.4.1: ispMACH 4A High Temperature Data Retention Results ..................................................................................... 13 3.5 PRODUCT FAMILY – ESD AND LATCH UP DATA ....................................................................................................................... 14 Table 3.5.1 ispMACH 4A Seiko Sakata ESD-HBM Data .......................................................................................................... 14 Table 3.5.2 ispMACH 4A Seiko Sakata ESD-CDM Data .......................................................................................................... 14 Table 3.5.3 ispMACH 4A I/O Latch-Up >100mA @ HOT (105°C) Data ................................................................................. 15 Table 3.5.4 ispMACH 4A Vcc Latch-Up >1.5X @ HOT (105°C) Data .................................................................................... 15 4.0 PACKAGE QUALIFICATION DATA FOR M4A3/M4A5-128/64 PRODUCTS ................................................. 16 Table 4.0 Product-Package Qualification-By-Extension Matrix............................................................................................... 16 4.1 SURFACE MOUNT PRECONDITIONING TESTING .......................................................................................................................... 17 Table 4.1.1 Surface Mount Precondition Data .......................................................................................................................... 17 4.2 HIGH TEMPERATURE STORAGE LIFE (HTSL) DATA .................................................................................................................. 18 Table 4.2.1: High Temperature Storage Life Results ................................................................................................................ 18 4.3 TEMPERATURE CYCLING DATA ................................................................................................................................................. 18 Table 4.3.1: Temperature Cycling Data .................................................................................................................................... 18 4.4 UNBIASED HAST DATA ............................................................................................................................................................ 19 Table 4.3.1: Unbiased HAST Data ............................................................................................................................................ 19 4.5 THB: BIASED HAST DATA ....................................................................................................................................................... 19 Table 4.4.1: Biased HAST Data ................................................................................................................................................ 19 5.0 SEIKO-SEKATA EE8 FAB PROCESS – WAFER LEVEL RELIABILITY ........................................................ 20 Table 5.1 – Wafer Level Reliability Results for EE8 (0.35um) Process Technology ................................................................. 20 6.0 PACKAGE ASSEMBLY INTEGRITY TESTS ................................................................................................... 21 6.1 WIRE BOND PULL ...................................................................................................................................................................... 21 7.0 ADDITIONAL FAMILY DATA ............................................................................................................................ 22 Table 7.1: ispMACH 4A Package Assembly Data- TQFP ........................................................................................................ 22 Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 3 1.0 INTRODUCTION The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation. Table 1.1 Lattice ispMACH™ 4A Product Family Attributes INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 4 2.0 LATTICE PRODUCT QUALIFICATION PROGRAM Lattice Semiconductor Corp. maintains a comprehensive reliability qualification program to assure that each product achieves its reliability goals. After initial qualification, the continued high reliability of Lattice products is assured through ongoing monitor programs as described in Reliability Monitor Program Procedure (Doc. #70101667). All product qualification plans are generated in conformance with Lattice Semiconductor’s Qualification Procedure (Doc. #70-100164) with failure analysis performed in conformance with Lattice Semiconductor’s Failure Analysis Procedure (Doc. #70-100166). Both documents are referenced in Lattice Semiconductor’s Quality Assurance Manual, which can be obtained upon request from a Lattice Semiconductor sales office or downloaded from the lattice website at www.latticesemi.com. Figure 2.1 shows the Product Qualification Process Flow. If failures occur during qualification, an 8-Discipline (8D) process is used to find root cause and eliminate the failure mode from the design, materials, or process. The effectiveness of any fix or change is validated through additional testing as required. Final testing results are reported in the qualification reports. Failure rates in this reliability report are expressed in FITS. Due to the very low failure rate of integrated circuits, 9 9 it is convenient to refer to failures in a population during a period of 10 device hours; one failure in 10 device hours is defined as one FIT. Product families are qualified based upon the requirements outlined in Table 2.2. In general, Lattice Semiconductor follows the current Joint Electron Device Engineering Council (JEDEC) and Military Standard testing methods. Lattice automotive products are qualified and characterized to the Automotive Electronics Council (AEC) testing requirements and methods. Product family qualification will include products with a wide range of circuit densities, package types, and package lead counts. Major changes to products, processes, or vendors require additional qualification before implementation. The ispMACH™ 4A product family is built on EE8 which is a 3.3V shallow trench isolated, 0.35um drawn / 0.25um Leff CMOS process with Electrically Erasable cell (E2 cell). This process uses three planarized metal interconnect layers and single layer polysilicon at either United Microelectronics Company (UMC), or Epson Sakata, and assembled at Advance Semiconductor Engineering Malaysia (ASEM), Amkor Korea and UNISEM Group Singapore, in TQFP and QFNS packages. To verify product reliability, Lattice Semiconductor maintains an active Reliability Monitor program on the ispMACH™ 4A products. Lattice Semiconductor publishes the Reliability Monitor Data quarterly. Lattice Semiconductor maintains a regular reliability monitor program. The current Lattice Reliability Monitor Report can be found at www.latticesemi.com/lit/docs/qa/product_reliability_monitor.pdf . INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 5 Figure 2.1: ispM4A Product Qualification Process Flow Qualification Plan Request Determine Generic Qualification Type New Foundry Technology Process Change Foundry Transfer New Product Family Add Product to Family Design Change New Package Technology Package Materials Change Assembly Transfer Expand Die or Package Size Automotive or Commercial? Commercial / Industrial JESD47 Standard Qualification Requirements Automotive AEC-Q100 Standard Qualification Requirements Check for Customer Specific Requirements Generate FMEA: Risk Management & Lessons Learned Generate Qualification Plan INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 6 Approved Qualification Plan Qualifiable Material Review Commercial Automotive Automotive or Commercial? Commercial Room Temperature Pre-stress testing & data logging Automotive 3-Temperature Pre-stress testing & data logging JEDEC standard based reliability stressing Room Temperature Post-stress testing & data logging 3-Temperature Post-stress testing & data logging Qualification Failures? Failure Analysis Qualification Report INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 7 Table 2.2: Standard Qualification Testing TEST STANDARD High Temperature Lattice Procedure Operating Life # 87-101943, HTOL MIL-STD-883, Method 1005.8, JESD22-A108D ispMACH 4A High Temp Data Retention HTRX High Temp Storage Life HTSL Lattice Procedure # 87-101925, JESD22-A103D JESD22-A117B TEST CONDITIONS SAMPLE SIZE PERFORMED ON (Typ) 125° C, 77/lot Design, Foundry Maximum operating Vcc, 2-3 lots Process, Package 168, 500, 1000, 2000 Qualification hrs. Preconditioned with 100 read/write cycles 150° C, Maximum operating Vcc, 168, 500, 1000, 2000 hrs. ispMACH 4A Preconditioned with 100 read/write cycles Lattice Procedure # 87-101925, JESD22-A103D 150° C, at 168, 500, 1000, 2000 hours. 77/lot 2-3 lots Design, Foundry Process, Package Qualification 2 E Cell Products Flash based Products 77/lot 2-3 lots Design, Foundry Process, Package Qualification ispMACH 4A Endurance Program/Erase Cycling Non-volatile Products ESD HBM ESD CDM Latch Up Resistance LU Surface Mount Pre-conditioning SMPC Temperature Cycling TC Unbiased HAST UHAST Lattice Procedure, # 70-104633 JESD22-A117B Program/Erase devices to 1,000 cycles Program/Erase devices to 10X cycles of data sheet specification Lattice Procedure Human Body Model # 70-100844, (HBM) sweep to 2000 MIL-STD-883, Method volts – (130nm and 3015.7 older) JESD22-A114F Lattice Procedure Charged Device model # 70-100844, (CDM) sweep to 1000 JESD22-C101E volts (130nm and older) Lattice Procedure ±100 ma on I/O's, # 70-101570, Vcc +50% on Power JESD78C Supplies. (Max operating temp.) Lattice Procedure 10 Temp cycles, # 70-103467, 24 hr 125° C Bake IPC/JEDEC 192hr. 30/60 Soak J-STD-020D.1 3 SMT simulation cycles JESD-A113F CPLD/FPGA - MSL 3 Lattice Procedure #70-101568, MIL-STD- 883, Method 1010, Condition B JESD22-A104D Lattice Procedure # 70-104285 JESD22-A118 (1000 cycles) Repeatedly cycled between -55° C and +125° C in an air environment 2 atm. Pressure, 96 hrs, 130 C, 85% Relative Humidity 10/lot Design, Foundry 2-3 lots typical Process, Package Qualification. 3 parts/lot Design, Foundry 1-3 lots typical Process 3 parts/lot Design, Foundry 1-3 lots typical Process 6 parts/lot Design, Foundry 1-3 lots typical Process All units going Plastic Packages only into Temp Cycling, UHAST, BHAST, 85/85 45 parts/lot 2-3 lots Design, Foundry Process, Package Qualification 45 parts/lot 2-3 lots Foundry Process, Package Qualification Plastic Packages only Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 8 TEST STANDARD TEST CONDITIONS Moisture Resistance Temperature Humidity Bias 85/85 THBS Lattice Procedure # 70-101571, JESD22-A101C Biased to maximum operating Vcc, 85° C, 85% Relative Humidity, 1000 hours SAMPLE SIZE PERFORMED ON (Typ) 45 devices/lot Design, Foundry 2-3 lots Process, Package Qualification Plastic Packages only or Biased HAST BHAST JESD22-A110C Wire Bond Strength Lattice Procedure # 70-100220 or Biased to maximum operating Vcc, 2atm. Pressure, 96 hrs, 130 C, 85% Relative Humidity Per package type 15 devices per Design, Foundry pkg. per year Process, Package Qualification INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 9 3.0 SILICON QUALIFICATION DATA FOR ispMACH™ 4A Product Family The ispMACH™ 4A product family is built on EE8 which is a 3.3V shallow trench isolated, 0.35um drawn / 0.25um Leff CMOS process with Electrically Erasable (E2) cells. This process uses three planarized metal interconnect layers and single layer polysilicon fabricated at either United Microelectronics Company (UMC), or Epson Sakata, and assembled at Advance Semiconductor Engineering Malaysia (ASEM), Amkor Korea and UNISEM Group Singapore, in TQFP packages. To verify product reliability, Lattice Semiconductor maintains an active Reliability Monitor program on the ispMACH™ 4A products. Lattice Semiconductor publishes the Reliability Monitor Data quarterly. Product Family: MACH4, ispMACH4A Packages offered: 100 TQFP, 84 PLCC Process Technology Node: 0.35um drawn / 0.25um Leff CMOS 3.1 Product Family Life Data High Temperature Operating Life (HTOL) Test The High Temperature Operating Life test is used to thermally accelerate those wear out and failure mechanisms that would occur as a result of operating the device continuously in a system application. Consistent with JEDEC JESD22-A108 “Temperature, Bias, and Operating Life”, a pattern specifically designed to exercise the maximum amount of circuitry is programmed into the device and this pattern is continuously exercised at specified voltages as described in test conditions for each device type. M4A3/M4A5 Life Test (HTOL) Conditions: Stress Duration: 168, 500, 1000 hours. Temperature: 125°C Stress Voltage ispMACH 4A: VCC= 3.6V or 5.5V Preconditioned with 100 read/write cycles Method: Lattice Document # 87-101943 and JESD22-A108 Table 3.1.1: EE8 Product Family HTOL Results Product Name Foundry Lot # Qty 168 Hrs Result 500 Hrs Result 1000 Hrs Result 2000 Hrs Result Cumulative Hours ispM4A5-128/64 Seiko Sakata Lot #1 78* 0 0 0 0 156000 ispM4A5-128/64 Seiko Sakata Lot #2 78* 0 0 0 0 154000 ispM4A5-128/64 Seiko Sakata Lot #3 77 0 0 0 0 154000 *Lot #1 with CD process splits *Lot #2 with Vt process splits EE8 Cumulative Device Hours = 464,000 EE8 Cumulative Sample Size = 0 / 233 EE8 FIT Rate = 55 FIT INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 10 3.2 High Temperature Data Retention (HTRX) High Temperature Data Retention (HTRX) The High Temperature Data Retention test measures the Electrically Erasable cell (E2 cell) reliability while the High Temperature Operating Life test is structured to measure functional operating circuitry failure mechanisms. The High Temperature Data Retention test is specifically designed to accelerate charge gain on to or charge loss off of the floating gates in the device's array. Since the charge on these gates determines the actual pattern and function of the device, this test is a measure of the reliability of the device in retaining programmed information. In High Temperature Data Retention, the E2 cell reliability is determined by monitoring the cell margin after biased static operation at 150°C. All cells in all arrays are life tested in both programmed and erased states. Data Retention (HTRX) Conditions: Stress Duration: 168, 500, 1000 hours. Temperature: 150°C Preconditioned with 100 read/write cycles Method: Lattice Document # 87-101925 and JESD22-A103 / JESD22-A117 Table 3.2.1: ispMACH 4A High Temperature Data Retention Results Product Name Foundry Lot # Qty 168 Hrs Result 500 Hrs Result 1000 Hrs Result 2000 Hrs Result Cumulative Hours ispM4A5-128/64 Seiko Sakata Lot #1 77 0 0 0 0 154000 ispM4A5-128/64 Seiko Sakata Lot #2 77 0 0 0 0 154000 ispM4A5-128/64 Seiko Sakata Lot #3 78* 0 0 0 0 154000 *Lot #3 with tunnel oxide process splits Cumulative HTRX Failure Rate = 0 / 232 Cumulative HTRX Device Hours = 462,000 INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 11 3.3 Extended Endurance (EE) Extended Endurance (EE) Extended Endurance testing measures the durability of the device through programming and erase cycles. Extended Endurance testing consists of repeatedly programming and erasing all E2 cells in the array at 25°C to simulate programming cycles the user would perform. This test evaluates the integrity of the thin tunnel oxide through which current passes to program the floating gate in each cell of the array. Extended Endurance (EE) Conditions: Stress Duration: 1000 cycles. Temperature: 25°C Method: Lattice Document # 70-104633 and JESD22-A117 Table 3.3.1: ispMACH 4A Extended Endurance Results Product Name Foundry Lot # Qty 0 Cycles Result 1000 Cycles Result ispM4A5-128/64 Seiko Sakata Lot #1 10 0 0 ispM4A5-128/64 Seiko Sakata Lot #2 10 0 0 ispM4A5-128/64 Seiko Sakata Lot #3 10 0 0 ispM4A5-128/64 Seiko Sakata Lot #4 10 0 0 ispM4A5-128/64 Seiko Sakata Lot #5 10 0 0 *Lot #4 is a thin tunnel oxide process split *Lot #5 is a thick tunnel oxide process split Cumulative EE Failure Rate = 0 / 50 INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 12 3.4 High Temperature Data Retention (HTDR) High Temperature Data Retention (HTDR) High Temperature Data Retention measures the ability of the E2 cell to meet the company’s retention goal of >10 years at Tjrel, including the effect of Write-Erase cycling to the product specification. HTDR is a wafer-level test. High Temperature Data Retention (HTDR) Conditions: Stress Duration: 1000 hours. Temperature: 250°C Preconditioned with 100 read/write cycles. Method: Lattice Document # 87-106567 and JESD22-A117 Table 3.4.1: ispMACH 4A High Temperature Data Retention Results Product Name Foundry Wafer # Split Die Qty 0 Hour Result 1000 Hour Result ispM4A5-128/64 Seiko Sakata Wafer #1 Thick Oxide 15 0 0 ispM4A5-128/64 Seiko Sakata Wafer #2 Thin Oxide 20 0 0 ispM4A5-128/64 Seiko Sakata Wafer #3 Nominal 18 0 0 o All splits pass >>10 years lifetime at Tjrel = 130 C Cumulative HTDR Failure Rate = 0 / 53 INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 13 3.5 Product Family – ESD and Latch UP Data Electrostatic Discharge-Human Body Model: ispMACH 4A product family fabricated at Seiko Sakata was tested per the JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) procedure and Lattice Procedure # 70-100844. 0 All units were tested at 25 C prior to reliability stress and after reliability stress. No failures were observed within the passing classification. Table 3.5.1 ispMACH 4A Seiko Sakata ESD-HBM Data Product 100-TQFP 100-csBGA 100-PQFP ispM4A3-64/64 >2000V Class 2 ispM4A5-128/64 >2000V Class 2 >2000V Class 2 >2000V Class 2 ispM4A3-128/64 >2000V Class 2 >2000V Class 2 >2000V Class 2 84-PLCC >2000V Class 2 M4-128N HBM classification for Commercial/Industrial products, per JESD22-A114 Electrostatic Discharge-Charged Device Model: ispMACH 4A product family fabricated at Seiko Sakata was tested per the JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components procedure and Lattice Procedure # 70-100844. 0 All units were tested at 25 C prior to reliability stress and after reliability stress. No failures were observed within the passing Classification. Table 3.5.2 ispMACH 4A Seiko Sakata ESD-CDM Data Product 100-TQFP 100-csBGA 100-PQFP ispM4A3-64/64 >1000V Class IV ispM4A5128/64 >1000V Class IV >1000V Class IV >1000V Class IV ispM4A3128/64 >1000V Class IV >1000V Class IV >1000V Class IV 84-PLCC >1000V Class IV M4-128N CDM classification for Commercial/Industrial products, per JESD22-C101 INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 14 Latch-Up: The ispMACH 4A product family was tested per the JEDEC EIA/JESD78 IC Latch-up Test procedure and Lattice Procedure # 70-101570. 0 All units were tested at 25 C prior to reliability stress and after reliability stress. No failures were observed within the passing Classification. Table 3.5.3 ispMACH 4A I/O Latch-Up >100mA @ HOT (105°C) Data Product 100-TQFP 100-csBGA 100-PQFP ispM4A3-64/64 >+/- 100mA Class II, Level A ispM4A5-128/64 >+/- 100mA Class II, Level A >+/- 100mA Class II, Level A >+/- 100mA Class II, Level A ispM4A3-128/64 >+/- 100mA Class II, Level A >+/- 100mA Class II, Level A >+/- 100mA Class II, Level A 84-PLCC >+/- 100mA Class II, Level A M4-128N Table 3.5.4 ispMACH 4A Vcc Latch-Up >1.5X @ HOT (105°C) Data Product 100-TQFP 100-csBGA 100-PQFP ispM4A3-64/64 >1.5x Vccmax ispM4A5-128/64 >1.5x Vccmax >1.5x Vccmax >1.5x Vccmax ispM4A3-128/64 >1.5x Vccmax >1.5x Vccmax >1.5x Vccmax M4-128N 84-PLCC >1.5x Vccmax INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 15 4.0 PACKAGE QUALIFICATION DATA FOR M4A3/M4A5-128/64 Products The primary package for the ispM4A3-128/64 and ispM4A5-128/64 is the 100TQFP assembled at ASE Malaysia. Package qualification tests include Surface Mount Preconditioning (SMPC), Temperature Cycling (T/C), Un-biased HAST (UHAST) and Biased HAST (BHAST). Mechanical evaluation tests include Scanning Acoustic Tomography (SAT) and visual package inspection. Table 4.0 Product-Package Qualification-By-Extension Matrix Products M4A3-64 M4A3-128 M4A5-128 M4-128 Stress Test SMPC T/C BHAST UHAST HTSL SMPC T/C BHAST UHAST HTSL SMPC T/C BHAST UHAST HTSL SMPC T/C BHAST UHAST HTSL Advanced Semiconductor Engineering, Malaysia (ASEM) 100-TQFP 100-csBGA 100-PQFP 84-PLCC (1) Package not offered Package not offered Package not offered (1) No package BOM changes No package BOM changes Package not offered No package BOM changes No package BOM changes Package not offered o MSL3 260 C 1000 cycles 96 hours 96 hours 1000 hours Packages not offered No package BOM changes Notes: 1 – Qualified by extension from Lattice ispM4A5-128 testing. Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 16 4.1 Surface Mount Preconditioning Testing The Surface Mount Preconditioning (SMPC) Test is used to model the surface mount assembly conditions during component solder processing. All devices stressed through Temperature Cycling, Un-biased HAST and Biased HAST were preconditioned. This preconditioning is consistent with JEDEC JESD22-A113 “Preconditioning Procedures of Plastic Surface Mount Devices Prior to Reliability Testing”, Moisture Sensitivity Level 3 (MSL3) package moisture sensitivity and dry-pack storage requirements. Consistent with Lattice Semiconductor Corp. document # 25-100164, package reliability testing can be qualified by extension. Once a package outline is qualified within a package grouping as per doc #70-103639, all lower lead count (and smaller body size) packages within that package type and assembly technology are qualified by extension. Additionally, once an assembly technology has been qualified for one package type, that package type shall be qualified by extension to all future fabrication processes as long as those processes continue to use the same critical elements. Those critical elements in this case, are that the process-to-process interlayer dielectric material and thickness differences do not exceed the current production process limits for the qualification vehicle used. For 180nm and older technologies, the critical elements are considered equivalent. Surface Mount Preconditioning (MSL3) (10 Temperature Cycles between -55°C and 125°C, 24 hours bake @ 125°C, 30°C/60% RH, soak 192 hours, Reflow Simulation, 3 passes) performed before all ispMach4A package tests. MSL3 Package: TQFP Table 4.1.1 Surface Mount Precondition Data Assembly Lot Site Number Quantity Reflow # of Fails Temperature Product Name Package ispM4A5-128/64 100 TQFP ASEM Lot #1 314 0 260°C ispM4A5-128/64 100 TQFP ASEM Lot #2 314 0 260°C ispM4A5-128/64 100 TQFP ASEM Lot #3 397 0 260°C Cumulative SMPC Failure Rate = 0 / 1,025 INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 17 4.2 High Temperature Storage Life (HTSL) Data High Temperature Storage Life (HTSL) High Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices. Units were stressed per JESD22-A103, High Temperature Storage Life. Prior to High Temperature Storage Life testing, all devices are subjected to Surface Mount Preconditioning. The High Temperature Storage Life units were stressed at 150°C. High Temperature Storage Life (HTSL) Conditions: Stress Duration: 168, 500, 1000, hours. Temperature: 150°C Method: Lattice Document # 87-101925 and JESD22-A103 / JESD22-A117 Table 4.2.1: High Temperature Storage Life Results 168 Hrs 500 Hrs 1000 Hrs Cumulative Result Result Result Hours Product Name Assembler Package Lot # Qty ispM4A5-128/64 ASEM 100 TQFP Lot #1 77 0 0 0 77000 ispM4A5-128/64 ASEM 100 TQFP Lot #2 77 0 0 0 77000 ispM4A5-128/64 ASEM 100 TQFP Lot #3 77 0 0 0 77000 Cumulative HTSL Failure Rate = 0 / 231 Cumulative HTSL Device Hours = 231,000 4.3 Temperature Cycling Data The Temperature Cycling test is used to accelerate those failures resulting from mechanical stresses induced by differential thermal expansion of adjacent films, layers and metallurgical interfaces in the die and package. Devices are tested at 25°C after exposure to repeated cycling between -55°C and +125°C in an air environment consistent with JEDEC JESD22-A104 “Temperature Cycling”, Condition B temperature cycling requirements. Prior to Temperature Cycling testing, all devices are subjected to Surface Mount Preconditioning. MSL3 Packages: TQFP Stress Duration: 1000 cycles Stress Conditions: Temperature cycling between -55°C to 125°C Method: Lattice Procedure # 70-101568 and JESD22-A104 Table 4.3.1: Temperature Cycling Data Assembly Lot Site Number Quantity 250 Cycles 500 Cycles 1000 Cycles Lot #1 83 0 0 0 ASEM Lot #2 83 0 0 0 ASEM Lot #3 84 0 0 0 Product Name Package ispM4A5-128/64 100 TQFP ASEM ispM4A5-128/64 100 TQFP ispM4A5-128/64 100 TQFP Cumulative Temp Cycle Failure Rate = 0 / 250 INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 18 4.4 Unbiased HAST Data Unbiased Highly Accelerated Stress Test (HAST) testing uses both pressure and temperature to accelerate penetration of moisture into the package and to the die surface. The Unbiased HAST test is designed to detect ionic contaminants present within the package or on the die surface, which can cause chemical corrosion. Consistent JEDEC JESD22-A118, “Accelerated Moisture Resistance - Unbiased HAST,” the Unbiased HAST conditions are 96 hour exposure at 130°C, 85% relative humidity, and 2 atmospheres of pressure. Prior to Unbiased HAST testing, all devices are subjected to Surface Mount Preconditioning. MSL3 Package: TQFP Stress Duration: 96 Hrs Stress Conditions: 130°C, 15psig, 85% RH Method: Lattice Procedure # 70-104285 and JESD22-A118 Table 4.3.1: Unbiased HAST Data Assembly Lot Site Number Quantity # of Fails Stress Duration Lot #1 77 0 96 Hrs ASEM Lot #2 77 0 96 Hrs ASEM Lot #3 77 0 96 Hrs Product Name Package ispM4A5-128/64 100 TQFP ASEM ispM4A5-128/64 100 TQFP ispM4A5-128/64 100 TQFP Cumulative Unbiased HAST failure Rate = 0 / 231 4.5 THB: Biased HAST Data Highly Accelerated Stress Test (HAST) testing uses both pressure and temperature to accelerate penetration of moisture into the package and to the die surface. The Biased HAST test is used to accelerate threshold shifts in the MOS device associated with moisture diffusion into the gate oxide region as well as electrochemical corrosion mechanisms within the device package. Consistent with JEDEC JESD A110-B “Highly-Accelerated Temperature and Humidity Stress Test (HAST)”, the biased HAST conditions are with Vcc bias and alternate pin biasing in an ambient of 130°C, 85% relative humidity, and 2 atmospheres of pressure. Prior to Biased HAST testing, all devices are subjected to Surface Mount Preconditioning. MSL3 Packages: TQFP Stress Conditions: ispMACH 4A5-128/64 Vcc= 5.5 V, 130°C / 85% RH, 15 psig Stress Duration: 96 hours Method: Lattice Procedure # 70-101571 and JESD22-A101 Table 4.4.1: Biased HAST Data Assembly Lot Site Number Quantity # of Fails Stress Duration Lot #1 77 0 96 Hrs ASEM Lot #2 77 0 96 Hrs ASEM Lot #3 77 0 96 Hrs Product Name Package ispM4A5-128/64 100 TQFP ASEM ispM4A5-128/64 100 TQFP ispM4A5-128/64 100 TQFP Cumulative BHAST failure Rate = 0 / 1,124 INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 19 5.0 Seiko-Sekata EE8 Fab Process – Wafer Level Reliability Several key fabrication process related parameters have been identified by the foundry that would affect the Reliability of the End-of-Life Product. These parameters are tested during the Development Phase of the Technology. Passing data (a 10yr lifetime at the reliability junction temperature) must be obtained for three lots minimum for each parameter before release to production. Normal operating conditions are defined in the Electrical Design Rules (EDR). These parameters are: Hot Carrier Immunity (HCI): Effect is a reduction in transistor Idsat. Worst case is low temperature. Time Dependent Dielectric Breakdown (TDDB): Transistor and capacitor oxide shorts or leakage. Negative Bias Temperature Instability (NBTI): Degradation of P channel transistors at negative Vg. Electromigration Lifetime (EML): Symptom is opens within, or shorts between, metal conductors. Stress Migration (SM): Microscopic voids may exist in Tungsten plug-Aluminum CMP-SiO2 IMD structures. Table 5.1 – Wafer Level Reliability Results for EE8 (0.35um) Process Technology HCI TDDB NBTI EML SM Device LVN LVP HVN HVP delta Ids Celsius Vgstress Vds TTF -10% 25 Vd/2 3.6 3 lots>58yr AC -10% 25 Vd -3.6 lots>5.4e4yr DC -10% 25 Vd/2 5.5 2 lots>525yr DC -10% 25 Vd -5.5 2 lots>5.5e8yr DC Device LVN LVP HVN HVP Celsius Vg 0.1% TTF 130 3.6 3 lots>2750 yr 130 -3.6 2 lots>4.1e4yr 130 5.5 3 lots>2.1e3yr 130 -5.5 2 lots>1.8e3yr Device LVP HVP delta Vth Celsius Vg TTF 100mv 130 -3.6 2 lots>13.4 yr 100mv 130 -5.5 2 lots>1840yr Device M1 M2 M3 Celsius delta R Jmax 0.1% TTF 130 +10% 2.00E+05 3 lots>18 yr 130 +10% 2.00E+05 3 lots>30 yr 130 +10% 2.00E+05 3 lots>17 yr Device delta R condition TTF M1 +10% 175C-1000hr 2 lots Pass M2 +10% 175C-1000hr 2 lots Pass M3 +10% 175C-1000hr 2 lots Pass Note: Reliability life times are based on listed temperature and used conditions. Detailed WLR test conditions are available upon request. INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 20 6.0 PACKAGE ASSEMBLY INTEGRITY TESTS 6.1 Wire Bond Pull This procedure is used to measure the wire bond strength at the ball joints and stitch bonds. For product evaluation 12 bonds from a minimum of five devices for each package lot were used for Wire Bond Pull. Requirement for 0.8 mil gold wire is >3 grams pre-stress, and >0.5 grams post-stress. WIRE BOND PULL RESULTS: All bond pull observations post 1000-hours HTSL >4.3 grams. All bond pull observations post 1000-temp cycles >4.9 grams. The average measured wire bond pull results for TQFP were Cpk of > 2. INDEX return Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 21 7.0 ADDITIONAL FAMILY DATA Table 7.1: ispMACH 4A Package Assembly Data- TQFP Package Attributes / Assembly Sites Die Family (Product Line) Fabrication Process Technology Package Assembly Site Package Type Pin Count Die Preparation/Singulation Die Attach Material - TQFP Mold Compound Supplier/ID - TQFP Wire Bond Material Wire Bond Methods Lead frame Material Lead Finish Marking ASEM ispMACH 4A EE8 (0.35um CMOS) Malaysia TQFP 100 wafer saw, full cut Ablebond 3230 Hitachi CEL9220HF Series Gold (Au) Thermosonic Ball Cu Alloy Matte Sn (annealed) Laser or Ink INDEX return Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, Oregon 97124 U.S.A. Telephone: (503) 268-8000, FAX: (503) 268-8556 www.latticesemi.com © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation Doc. #25-106901 Rev. D 22