Lattice Copper (Cu) Bond Wire Qualification Summary Lattice Document # 25 – 106990 March 2015 © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respectiv e holders. The specif ications and inf ormatio n herein are subject to change without notice. www.latticesemi.com Dear Customer, Enclosed is Lattice Semiconductor’s Copper (Cu) Bond Wire Qualification Summary Product Family Qualification Report. This report was created to assist you in the decision making process of selecting and using our products. The information contained in this report represents the entire qualification effort for this device family. The information is drawn from an extensive qualification program of the wafer technology and packaging assembly processes used to manufacture our products. The program adheres to JEDEC and Automotive Industry standards for qualification of the technology and device packaging. This program ensures you only receive product that meets the most demanding requirements for Quality and Reliability. Your feedback is valuable to Lattice. If you have suggestions to improve this report, or the data included, we encourage you to contact your Lattice representative. Sincerely, James M. Orr Vice President, Corporate Quality & Product Development Lattice Semiconductor Corporation Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 2 TABLE OF CONTENTS 1.0 LATTI CE PRODUCT QUALIFICATION P ROGRAM .................................................................................5 Figure 1.0.1 Lattice Standard Product Qualification Process Flow.................................................................6 Figure 1.0.1 Lattice Standard Product Qualification Process Flow (cont.).......................................................7 Table 1.0.2 Qualification tests for components in non-hermetic packages ......................................................8 2.0 PACKAGE FAMILY QUALIFICATION RESULTS ....................................................................................9 Table 2.0.1 Summary of ASEM Reliability Test Conditions and Results .........................................................9 Table 2.0.2 Summary of ASET Reliability Test Conditions and Results ....................................................... 11 Table 2.0.3 Summary of ATP Reliability Test Conditions and Results.......................................................... 12 Table 2.0.4 Summary of J-Devices Reliability Test Conditions and Results .................................................. 14 2.1 FAMILY QUALIFICATIONS ........................................................................................................................ 15 Table 2.1.1 Leaded-QFP Package Qualification-By-Similarity Matrix for ASEM and ASET ............................. 15 Table 2.1.2 Leaded-QFP Package Qualification-By-Similarity Matrix for ATP and J-Devices .......................... 16 Table 2.1.3 Saw-Singulated BGA Pack age Qualification-By-Similarity Matrix for ASEM and ASET ................. 17 Table 2.1.4 Saw-Singulated BGA Pack age Qualification-By-Similarity Matrix for ATP and J-Devices............... 18 Table 2.1.5 Over-Molded BGA Package Qualification-By-Similarity Matrix ................................................... 19 2.2 SURFACE MOUNT PRECONDITIONING TESTING............................................................................................. 20 Table 2.2.1 Surface Mount Precondition Data (ASEM) .............................................................................. 20 Table 2.2.2 Surface Mount Precondition Data (ASET)............................................................................... 22 Table 2.2.3 Surface Mount Precondition Data (ATP)................................................................................. 23 Table 2.2.4 Surface Mount Precondition Data (J-Devices) ......................................................................... 25 2.3 TEMPERATURE CYCLING (TC) ................................................................................................................. 26 Table 2.3.1 Temperature Cycling Data (ASEM)........................................................................................ 26 Table 2.3.2 Temperature Cycling Data (ASET) ........................................................................................ 27 Table 2.3.3 Temperature Cycling Data (ATP)........................................................................................... 28 Table 2.3.4 Temperature Cycling Data (J-Devices)................................................................................... 30 2.4 UNBIASED HAST ................................................................................................................................. 31 Table 2.4.1 Unbiased HAST Data (ASEM) .............................................................................................. 31 Table 2.4.2 Unbiased HAST Data (ASET) ............................................................................................... 32 Table 2.4.3 Unbiased HAST Data (ATP) ................................................................................................. 33 Table 2.4.4 Unbiased HAST Data (J-Devices) ......................................................................................... 34 2.5 THB: BIASED HAST OR 85/85................................................................................................................ 35 Table 2.5.1 THB Data (ASEM)............................................................................................................... 35 Table 2.5.2 THB Data (ASET) ............................................................................................................... 37 Table 2.5.3 THB Data (ATP).................................................................................................................. 38 Table 2.5.4 THB Data (J-Devices).......................................................................................................... 39 2.6 HIGH TEMPERATURE STORAGE LIFE ......................................................................................................... 40 Table 2.6.1 High Temperature Storage Life Data (ASEM).......................................................................... 40 Table 2.6.2 High Temperature Storage Life Data (ASET) .......................................................................... 42 Table 2.6.3 High Temperature Storage Life Data (ATP) ............................................................................ 43 Table 2.6.4 High Temperature Storage Life Data (J-Devices)..................................................................... 44 Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 3 3.0 ADDITIONAL PACKAGE FAMILY DATA .............................................................................................. 45 Table 3.0.1 Copper (Cu) Bond Wire Bills of Material by Package Type and Assembly Site............................. 45 4.0 REVISION HISTORY ............................................................................................................................ 46 Table 4.0.1 Copper (Cu) Bond Wire Qualification Summary revisions ......................................................... 46 Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 4 1.0 LATTICE PRODUCT QUALIFICATION PROGRAM Lattice Semiconductor Corp. maintains a comprehensive reliability qualification program to assure that each product achieves its reliability goals. After initial qualification, the continued high reliability of Lattice products is assured through ongoing monitor programs as described in Lattice Semiconductor’s Reliability Monitor Program Procedure (Doc. #70-101667). All product qualification plans are generated in conformance with Lattice Semiconductor’s Qualification Procedure (Doc. #70-100164) with failure analysis performed in conformance with Lattice Semiconductor’s Failure Analysis Procedure (Doc. #70-100166). Both documents are referenced in Lattice Semiconductor’s Quality Assurance Manual, which can be obtained upon request from a Lattice Semiconductor sales office. Figure 1.1 shows the Product Qualification Process Flow. If failures occur during qualification, an 8D process is used to find root cause and eliminate the failure mode from the design, materials, or process. The effectiveness of any fix or change is validated through additional testing as required. Final testing results are reported in the qualification reports. Package families are qualified based upon the requirements outlined in Table 1.2. In general, Lattice Semiconductor follows the current JEDEC Solid State Technology Association testing methods. Package family qualification will include products with a wide range of circuit densities, package types, and package lead counts. Major changes to products, processes, or vendors require additional qualification before implementation in production. Lattice Semiconductor maintains a regular reliability monitor program. The current Lattice Reliability Monitor Report can be found at Product Reliability Monitor Report. INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 5 Figure 1.0.1 Lattice Standard Product Qualification Process Flow This diagram represents the standard qualification flow used by Lattice to qualify new Product Families. The target end market for the Product Family determines which flow options are used. The Copper wire assembly technology was qualified using the Commercial / Industrial Qualification Option. INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 6 Figure 1.0.1 Lattice Standard Product Qualification Process Flow (cont.) INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 7 Table 1.0.2 Qualification tests for components in non-hermetic packages TEST STANDARD Surface Mount IPC/JEDEC, J-STD-020D.1 Pre-conditioning JESD-A113 SMPC TEST CONDITIONS SAMPLE SIZE (Typical) 5 Temp cycles, All units going 24 hr 125° C Bake into HTSL, TC, 192hr. 30/60 Soak UHAST, and 3 SMT simulation cycles BHAST 150° C, at 168, 500, 1000 77 parts/lot hours. 3 lots PERFORMED ON Package Qualification High Temp Storage Life HTSL Temperature Cycling TC JESD22-A103 JESD22-A104 (700 cycles) Repeatedly cycled between -55° C and +125° C in an air environment 77 parts/lot 3 lots Package Qualification Unbiased Temperature Humidity (Unbiased HAST) Temperature Humidity Bias (Biased HAST or 85-85) JESD22-A118 85% Relative Humidity at 77 parts/lot either 130° C for 96 hours, 3 lots or 110° C for 264 hours Package Qualification JESD22-A110 (Biased HAST) JESD22-A101 (85-85) Package Qualification Bond Strength M2011 Ball Shear JESD22-B117 Bond Shear JESD22-B116 Pins alternately biased to Vcc or Ground, and 85% Relative Humidity at either 130° C for 96 hours, or 110° C for 264 hours, or 85° C for 1000 hours Characterization, Pre Encapsulation Characterization, Pre Encapsulation Characterization 77 devices/lot 3 lots Package Qualification 30 bonds/5 units Package Qualification 30 balls/5 units Package Qualification 30 bonds/5 units Package Qualification INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 8 2.0 PACKAGE FAMILY QUALIFICATION RESULTS The devices are assembled and tested at Advanced Semiconductor Engineering, Malaysia (ASEM), Advanc ed Semiconductor Engineering, Kaohsiung Taiwan (ASET), Amkor Technology Philippines (ATP), and J-Devic es Corporation (J-Devices). Package qualification tests include Surface Mount Pre-Conditioning (SMPC), Temperature Cycling (T/C), Un-biased HAST (UHAST), THB - Biased HAST or 85/85, and High Temperat ure Storage (HTSL). Electrical test is performed pre- and post-stress. Mechanical evaluation tests include Scanning Acoustic Tomography (SAT) and Visual Package Inspection. Details can be found under the specific stress sections. Table 2.0.1 Summary of ASEM Reliability Test Conditions and Results Test Stress Conditions SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x TC TC TC TC TC TC TC TC 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 250°C 250°C 250°C -55C -55C -55C -55C -55C -55C -55C -55C reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow to 125C to 125C to 125C to 125C to 125C to 125C to 125C to 125C LFXP2-5 LFXP6 LCMXO2-1200 LFXP2-17 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO2-1200 LCMXO2-7000 LFXP2-40 LFE2-50 LFE2M100 LFE3-150 Package Type 144-TQFP 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 672-fpBGA 900-fpBGA 1156-fpBGA LFXP2-5 LFXP6 LFXP2-30 LCMXO-2280 LCMXO-2280 LFXP2-40 LFE2M100 LFE3-150 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 324-ftBGA 484-fpBGA 900-fpBGA 1156-fpBGA 4 3 4 3 3 4 3 3 308,000 230,000 308,000 231,000 231,000 308,000 231,000 231,000 cycles cycles cycles cycles cycles cycles cycles cycles 0 0 0 1 0 0 0 0 Test Vehicle Lot Cumulative Device Quantity Units/Hours/Cycles 4 1078 units 3 231 units 3 552 units 4 770 units 4 308 units 6 693 units 3 462 units 3 552 units 3 552 units 4 843 units 3 231 units 3 462 units 3 462 units # of Fails 0 0 0 0 0 0 0 0 0 0 0 0 0 BHAST BHAST BHAST BHAST BHAST 85%RH, 130°C, 96 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours LFXP2-5 LFXP2-17 LCMXO-2280 LFE2-50 LFE3-150 144-TQFP 256-ftBGA 256-ftBGA 672-fpBGA 1156-fpBGA 3 3 6 3 3 22,176 hours 60,984 hours 121,968 hours 60,984 hours 59,400 hours 0 0 4 1 0 85/85 85/85 85/85 85%RH, 85°C, 1,000 hours 85%RH, 85°C, 1,000 hours 85%RH, 85°C, 1,000 hours LCMXO2-1200 LCMXO2-1200 LCMXO2-7000 144-TQFP 132-csBGA 484-fpBGA 3 3 3 75,000 hours 75,000 hours 75,000 hours 0 1 0 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 9 Test Stress Conditions Test Vehicle Package Type UHAST UHAST UHAST UHAST UHAST UHAST 85%RH, 130°C, 96 hours 85%RH, 130°C, 96 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours LFXP2-5 LCMXO2-1200 LFXP2-17 LCMXO2-1200 LCMXO2-7000 LFXP2-40 144-TQFP 144-TQFP 256-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 3 3 3 3 3 3 22,176 22,176 60,720 60,984 60,984 59,928 hours hours hours hours hours hours 0 0 0 0 0 0 LFXP2-5 LCMXO2-1200 LFXP2-17 LCMXO-2280 LCMXO2-1200 LCMXO2-7000 LFXP2-40 LFE2M100 144-TQFP 144-TQFP 256-ftBGA 324-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 900-fpBGA 4 3 4 3 3 3 4 3 308,000 231,000 307,000 231,000 230,000 231,000 308,000 231,000 hours hours hours hours hours hours hours hours 1 0 0 0 0 0 0 0 HTSL HTSL HTSL HTSL HTSL HTSL HTSL HTSL 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 1000 1000 1000 1000 1000 1000 1000 1000 hours hours hours hours hours hours hours hours Lot Cumulative Device Quantity Units/Hours/Cycles # of Fails INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 10 Table 2.0.2 Summary of ASET Reliability Test Conditions and Results Test Stress Conditions SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x TC TC TC TC TC TC TC TC TC TC 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 250°C 250°C 250°C -55C -55C -55C -55C -55C -55C -55C -55C -55C -55C reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow to 125C to 125C to 125C to 125C to 125C to 125C to 125C to 125C to 125C to 125C LFXP2-5 LFXP6 LCMXO2-1200 LFXP2-17 LFXP2-30 LCMXO-2280 LCMXO2-1200 LCMXO2-7000 LFXP2-40 LFE2-50 LFE2M100 LFE3-150 Package Type 144-TQFP 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 324-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 672-fpBGA 900-fpBGA 1156-fpBGA LFXP2-5 LFXP6 LCMXO2-1200 LFXP2-30 LCMXO-2280 LCMXO2-1200 LFXP2-40 LCMXO2-7000 LFE2M100 LFE3-150 144-TQFP 144-TQFP 144-TQFP 256-ftBGA 324-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 900-fpBGA 1156-fpBGA 4 3 3 4 3 3 4 3 3 3 Test Vehicle Lot Cumulative Device Quantity Units/Hours/Cycles 4 847 units 3 231 units 3 693 units 4 539 units 4 308 units 3 462 units 3 812 units 3 693 units 4 847 units 3 255 units 3 462 units 3 231 units 308,000 231,000 231,000 308,000 231,000 231,000 308,000 231,000 231,000 231,000 cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles # of Fails 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BHAST BHAST 85%RH, 130°C, 96 hours 85%RH, 110°C, 264 hours LFXP2-5 LFXP2-17 144-TQFP 256-ftBGA 3 3 23,616 hours 64,944 hours 0 0 85/85 85/85 85/85 85%RH, 85°C, 1,000 hours 85%RH, 85°C, 1,000 hours 85%RH, 85°C, 1,000 hours LCMXO2-1200 LCMXO2-1200 LCMXO2-7000 144-TQFP 132-csBGA 484-fpBGA 3 3 3 105,000 hours 104,000 hours 105,000 hours 0 0 0 UHAST UHAST UHAST UHAST UHAST UHAST 85%RH, 130°C, 96 hours 85%RH, 130°C, 96 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours LFXP2-5 LCMXO2-1200 LFXP2-17 LCMXO2-1200 LCMXO2-7000 LFXP2-40 144-TQFP 144-TQFP 256-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 3 3 3 3 3 3 22,176 22,176 60,984 60,984 60,984 60,984 hours hours hours hours hours hours 0 0 0 0 0 0 LFXP2-5 LCMXO2-1200 LFXP2-17 LCMXO-2280 LCMXO2-1200 LCMXO2-7000 LFXP2-40 LFE2M100 144-TQFP 144-TQFP 256-ftBGA 324-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 900-fpBGA 4 3 4 3 3 3 4 3 308,000 231,000 308,000 231,000 231,000 231,000 308,000 231,000 hours hours hours hours hours hours hours hours 0 0 0 0 0 0 0 0 HTSL HTSL HTSL HTSL HTSL HTSL HTSL HTSL 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 1000 1000 1000 1000 1000 1000 1000 1000 hours hours hours hours hours hours hours hours INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 11 Table 2.0.3 Summary of ATP Reliability Test Conditions and Results Test reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow reflow LFXP2-5 LFXP6 LC4128 LCMXO2-1200 LFXP2-17 LFXP2-30 LCMXO-2280 LC4512 LCMXO-2280 LCMXO2-1200 LCMXO2-7000 LFXP2-40 LFE2-50 LFE2M100 LFE3-150 Package Type 144-TQFP 144-TQFP 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 672-fpBGA 900-fpBGA 1156-fpBGA Stress Conditions SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 3x 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 250°C 250°C 250°C Test Vehicle Lot Cumulative Device Quantity Units/Hours/Cycles 4 1,102 units 3 231 units 3 1,020 units 3 858 units 4 794 units 4 308 units 3 486 units 3 693 units 3 462 units 3 828 units 3 582 units 4 847 units 3 231 units 3 462 units 3 486 units # of Fails 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC TC TC TC TC -55°C -55°C -55°C -55°C -55°C to 125°C to 125°C to 125°C to 125°C to 125°C LFXP2-5 LFXP6 LC4128 LCMXO2-1200 LFXP2-30 144-TQFP 144-TQFP 144-TQFP 144-TQFP 256-ftBGA 4 3 3 3 4 308,000 231,000 231,000 231,000 308,000 cycles cycles cycles cycles cycles 0 0 0 0 0 TC TC TC TC TC TC TC TC TC -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C LCMXO-2280 LC4512 LCMXO-2280 LCMXO2-1200 LFXP2-40 LCMXO2-7000 LFE2-50 LFE2M100 LFE3-150 256-ftBGA 256-ftBGA 324-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 672-fpBGA 900-fpBGA 1156-fpBGA 3 3 3 3 4 3 3 3 3 231,000 231,000 231,000 231,000 308,000 231,000 231,000 231,000 231,000 cycles cycles cycles cycles cycles cycles cycles cycles cycles 0 0 0 0 0 0 0 0 0 BHAST BHAST BHAST BHAST BHAST BHAST 85%RH, 130°C, 96 hours 85%RH, 130°C, 96 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours LFXP2-5 LC4128 LFXP2-17 LCMXO-2280 LC4512 LFE2-50 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 256-ftBGA 672-fpBGA 3 3 3 3 3 3 22,944 31,104 62,832 63,096 60,984 63,360 hours hours hours hours hours hours 1 1 2 1 0 0 85/85 85/85 85/85 85%RH, 85°C, 1,000 hours 85%RH, 85°C, 1,000 hours 85%RH, 85°C, 1,000 hours LCMXO2-1200 LCMXO2-1200 LCMXO2-7000 144-TQFP 132-csBGA 484-fpBGA 3 3 3 88,000 hours 90,000 hours 75,000 hours 2 0 0 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 12 Test UHAST UHAST UHAST UHAST UHAST UHAST UHAST UHAST HTSL HTSL HTSL HTSL HTSL HTSL HTSL HTSL HTSL HTSL Stress Conditions 85%RH, 85%RH, 85%RH, 85%RH, 85%RH, 85%RH, 85%RH, 85%RH, 130°C, 130°C, 130°C, 110°C, 110°C, 110°C, 110°C, 110°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 264 264 264 264 264 264 264 264 hours hours hours hours hours hours hours hours hours hours hours hours hours hours hours hours hours hours Test Vehicle Package Type Lot Cumulative Device Quantity Units/Hours/Cycles LFXP2-5 LC4128 LCMXO2-1200 LFXP2-17 LC4512 LCMXO2-1200 LCMXO2-7000 LFXP2-40 144-TQFP 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 3 3 3 3 3 3 3 3 60,984 60,984 22,176 60,984 60,984 60,984 60,984 60,984 hours hours hours hours hours hours hours hours 0 0 0 0 0 0 0 0 LFXP2-5 LC4128 LCMXO2-1200 LFXP2-17 LC4512 LCMXO-2280 LCMXO2-1200 LCMXO2-7000 LFXP2-40 LFE2M100 144-TQFP 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 324-ftBGA 132-csBGA 484-fpBGA 484-fpBGA 900-fpBGA 4 3 3 4 3 3 3 3 4 3 308,000 231,000 231,000 308,000 231,000 231,000 231,000 231,000 308,000 231,000 hours hours hours hours hours hours hours hours hours hours 0 0 0 0 0 0 0 0 0 0 # of Fails INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 13 Table 2.0.4 Summary of J-Devices Reliability Test Conditions and Results Test SMPC SMPC SMPC SMPC SMPC SMPC SMPC SMPC TC TC TC TC TC TC TC TC reflow reflow reflow reflow reflow reflow reflow reflow LFXP2-5 LFXP6 LCMXO2-1200 LFXP2-17 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO2-1200 Package Type 144-TQFP 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 132-csBGA to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C LFXP2-5 LFXP6 LCMXO2-1200 LFXP2-30 LCMXO-2280 LC4512 LCMXO-2280 LCMXO2-1200 144-TQFP 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 132-csBGA 4 3 3 4 3 3 3 3 433,000 276,000 327,000 456,000 378,000 270,000 327,000 378,000 cycles cycles cycles cycles cycles cycles cycles cycles 0 0 0 0 0 0 0 0 Stress Conditions 3x 3x 3x 3x 3x 3x 3x 3x 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C Test Vehicle Lot Cumulative Device Quantity Units/Hours/Cycles 4 1,545 units 3 314 units 3 1,201 units 4 1,535 units 4 559 units 3 666 units 3 750 units 3 1,249 units # of Fails 0 0 0 0 0 0 0 0 BHAST BHAST BHAST BHAST 85%RH, 130°C, 96 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours 85%RH, 110°C, 264 hours LFXP2-5 LFXP2-17 LCMXO-2280 LC4512 144-TQFP 256-ftBGA 256-ftBGA 256-ftBGA 3 3 3 3 23,040 63,360 63,360 64,944 hours hours hours hours 0 0 0 0 85/85 85/85 85%RH, 85°C, 1000 hours 85%RH, 85°C, 1000 hours LCMXO2-1200 LCMXO2-1200 144-TQFP 132-csBGA 3 3 90,000 hours 90,000 hours 0 0 UHAST UHAST UHAST UHAST UHAST 85%RH, 130°C, 96 hours 85%RH, 130°C, 96 hours 85%RH, 110°C, 264 hours 85%RH, 130°C, 264 hours 85%RH, 130°C, 528 hours LFXP2-5 LCMXO2-1200 LFXP2-17 LC4512 LCMXO2-1200 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 132-csBGA 3 3 3 3 3 31,392 hours 31,392 hours 84,480 hours 30,360 hours 144,144 hours 0 0 0 1 0 LFXP2-5 LCMXO2-1200 LFXP2-17 LC4512 LCMXO-2280 LCMXO2-1200 144-TQFP 144-TQFP 256-ftBGA 256-ftBGA 324-ftBGA 132-csBGA 4 3 4 3 3 3 436,000 326,000 427,000 270,000 327,000 375,000 0 0 0 0 0 0 HTSL HTSL HTSL HTSL HTSL HTSL 150°C, 150°C, 150°C, 150°C, 150°C, 150°C, 1000 1000 1000 1000 1000 1000 hours hours hours hours hours hours hours hours hours hours hours hours INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 14 2.1 Family Qualifications The generation and use of generic data applied across a family of packages emanating from one base assembly process is a Family Qualification, or Qualification-by-Similarity. For the package stresses BHAST or 85/85, UHAST, and HTSL, these are considered generic for a given Package Technology . T/C is considered generic up to an evaluated die size + package size + 10%, for a given Package Technology. Surface Mount Pre -Conditioning (SMPC) is considered generic up to an evaluated Peak Reflow temperature, for a given Package Technology. The foll owing table demonstrates the package stresses qualification matrix. Table 2.1.1 Leaded-QFP Package Qualification-By-Similarity Matrix for ASEM and ASET Advanced Semiconductor Engineering, Malaysia (ASEM) and Taiwan (ASET) Package types to the right are Qualified-by-Similarity using the qualification vehicles below. LFXP2-5, TN144 (Baseline qualification vehicle including the smallest vertical separation to CUP) LFXP6, TN144 (Largest die) LCMXO2-1200, TN144 (Newest family & newest fab technology 65nm SRAM + Flash) Stress Tests 48-TQFP 1.0mm thick, 7x7mm, 0.5mm pitch 44-TQFP 1.0mm thick, 10x10mm, 0.8mm pitch 64-TQFP 1.4mm thick, 10x10mm, 0.5mm pitch 100-TQFP 1.4mm thick, 14x14mm, 0.5mm pitch 128-TQFP 1.4mm thick, 14x14mm, 0.4mm pitch 144-TQFP 1.4mm thick, 20x20mm, 0.5mm pitch SMPC T/C BHAST UHAST HTSL SMPC T/C BHAST UHAST HTSL MSL3 700 cycles 96 hours 96 hours 1000 hours MSL3 1000 cycles SMPC MSL3 T/C 85/85 UHAST HTSL 700 hours 96 hours 1000 hours *Product families (ispMACH 4000ZE, LatticeEC, LatticeECP, LatticeECP2, LatticeECP3, LatticeXP, LatticeXP2, MachXO and MachXO2) assemb led in this assembly technology and b uilt in the package types shown are qualified-b y-similarity using the family generic data from the product/package comb inations ab ove. INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 15 Table 2.1.2 Leaded-QFP Package Qualification-By-Similarity Matrix for ATP and J-Devices Amkor Technology Philippines (ATP) and J-Devices Corporation (J-Devices) Package types to the right are Qualified-by-Similarity using the qualification vehicles below. LFXP2-5, TN144 (Baseline qualification vehicle including the smallest vertical separation to CUP) LFXP6, TN144 (Largest die) LCMXO2-1200, TN144 (Newest family & newest fab technology 65nm SRAM + Flash) LC4128, TN144 Stress Tests 48-TQFP 1.0mm thick, 7x7mm, 0.5mm pitch 44-TQFP 1.0mm thick, 10x10mm, 0.8mm pitch 64-TQFP 1.4mm thick, 10x10mm, 0.5mm pitch 100-TQFP 1.4mm thick, 14x14mm, 0.5mm pitch 128-TQFP 1.4mm thick, 14x14mm, 0.4mm pitch 144-TQFP 1.4mm thick, 20x20mm, 0.5mm pitch SMPC T/C BHAST UHAST HTSL SMPC T/C BHAST UHAST HTSL MSL3 700 cycles 96 hours 96 hours 1000 hours MSL3 1000 cycles SMPC MSL3 T/C 85/85 UHAST HTSL SMPC T/C BHAST UHAST HTSL 700 hours 96 hours 1000 hours MSL3 700 cycles 96 hours 1000 hours *Product families (ispMACH 4000 family, LatticeEC, LatticeECP, LatticeECP2, LatticeECP3, LatticeXP, LatticeXP2, MachXO and MachXO2) assemb led in this assembly technology and b uilt in the package types shown are qualified -b y-similarity using the family generic data from the product/package comb inations ab ove. INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 16 Table 2.1.3 Saw-Singulated BGA Package Qualification-By-Similarity Matrix for ASEM and ASET Advanced Semiconductor Engineering, Malaysia (ASEM) and Taiwan (ASET) Package types to the right are Qualified-bySimilarity using the qualification vehicles below. Stress Tests LFXP2-17, 256-ftBGA (Baseline qualification and smallest vertical CUP separation) SMPC T/C BHAST UHAST HTSL LFXP2-30, 256-ftBGA (Largest die and smallest vertical CUP separation) SMPC T/C BHAST UHAST HTSL LCMXO-2280, 324ftBGA (Largest package) 64 ucBGA (4x4mm, 0.4mm pitch) 64 csBGA (5x5mm, 0.5mm pitch) 132 ucBGA (6x6mm, 0.4mm pitch) 56 csBGA (6x6mm, 0.5mm pitch) 144 csBGA (7x7mm, 0.5mm pitch) 100 csBGA (8x8mm, 0.5mm pitch) 132 csBGA (8x8mm, 0.5mm pitch) 328 256 csBGA caBGA (10x10mm, (14x14mm, 0.5mm 0.8mm pitch) pitch) 332 caBGA 17x17m, 0.8mm pitch) 256 ftBGA (17x17m, 1.0mm pitch) MSL3 264 hours 264 hours 1000 hours MSL3 700 cycles SMPC T/C MSL3 1000 cycles BHAST UHAST HTSL LCMXO-2280, 256ftBGA (Longest wire) SMPC T/C BHAST UHAST HTSL LCMXO2-1200, 132csBGA (Newest family & fab 65nm SRAM + Flash) SMPC T/C 85/85 UHAST HTSL 324 ftBGA (19x19mm, 1.0mm pitch) 1000 hours MSL3 700 cycles 264 hours MSL3 1000 hours 264 hours 1000 hours *Product families (ispMACH 4000ZE, LatticeECP3, LatticeXP2, MachXO and MachXO2) assemb led in this assemb ly technology and b uilt in the package types shown are qualified-by-similarity using the family generic data from the product/package combinations ab ove. INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 17 Table 2.1.4 Saw-Singulated BGA Package Qualification-By-Similarity Matrix for ATP and J-Devices Package types to the right are Qualified-bySimilarity using the qualification vehicles below. LFXP2-17, 256-ftBGA (Baseline qualification and smallest vertical CUP separation) LFXP2-30, 256-ftBGA (Largest die and smallest vertical CUP separation) LCMXO-2280, 324ftBGA (Largest package) LCMXO-2280, 256ftBGA (Longest wire) Amkor Technology Philippines (ATP) and J-Devices Corporation (J-Devices) Stress Tests 64 ucBGA (4x4mm, 0.4mm pitch) 64 csBGA (5x5mm, 0.5mm pitch) 132 ucBGA (6x6mm, 0.4mm pitch) 56 csBGA (6x6mm, 0.5mm pitch) 144 csBGA (7x7mm, 0.5mm pitch) 100 csBGA (8x8mm, 0.5mm pitch) 132 csBGA (8x8mm, 0.5mm pitch) SMPC T/C BHAST UHAST HTSL SMPC T/C BHAST UHAST HTSL 328 csBGA (10x10mm, 0.5mm pitch) 256 332 caBGA caBGA (14x14mm, 17x17mm, 0.8mm 0.8mm pitch) pitch) 256 ftBGA (17x17mm, 1.0mm pitch) MSL3 264 hours 264 hours 1000 hours MSL3 700 cycles SMPC T/C BHAST UHAST HTSL MSL3 700 cycles 1000 hours SMPC T/C MSL3 700 cycles BHAST UHAST HTSL 264 hours LCMXO2-1200, 132csBGA (Newest family & fab 65nm SRAM + Flash) SMPC T/C 85/85 UHAST HTSL LC4512, 256-ftBGA SMPC T/C BHAST UHAST HTSL 324 ftBGA (19x19mm, 1.0mm pitch) MSL3 1000 hours 264 hours 1000 hours MSL3 700 cycles 264 hours 264 hours 1000 hours *Product families (ispMACH 4000 family, LatticeECP3, LatticeXP2, MachXO and MachXO2) assemb led in this assemb ly technology and b uilt in the package types shown are qualified-by-similarity using the family generic data from the product/package combinations above. INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 18 Table 2.1.5 Over-Molded BGA Package Qualification-By-Similarity Matrix Advanced Semiconductor Engineering, Malaysia (ASEM) and Taiwan (ASET); Amkor Technology Philippines (ATP) Package types to the right are Qualified-by-Similarity using the qualification vehicles below. Stress Tests LFXP2-40, 484-fpBGA (Baseline qualification vehicle including the smallest vertical separation to CUP) SMPC T/C BHAST UHAST HTSL LFE2M100, 900-fpBGA (Largest die) SMPC T/C BHAST UHAST HTSL LFE3-150, 1156-fpBGA (Largest package) SMPC T/C BHAST UHAST HTSL LFE2-50, 672-fpBGA (2nd BHAST vehicle) SMPC T/C BHAST UHAST HTSL LCMXO2-7000, 484-fpBGA (Newest family & fab 65nm SRAM+Flash) SMPC T/C 85/85 UHAST HTSL 256 fpBGA (17x17m, 1.0mm pitch) 388 fpBGA (23x23m, 1.0mm pitch) 484 fpBGA (23x23m, 1.0mm pitch) 672 fpBGA (27x27m, 1.0mm pitch) 900 fpBGA (31x31m, 1.0mm pitch) 1152 fpBGA (35x35m, 1.0mm pitch) 1156 fpBGA (35x35m, 1.0mm pitch) MSL3 1000 cycles 264 hours 1000 hours MSL3 1000 cycles 1000 hours MSL3 1000 cycles 264 hours MSL3 264 hours MSL3 1000 hours 264 hours 1000 hours *Product families (LatticeEC, LatticeECP, LatticeECP2M, LatticeECP3, LatticeXP, LatticeXP2, and MachXO2) assemb led in this assembly technology and b uilt in the package types shown are qualified-b y-similarity using the family generic data from the product/package combinations ab ove. INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 19 2.2 Surface Mount Preconditioning Testing The Surface Mount Preconditioning (SMPC) Test is used to model the surface mount assembly conditions during component solder processing. All devices stressed through High Temperature Storage, Temperature Cycling, Un-biased HAST, Biased HAST, or 85/85 were preconditioned. This preconditioning is consistent with J-STD- 020D.1 and JEDEC JESD22-A113 “Preconditioning Procedures of Plastic Surface Mount Devices Prior to Reliability Testing”, Moisture Sensitivity Level 3 (MSL3) package moisture sensitivity and dry -pack storage requirements. Surface Mount Preconditioning (MSL3): (5 Temperature Cycles; 24 hours bake @ 125°C; 30°C/60% RH soak for 192 hours; 3X passes of reflow simulation) performed before all package stresses. MSL3 Packages: TQFP, ucBGA, csBGA, caBGA, ftBGA and fpBGA Method: J-STD-020D.1 and JESD22-A113 Table 2.2.1 Surface Mount Precondition Data (ASEM) 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP Assembly Site ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM Lot Number Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Moisture Soak Level MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 3X Reflow Temperature 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 324-ftBGA 324-ftBGA ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #4 Lot #5 Lot #6 Lot #1 Lot #2 Lot #3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 LFXP2-5 LFXP6 LFXP6 LFXP6 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LFXP2-17 LFXP2-17 LFXP2-17 LFXP2-17 LFXP2-30 LFXP2-30 LFXP2-30 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 Quantity # of Fails 308 308 308 154 77 77 77 184 184 184 0 0 0 0 0 0 0 0 0 0 231 231 231 77 77 77 77 77 154 154 154 77 77 77 154 154 154 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 20 Product Name Package Assembly Site Lot Number Moisture Soak Level 3X Reflow Temperature Quantity # of Fails LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA 132-csBGA ASEM ASEM ASEM Lot #1 Lot #2 Lot #3 MSL3 MSL3 MSL3 260°C 260°C 260°C 184 184 184 0 0 0 LCMXO2-7000 LCMXO2-7000 LCMXO2-7000 LFXP2-40 LFXP2-40 LFXP2-40 LFXP2-40 LFE2-50 LFE2-50 LFE2-50 LFE2M100 LFE2M100 LFE2M100 LFE3-150 LFE3-150 LFE3-150 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 672-fpBGA 672-fpBGA 672-fpBGA 900-fpBGA 900-fpBGA 900-fpBGA 1156-fpBGA 1156-fpBGA 1156-fpBGA ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 260°C 260°C 260°C 260°C 260°C 260°C 260°C 250°C 250°C 250°C 250°C 250°C 250°C 250°C 250°C 250°C 184 184 184 231 227B 231 154 77 77 77 154 154 154 154 154 154 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. B = Four units removed due to mechanical handler damage. Cumulative SMPC Failure Rate = 0 / 7,196 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 21 Table 2.2.2 Surface Mount Precondition Data (ASET) 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP Assembly Site ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET Lot Number Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Moisture Soak Level MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 3X Reflow Temperature 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C LFXP2-17 LFXP2-17 LFXP2-17 LFXP2-17 LFXP2-30 LFXP2-30 LFXP2-30 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 324-ftBGA 324-ftBGA ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA 132-csBGA ASET ASET ASET Lot #1 Lot #2 Lot #3 LCMXO2-7000 LCMXO2-7000 LCMXO2-7000 LFXP2-40 LFXP2-40 LFXP2-40 LFXP2-40 LFE2-50 LFE2-50 LFE2-50 LFE2M100 LFE2M100 LFE2M100 LFE3-150 LFE3-150 LFE3-150 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 672-fpBGA 672-fpBGA 672-fpBGA 900-fpBGA 900-fpBGA 900-fpBGA 1156-fpBGA 1156-fpBGA 1156-fpBGA ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 LFXP2-5 LFXP6 LFXP6 LFXP6 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 Quantity # of Fails 231 231 231 154 77 77 77 231 231 231 0 0 0 0 0 0 0 0 0 0 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 154 154 154 77 77 77 77 77 154 154 154 0 0 0 0 0 0 0 0 0 0 0 MSL3 MSL3 MSL3 260°C 260°C 260°C 271 271 270 0 0 0 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 260°C 260°C 260°C 260°C 260°C 260°C 260°C 250°C 250°C 250°C 250°C 250°C 250°C 250°C 250°C 250°C 231 231 231 231 231 231 154 85 85 85 154 154 154 77 77 77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. Cumulative SMPC Failure Rate = 0 / 6,380 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 22 Table 2.2.3 Surface Mount Precondition Data (ATP) 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP Assembly Site ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP Lot Number Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Moisture Soak Level MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 3X Reflow Temperature 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C LFXP2-17 LFXP2-17 LFXP2-17 LFXP2-17 LFXP2-30 LFXP2-30 LFXP2-30 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO-2280 LC4512 LC4512 LC4512 LCMXO-2280 LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 324-ftBGA 324-ftBGA ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA 132-csBGA ATP ATP ATP Lot #1 Lot #2 Lot #3 LCMXO2-7000 LCMXO2-7000 LCMXO2-7000 LFXP2-40 LFXP2-40 LFXP2-40 LFXP2-40 LFE2-50 LFE2-50 LFE2-50 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 672-fpBGA 672-fpBGA 672-fpBGA ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 LFXP2-5 LFXP6 LFXP6 LFXP6 LC4128 LC4128 LC4128 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 Quantity # of Fails 316 316 316 154 77 77 77 339 340 341 286 286 286 0 0 0 0 0 0 0 0 0 0 0 0 0 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 239 239 239 77 77 77 77 77 162 162 162 231 231 231 154 154 154 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSL3 MSL3 MSL3 260°C 260°C 260°C 276 276 276 0 0 0 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 260°C 260°C 260°C 260°C 260°C 260°C 260°C 250°C 250°C 250°C 194 194 194 231 231 231 154 77 77 77 0 0 0 0 0 0 0 0 0 0 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 23 Product Name Package LFE2M100 LFE2M100 LFE2M100 LFE3-150 LFE3-150 LFE3-150 900-fpBGA 900-fpBGA 900-fpBGA 1156-fpBGA 1156-fpBGA 1156-fpBGA Assembly Site ATP ATP ATP ATP ATP ATP Lot Number Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Moisture Soak Level MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 3X Reflow Temperature 250°C 250°C 250°C 250°C 250°C 250°C Quantity # of Fails 154 154 154 162 162 162 0 0 0 0 0 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. Cumulative SMPC Failure Rate = 0 / 9,390 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 24 Table 2.2.4 Surface Mount Precondition Data (J-Devices) 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP Assembly Site J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices Lot Number Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Moisture Soak Level MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 3X Reflow Temperature 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C LFXP2-17 LFXP2-17 LFXP2-17 LFXP2-17 LFXP2-30 LFXP2-30 LFXP2-30 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 324-ftBGA 324-ftBGA J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 MSL3 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA 132-csBGA J-Devices J-Devices J-Devices Lot #1 Lot #2 Lot #3 MSL3 MSL3 MSL3 Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 LFXP2-5 LFXP6 LFXP6 LFXP6 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 Quantity # of Fails 435 435 435 240 107 101 106 402 403 396 0 0 0 0 0 0 0 0 0 0 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 434 434 433 234 140 140 140 139 222 222 222 250 250 250 0 0 0 0 0 0 0 0 0 0 0 0 0 0 260°C 260°C 260°C 447 401B 401B 0 0 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. B = One unit removed due to mechanical handler damage. Cumulative SMPC Failure Rate = 0 / 7,819 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 25 2.3 Temperature Cycling (TC) The Temperature Cycling test is used to accelerate those failures resulting from mechanical stresses induced by differential thermal expansion of adjacent films, layers and metallurgical interfaces in the die and package. Devices are tested at 25°C after exposure to repeated cycling between -55°C and +125°C in an air environment consistent with JEDEC JESD22-A104 “Temperature Cycling”, Condition B temperature cycling requirements . Prior to Temperature Cycling testing, all devices are subjected to Surface Mount Preconditioning. MSL3 Packages: TQFP, μcBGA, csBGA, caBGA, ftBGA and fpBGA Stress Duration: 1000 cycles Stress Conditions: Temperature cycling between -55°C to 125°C Method: JESD22-A104, Condition B Table 2.3.1 Temperature Cycling Data (ASEM) Product Name Package Assembly Site Lot Number Stress Temperature Stress Duration LFXP2-5 LFXP2-5 LFXP2-5 LFXP2-5 LFXP6 LFXP6 LFXP6 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP ASEM ASEM ASEM ASEM ASEM ASEM ASEM Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 -55°C -55°C -55°C -55°C -55°C -55°C -55°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C 1000 1000 1000 1000 1000 1000 1000 LFXP2-30 LFXP2-30 LFXP2-30 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 324-ftBGA 324-ftBGA ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C LFXP2-40 LFXP2-40 LFXP2-40 LFXP2-40 LFE2M100 LFE2M100 LFE2M100 LFE3-150 LFE3-150 LFE3-150 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 900-fpBGA 900-fpBGA 900-fpBGA 1156-fpBGA 1156-fpBGA 1156-fpBGA ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C Quantity # of Fails cycles cycles cycles cycles cycles cycles cycles 77 77 77 77 77 76C 77 0 0 0 0 0 0 0 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles 77 77 77 77 77 77 77 77 77 77 0 0 0 0 0 1B 0 0 0 0 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles 77 77 77 77 77 77 77 77 77 77 0 0 0 0 0 0 0 0 0 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. B = One random assembly defect unrelated to copper wireb ond process. Cumulative Temp Cycle Failure Rate = 1 / 2,078 C = One unit removed due to mechanical handler damage. Cumulative device Temp Cycles = 2,078,000 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 26 Table 2.3.2 Temperature Cycling Data (ASET) 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP Assembly Site ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET Lot Number Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Stress Temperature -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C Stress Duration 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles LFXP2-30 LFXP2-30 LFXP2-30 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 324-ftBGA 324-ftBGA ASET ASET ASET ASET ASET ASET ASET Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 -55°C -55°C -55°C -55°C -55°C -55°C -55°C 1000 1000 1000 1000 1000 1000 1000 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA 132-csBGA ASET ASET ASET Lot #1 Lot #2 Lot #3 LFXP2-40 484-fpBGA LFXP2-40 484-fpBGA LFXP2-40 484-fpBGA LFXP2-40 484-fpBGA LCMXO2-7000 484-fpBGA LCMXO2-7000 484-fpBGA LCMXO2-7000 484-fpBGA LFE2M100 900-fpBGA LFE2M100 900-fpBGA LFE2M100 900-fpBGA LFE3-150 1156-fpBGA LFE3-150 1156-fpBGA LFE3-150 1156-fpBGA ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET ASET Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 LFXP2-5 LFXP6 LFXP6 LFXP6 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 Quantity # of Fails 77 77 77 77 77 77 77 77 77 77 0 0 0 0 0 0 0 0 0 0 cycles cycles cycles cycles cycles cycles cycles 77 77 77 77 77 77 77 0 0 0 0 0 0 0 -55°C to 125°C -55°C to 125°C -55°C to 125°C 1000 cycles 1000 cycles 1000 cycles 77 77 77 0 0 0 -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 77 77 77 77 77 77 77 77 77 77 77 77 77 0 0 0 0 0 0 0 0 0 0 0 0 0 to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. Cumulative Temp Cycle Failure Rate = 0 / 2,541 Cumulative device Temp Cycles = 2,541,000 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 27 Table 2.3.3 Temperature Cycling Data (ATP) 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP Assembly Site ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP Lot Number Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Stress Temperature -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C Stress Duration 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles LFXP2-30 LFXP2-30 LFXP2-30 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO-2280 LC4512 LC4512 LC4512 LCMXO-2280 LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 324-ftBGA 324-ftBGA ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA 132-csBGA ATP ATP ATP Lot #1 Lot #2 Lot #3 LFXP2-40 LFXP2-40 LFXP2-40 LFXP2-40 LCMXO2-7000 LCMXO2-7000 LCMXO2-7000 LFE2-50 LFE2-50 LFE2-50 LFE2M100 LFE2M100 LFE2M100 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 672-fpBGA 672-fpBGA 672-fpBGA 900-fpBGA 900-fpBGA 900-fpBGA ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP ATP Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #1 Lot #2 Lot #3 Lot #2 Lot #3 Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 LFXP2-5 LFXP6 LFXP6 LFXP6 LC4128 LC4128 LC4128 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 Quantity # of Fails 77 77 77 77 77 77 77 77 77 77 77 77 77 0 0 0 0 0 0 0 0 0 0 0 0 0 cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles 77 77 77 77 77 77 77 77 77 77 77 77 77 0 0 0 0 0 0 0 0 0 0 0 0 0 -55°C to 125°C -55°C to 125°C -55°C to 125°C 1000 cycles 1000 cycles 1000 cycles 77 77 77 0 0 0 -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 77 77 77 77 77 77 77 77 77 77 77 77 77 0 0 0 0 0 0 0 0 0 0 0 0 0 to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 28 Product Name Package LFE3-150 LFE3-150 LFE3-150 1156-fpBGA 1156-fpBGA 1156-fpBGA Assembly Site ATP ATP ATP Lot Number Lot #1 Lot #2 Lot #3 Stress Temperature -55°C to 125°C -55°C to 125°C -55°C to 125°C Stress Duration 1000 cycles 1000 cycles 1000 cycles Quantity # of Fails 77 77 77 0 0 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. Cumulative Temp Cycle Failure Rate = 0 / 3,465 Cumulative device Temp Cycles = 3,465,000 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 29 Table 2.3.4 Temperature Cycling Data (J-Devices) 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP Assembly Site J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices Lot Number Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Stress Temperature -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C -55°C to 125°C Stress Duration 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles 1000 cycles LFXP2-30 LFXP2-30 LFXP2-30 LFXP2-30 LCMXO-2280 LCMXO-2280 LCMXO-2280 LC4512 LC4512 LC4512 LCMXO-2280 LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 324-ftBGA 324-ftBGA 324-ftBGA J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices Lot #1 Lot #2 Lot #3 Lot #4A Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C -55°C 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA 132-csBGA J-Devices J-Devices J-Devices Lot #1 Lot #2 Lot #3 -55°C to 125°C -55°C to 125°C -55°C to 125°C Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 LFXP2-5 LFXP6 LFXP6 LFXP6 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C to 125°C Quantity # of Fails 109 106 109 109 92 92 92 109 109 109 0 0 0 0 0 0 0 0 0 0 cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles 114 114 114 114 126 126 126 90 90 90 109 109 109 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 cycles 1000 cycles 1000 cycles 126 126 126 0 0 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. Cumulative Temp Cycle Failure Rate = 0 / 2,845 Cumulative device Temp Cycles = 2,845,000 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 30 2.4 Unbiased HAST Unbiased Highly Accelerated Stress Test (HAST) testing uses both pressure and temperature to accelerate penetration of moisture into the package and to the die surface. The Unbiased HAST test is designed to detect ionic contaminants present within the package or on the die surface, which can cause chemical corrosion. Consistent with JEDEC JESD22-A118, “Accelerated Moisture Resistance - Unbiased HAST,” the Unbiased HAST conditions are either 96 hours exposure at 130°C and 85% relative humidity, or 264 hours exposure at 110°C and 85% relative humidity. Prior to Unbiased HAST testing, all devices are subjected to Surface Mount Preconditioning. MSL3 Packages: TQFP, μcBGA, csBGA, caBGA, ftBGA and fpBGA Stress Conditions: 130°C/85% RH or 110°C/85% RH Stress Duration: 96 hours or 264 hours, respectively Method: JESD22-A118 Table 2.4.1 Unbiased HAST Data (ASEM) 144-TQFP Assembly Site ASEM Lot Number Lot #1 Stress Humidity 85% RH Stress Temperature 130°C Stress Duration 96 hours 77 # of Fails 0 LFXP2-5 144-TQFP ASEM Lot #2 85% RH 130°C LFXP2-5 144-TQFP ASEM Lot #3 85% RH 130°C 96 hours 77 0 96 hours 77 0 LCMXO2-1200 144-TQFP ASEM Lot #1 85% RH 130°C 96 hours 77 0 LCMXO2-1200 144-TQFP ASEM Lot #2 85% RH 130°C 96 hours 77 0 LCMXO2-1200 144-TQFP ASEM Lot #3 85% RH 130°C 96 hours 77 0 LFXP2-17 LFXP2-17 LFXP2-17 256-ftBGA 256-ftBGA 256-ftBGA ASEM ASEM ASEM Lot #1 Lot #2 Lot #3 85% RH 85% RH 85% RH 110°C 110°C 110°C 264 hours 264 hours 264 hours 77 77 76A 0 0 0 LCMXO2-1200 LCMXO2-1200 132-csBGA ASEM Lot #1 85% RH 110°C 264 hours 77 0 132-csBGA ASEM Lot #2 85% RH 110°C 264 hours 77 0 LCMXO2-1200 132-csBGA ASEM Lot #3 85% RH 110°C 264 hours 77 0 LCMXO2-7000 LCMXO2-7000 LCMXO2-7000 LFXP2-40 LFXP2-40 LFXP2-40 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA ASEM ASEM ASEM ASEM ASEM ASEM Lot Lot Lot Lot Lot Lot 85% 85% 85% 85% 85% 85% 110°C 110°C 110°C 110°C 110°C 110°C 264 264 264 264 264 264 77 77 77 77 73 77 0 0 0 0 0 0 Product Name Package LFXP2-5 #1 #2 #3 #1 #2 #3 RH RH RH RH RH RH hours hours hours hours hours hours Qty A = One unit removed due to mechanical handler damage. Cumulative Unbiased HAST failure Rate = 0 / 1,381 Cumulative Unbiased device hours = 286,968 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 31 Table 2.4.2 Unbiased HAST Data (ASET) 144-TQFP 144-TQFP 144-TQFP 144-TQFP Assembly Site ASET ASET ASET ASET Lot Number Lot #1 Lot #2 Lot #3 Lot #1 Stress Humidity 85% RH 85% RH 85% RH 85% RH Stress Temperature 130°C 130°C 130°C 130°C Stress Duration 96 hours 96 hours 96 hours 96 hours LCMXO2-1200 LCMXO2-1200 144-TQFP 144-TQFP ASET ASET Lot #2 Lot #3 85% RH 85% RH 130°C 130°C LFXP2-17 LFXP2-17 LFXP2-17 256-ftBGA 256-ftBGA 256-ftBGA ASET ASET ASET Lot #1 Lot #2 Lot #3 85% RH 85% RH 85% RH LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA 132-csBGA ASET ASET ASET Lot #1 Lot #2 Lot #3 LCMXO2-7000 LCMXO2-7000 LCMXO2-7000 LFXP2-40 LFXP2-40 LFXP2-40 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA ASET ASET ASET ASET ASET ASET Lot Lot Lot Lot Lot Lot Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 LCMXO2-1200 #1 #2 #3 #1 #2 #3 77 77 77 77 # of Fails 0 0 0 0 96 hours 96 hours 77 77 0 0 110°C 110°C 110°C 264 hours 264 hours 264 hours 77 77 77 0 0 0 85% RH 85% RH 85% RH 110°C 110°C 110°C 264 hours 264 hours 264 hours 77 77 77 0 0 0 85% 85% 85% 85% 85% 85% 110°C 110°C 110°C 110°C 110°C 110°C 264 264 264 264 264 264 77 77 77 77 77 77 0 0 0 0 0 0 RH RH RH RH RH RH hours hours hours hours hours hours Qty Cumulative Unbiased HAST failure Rate = 0 / 1,386 Cumulative Unbiased device hours = 288,288 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 32 Table 2.4.3 Unbiased HAST Data (ATP) 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP 144-TQFP Assembly Site ATP ATP ATP ATP ATP ATP ATP Lot Number Lot #1 Lot #2 Lot #3 Lot #1 Lot #2 Lot #3 Lot #1 Stress Humidity 85% RH 85% RH 85% RH 85% RH 85% RH 85% RH 85% RH Stress Temperature 110°C 110°C 110°C 130°C 130°C 130°C 130°C Stress Duration 264 hours 264 hours 264 hours 264 hours 264 hours 264 hours 96 hours LCMXO2-1200 LCMXO2-1200 144-TQFP 144-TQFP ATP ATP Lot #2 Lot #3 85% RH 85% RH 130°C 130°C 96 hours 96 hours LFXP2-17 LFXP2-17 LFXP2-17 LC4512 LC4512 LC4512 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA ATP ATP ATP ATP ATP ATP Lot Lot Lot Lot Lot Lot 85% 85% 85% 85% 85% 85% RH RH RH RH RH RH 110°C 110°C 110°C 110°C 110°C 110°C 264 264 264 264 264 264 LCMXO2-1200 132-csBGA ATP Lot #1 85% RH LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA ATP ATP Lot #2 Lot #3 LCMXO2-7000 LCMXO2-7000 LCMXO2-7000 LFXP2-40 LFXP2-40 LFXP2-40 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA 484-fpBGA ATP ATP ATP ATP ATP ATP Lot Lot Lot Lot Lot Lot Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 LC4128 LC4128 LC4128 LCMXO2-1200 #1 #2 #3 #1 #2 #3 #1 #2 #3 #1 #2 #3 77 77 77 77 77 77 77 # of Fails 0 0 0 0 0 0 0 77 77 0 0 hours hours hours hours hours hours 77 77 77 77 77 77 0 0 0 0 0 0 110°C 264 hours 77 0 85% RH 85% RH 110°C 110°C 264 hours 264 hours 77 77 0 0 85% 85% 85% 85% 85% 85% 110°C 110°C 110°C 110°C 110°C 110°C 264 264 264 264 264 264 77 77 77 77 77 77 0 0 0 0 0 0 RH RH RH RH RH RH hours hours hours hours hours hours Qty Cumulative Unbiased HAST failure Rate = 0 / 1,848 Cumulative Unbiased device hours = 449,064 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 33 Table 2.4.4 Unbiased HAST Data (J-Devices) 144-TQFP 144-TQFP 144-TQFP Assembly Site J-Devices J-Devices J-Devices Lot Number Lot #1 Lot #2 Lot #3 Stress Humidity 85% RH 85% RH 85% RH Stress Temperature 130°C 130°C 130°C Stress Duration 96 hours 96 hours 96 hours LCMXO2-1200 144-TQFP J-Devices Lot #1 85% RH 130°C LCMXO2-1200 144-TQFP J-Devices Lot #2 85% RH LCMXO2-1200 144-TQFP J-Devices Lot #3 LFXP2-17 LFXP2-17 LFXP2-17 LC4512 LC4512 LC4512 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA 256-ftBGA J-Devices J-Devices J-Devices J-Devices J-Devices J-Devices Lot Lot Lot Lot Lot Lot LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA J-Devices J-Devices LCMXO2-1200 132-csBGA J-Devices Product Name Package LFXP2-5 LFXP2-5 LFXP2-5 109 109 109 # of Fails 0 0 0 96 hours 109 0 130°C 96 hours 109 0 85% RH 130°C 96 hours 109 0 85% 85% 85% 85% 85% 85% RH RH RH RH RH RH 110°C 110°C 110°C 130°C 130°C 130°C 264 264 264 264 264 264 109 105 106 40 51 24 0 0 0 0 0 1A Lot #1 Lot #2 85% RH 85% RH 130°C 130°C 528 hours 528 hours 94 93 0 0 Lot #3 85% RH 130°C 528 hours 86 0 #1 #2 #3 #1 #2 #3 hours hours hours hours hours hours Qty A = J-Devices 8D found lifted b all b ond. Corrective actions implemented. Validation in process. Due Q2’15. Cumulative Unbiased HAST failure Rate = 1 / 1,362 Cumulative Unbiased device hours = 321,768 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 34 2.5 THB: Biased HAST or 85/85 Highly Accelerated Stress Test (HAST) testing uses both pressure and temperature to accelerate penetration of moisture into the package and to the die surface. The Biased HAST test is used to accelerate threshold shifts in the MOS device associated with moisture diffusion into the gate oxide region as well as electrochemical corrosion mechanisms within the device package. Consistent with JEDEC JESD22-A110 “Highly-Accelerated Temperat ure and Humidity Stress Test (HAST)”, the biased HAST conditions are either 96 hours exposure at 130°C and 85% relative humidity, or 264 hours exposure at 110°C and 85% relative humidity or JEDEC JESD22-A101 “Steady State Temperature Humidity Bias Life Test (THB or 85/85)”, the 85/85 conditions are 1000 hours exposure at 85°C and 85% relative humidity. Prior to Biased HAST or 85/85 testing, all devices are subjected to Surface Mount Preconditioning. MSL3 Packages: TQFP, μcBGA, csBGA, caBGA, ftBGA and fpBGA Stress Conditions: Vcc= Max operating condition and 130°C/85% RH, 110°C/85% RH or 85°C/85% RH Stress Duration: 96 Hours, 264 hours, or 1000 hours respectively Method: JESD22-A110 or JESD22-A101 Table 2.5.1 THB Data (ASEM) 144-TQFP Assembly Site ASEM Lot Number Lot #1 Stress Humidity 85% RH Stress Temperature 130°C Stress Duration 96 hours 77 # of Fails 0 LFXP2-5 LFXP2-5 144-TQFP 144-TQFP ASEM ASEM Lot #2 Lot #3 85% RH 85% RH 130°C 130°C 96 hours 96 Hours 77 77 0 0 LCMXO2-1200 LCMXO2-1200 144-TQFP 144-TQFP ASEM ASEM Lot #1 Lot #2 85% RH 85% RH 85°C 85°C 1000 hours 1000 hours 25 25 0 0 LCMXO2-1200 144-TQFP ASEM Lot #3 85% RH 85°C 1000 hours 25 0 LFXP2-17 256-ftBGA ASEM Lot #1 85% RH 110°C 264 hours 77 0 LFXP2-17 LFXP2-17 256-ftBGA 256-ftBGA ASEM ASEM Lot #2 Lot #3 85% RH 85% RH 110°C 110°C 264 hours 264 hours 77 77 0 0 LCMXO-2280 256-ftBGA ASEM Lot #1 85% RH 110°C 264 hours 77 1A LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA ASEM ASEM Lot #2 Lot #3 85% RH 85% RH 110°C 110°C 264 hours 264 hours 77 77 1A 1A LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA ASEM ASEM Lot #4 Lot #5 85% RH 85% RH 110°C 110°C 264 hours 264 hours 77 77 0 0 LCMXO-2280 256-ftBGA ASEM Lot #6 85% RH 110°C 264 hours 77 1A LCMXO2-1200 132-csBGA ASEM Lot #1 85% RH 85°C 1000 hours 25 0 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA ASEM ASEM Lot #2 Lot #3 85% RH 85% RH 85°C 85°C 1000 hours 1000 hours 25 25 1B 0 Product Name Package LFXP2-5 Qty INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 35 Product Name Package Assembly Site Lot Number Stress Humidity Stress Temperature Stress Duration Qty # of Fails LFE2-50 672-fpBGA ASEM Lot #1 85% RH 110°C 264 hours 77 0 LFE2-50 LFE2-50 672-fpBGA 672-fpBGA ASEM ASEM Lot #2 Lot #3 85% RH 85% RH 110°C 110°C 264 hours 264 hours 77 77 0 1A LFE3-150 1156-fpBGA ASEM Lot #1 85% RH 110°C 264 hours 75C 0 LFE3-150 LFE3-150 1156-fpBGA 1156-fpBGA ASEM ASEM Lot #2 Lot #3 85% RH 85% RH 110°C 110°C 264 hours 264 hours 75C 75C 0 0 LCMXO2-7000 LCMXO2-7000 484-fpBGA 484-fpBGA ASEM ASEM Lot #1 Lot #2 85% RH 85% RH 85°C 85°C 1000 hours 1000 hours 25 25 0 0 LCMXO2-7000 484-fpBGA ASEM Lot #3 85% RH 85°C 1000 hours 25 0 A = One random assembly defect at 264 hours, unrelated to copper wireb ond process. B = One random assembly defect unrelated to copper wireb ond process. C = Sample size limited to b oard capacity. Cumulative THB failure Rate = 6 / 1,607 Cumulative THB device hours = 656,952 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 36 Table 2.5.2 THB Data (ASET) 144-TQFP Assembly Site ASET Lot Number Lot #1 Stress Humidity 85% RH Stress Temperature 130°C Stress Duration 96 hours 82 # of Fails 0 144-TQFP ASET Lot #2 85% RH 130°C 96 hours 82 0 LFXP2-5 LCMXO2-1200 144-TQFP 144-TQFP ASET ASET Lot #3 Lot #1 85% RH 85% RH 130°C 85°C 96 Hours 1000 hours 82 35 0 0 LCMXO2-1200 LCMXO2-1200 144-TQFP 144-TQFP ASET ASET Lot #2 Lot #3 85% RH 85% RH 85°C 85°C 1000 hours 1000 hours 35 35 0 0 LFXP2-17 LFXP2-17 256-ftBGA 256-ftBGA ASET ASET Lot #1 Lot #2 85% RH 85% RH 110°C 110°C 264 hours 264 hours 82 82 0 0 LFXP2-17 256-ftBGA ASET Lot #3 85% RH 110°C 264 hours 82 0 LCMXO2-1200 132-csBGA ASET Lot #1 85% RH 85°C 1000 hours 35 0 LCMXO2-1200 132-csBGA LCMXO2-1200 132-csBGA ASET ASET Lot #2 Lot #3 85% RH 85% RH 85°C 85°C 1000 hours 1000 hours 35 34 0 0 LCMXO2-7000 484-fpBGA ASET Lot #1 85% RH 85°C 1000 hours 35 0 LCMXO2-7000 484-fpBGA ASET Lot #2 85% RH 85°C 1000 hours 35 0 LCMXO2-7000 484-fpBGA ASET Lot #3 85% RH 85°C 1000 hours 35 0 Product Name Package LFXP2-5 LFXP2-5 Qty Cumulative THB failure Rate = 0 / 806 Cumulative THB device hours = 402,560 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 37 Table 2.5.3 THB Data (ATP) 144-TQFP Assembly Site ATP Lot Number Lot #1 Stress Humidity 85% RH Stress Temperature 130°C Stress Duration 96 hours 80 # of Fails 0 144-TQFP ATP Lot #2 85% RH 130°C 96 hours 80 0 LFXP2-5 LC4128 144-TQFP 144-TQFP ATP ATP Lot #3 Lot #1 85% RH 85% RH 130°C 130°C 96 Hours 96 Hours 79 108 1A 0 LC4128 LC4128 144-TQFP 144-TQFP ATP ATP Lot #2 Lot #3 85% RH 85% RH 130°C 130°C 96 Hours 96 Hours 109 107 1A 0 LCMXO2-1200 144-TQFP ATP Lot #1 85% RH 85°C 1000 hours 29 1A LCMXO2-1200 LCMXO2-1200 144-TQFP 144-TQFP ATP ATP Lot #2 Lot #3 85% RH 85% RH 85°C 85°C 1000 hours 1000 hours 29 30 1A 0 LFXP2-17 256-ftBGA ATP Lot #1 85% RH 110°C 264 hours 80 0 LFXP2-17 256-ftBGA ATP Lot #2 85% RH 110°C 264 hours 78 2A LFXP2-17 LCMXO-2280 256-ftBGA 256-ftBGA ATP ATP Lot #3 Lot #1 85% RH 85% RH 110°C 110°C 264 hours 264 hours 80 80 0 0 LCMXO-2280 LCMXO-2280 256-ftBGA 256-ftBGA ATP ATP Lot #2 Lot #3 85% RH 85% RH 110°C 110°C 264 hours 264 hours 79 80 1A 0 LC4512 256-ftBGA ATP Lot #1 85% RH 110°C 264 hours 77 0 LC4512 LC4512 256-ftBGA 256-ftBGA ATP ATP Lot #2 Lot #3 85% RH 85% RH 110°C 110°C 264 hours 264 hours 77 77 0 0 LCMXO2-1200 132-csBGA ATP Lot #1 85% RH 85°C 1000 hours 30 0 LCMXO2-1200 132-csBGA ATP Lot #2 85% RH 85°C 1000 hours 30 0 LCMXO2-1200 132-csBGA ATP Lot #3 85% RH 85°C 1000 hours 30 0 LCMXO2-7000 484-fpBGA LCMXO2-7000 484-fpBGA ATP ATP Lot #1 Lot #2 85% RH 85% RH 85°C 85°C 1000 hours 1000 hours 25 25 0 0 LCMXO2-7000 484-fpBGA Product Name Package LFXP2-5 LFXP2-5 Qty ATP Lot #3 85% RH 85°C 1000 hours 25 0 LFE2-50 LFE2-50 672-fpBGA 672-fpBGA ATP ATP Lot #1 Lot #2 85% RH 85% RH 110°C 110°C 264 hours 264 hours 80 80 0 0 LFE2-50 672-fpBGA ATP Lot #3 85% RH 110°C 264 hours 80 0 A = Amkor 8D found engineering lot handling issue, corrective actions implemented. Validation in process. Due Q2’15. Cumulative THB failure Rate = 7 / 1,764 Cumulative THB device hours = 557,320 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 38 Table 2.5.4 THB Data (J-Devices) 144-TQFP Assembly Site J-Devices Lot Number Lot #1 Stress Humidity 85% RH Stress Temperature 130°C Stress Duration 96 hours 80 # of Fails 0 144-TQFP J-Devices Lot #2 85% RH 130°C 96 hours 80 0 LFXP2-5 144-TQFP LCMXO2-1200 144-TQFP J-Devices J-Devices Lot #3 Lot #1 85% RH 85% RH 130°C 85°C 96 Hours 1000 hours 80 30 0 0 LCMXO2-1200 144-TQFP LCMXO2-1200 144-TQFP J-Devices J-Devices Lot #2 Lot #3 85% RH 85% RH 85°C 85°C 1000 hours 1000 hours 30 30 0 0 256-ftBGA 256-ftBGA J-Devices J-Devices Lot #1 Lot #2 85% RH 85% RH 110°C 110°C 264 hours 264 hours 80 80 0 0 LFXP2-17 256-ftBGA LCMXO-2280 256-ftBGA J-Devices J-Devices Lot #3 Lot #1 85% RH 85% RH 110°C 110°C 264 hours 264 hours 80 80 0 0 LCMXO-2280 256-ftBGA J-Devices Lot #2 85% RH 110°C 264 hours 80 0 LCMXO-2280 256-ftBGA LC4512 256-ftBGA J-Devices J-Devices Lot #3 Lot #1 85% RH 85% RH 110°C 110°C 264 hours 264 hours 80 82 0 0 J-Devices J-Devices Lot #2 Lot #3 85% RH 85% RH 110°C 110°C 264 hours 264 hours 82 82 0 0 LCMXO2-1200 132-csBGA LCMXO2-1200 132-csBGA J-Devices J-Devices Lot #1 Lot #2 85% RH 85% RH 85°C 85°C 1000 hours 1000 hours 30 30 0 0 LCMXO2-1200 132-csBGA J-Devices Lot #3 85% RH 85°C 1000 hours 30 0 Product Name Package LFXP2-5 LFXP2-5 LFXP2-17 LFXP2-17 LC4512 LC4512 256-ftBGA 256-ftBGA Qty Cumulative THB failure Rate = 0 / 1,146 Cumulative THB device hours = 394,704 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 39 2.6 High Temperature Storage Life The High Temperature Storage Life test is used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms. Consistent with JEDEC JESD22-A103, the devices are subjected to high temperature storage Condition B: +150 (-0/+10) °C for 1000 hours. Prior to High Temperat ure Storage, all devices are subjected to Surface Mount Preconditioning. This is a relatively new requ irement consistent with JESD47 for Pb-free, wirebonded packages. MSL3 Packages: TQFP, μcBGA, csBGA, caBGA, ftBGA and fpBGA Stress Duration: 1000 hours Temperature: 150°C (ambient) Method: JESD22-A103 Table 2.6.1 High Temperature Storage Life Data (ASEM) Assembly Lot Site Number ASEM Lot # 1 ASEM Lot # 2 Stress Temperature 150°C 150°C Stress Duration 1000 hours 1000 hours Lot # 3 150°C Lot # 4A Lot #1 150°C 150°C Lot #2 Lot #3 ASEM ASEM 256-ftBGA 256-ftBGA LCMXO-2280 LCMXO-2280 LCMXO-2280 LCMXO2-1200 Product Name Package Quantity # of Fails LFXP2-5 LFXP2-5 144-TQFP 144-TQFP 77 77 1B 0 LFXP2-5 144-TQFP ASEM LFXP2-5 LCMXO2-1200 144-TQFP 144-TQFP ASEM ASEM 1000 hours 77 0 1000 hours 1000 hours 77 77 0 0 LCMXO2-1200 LCMXO2-1200 144-TQFP 144-TQFP ASEM ASEM 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFXP2-17 LFXP2-17 256-ftBGA 256-ftBGA Lot #1 Lot #2 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFXP2-17 LFXP2-17 ASEM ASEM Lot #3 Lot #4A 150°C 150°C 1000 hours 1000 hours 77 76C 0 0 324-ftBGA ASEM Lot #1 150°C 1000 hours 77 0 324-ftBGA 324-ftBGA ASEM ASEM Lot #2 Lot #3 150°C 150°C 1000 hours 1000 hours 77 77 0 0 132-csBGA ASEM Lot #1 150°C 1000 Hours 77 0 0 LCMXO2-1200 132-csBGA ASEM Lot #2 150°C 1000 Hours 76C LCMXO2-1200 132-csBGA ASEM Lot #3 150°C 1000 Hours 77 0 LCMXO2-7000 LCMXO2-7000 484-fpBGA 484-fpBGA ASEM ASEM Lot #1 Lot #2 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LCMXO2-7000 484-fpBGA ASEM Lot #3 150°C 1000 hours 77 0 LFXP2-40 LFXP2-40 484-fpBGA 484-fpBGA ASEM ASEM Lot #1 Lot #2 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFXP2-40 LFXP2-40 484-fpBGA 484-fpBGA ASEM ASEM Lot #3 Lot #4 A 150°C 150°C 1000 hours 1000 hours 77 77 0 0 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 40 Assembly Lot Site Number ASEM Lot #1 Product Name Package LFE2M100 900-fpBGA LFE2M100 900-fpBGA ASEM LFE2M100 900-fpBGA ASEM Stress Temperature 150°C Stress Duration 1000 hours Lot #2 150°C Lot #3 150°C Quantity # of Fails 77 0 1000 hours 77 0 1000 hours 77 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. B = One random assembly defect unrelated to copper wireb ond process. C = One unit removed due to mechanical handler damage. Cumulative HTSL failure Rate = 1 / 2,077 Cumulative HTSL device hours = 2,077,000 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 41 Table 2.6.2 High Temperature Storage Life Data (ASET) Assembly Lot Site Number ASET Lot # 1 Stress Temperature 150°C Stress Duration 1000 hours Lot # 2 150°C 1000 hours ASET ASET Lot # 3 Lot # 4A 150°C 150°C 144-TQFP 144-TQFP ASET ASET Lot #1 Lot #2 LCMXO2-1200 144-TQFP ASET LFXP2-17 256-ftBGA LFXP2-17 LFXP2-17 Product Name Package Quantity # of Fails LFXP2-5 144-TQFP LFXP2-5 144-TQFP ASET 77 0 77 0 LFXP2-5 LFXP2-5 144-TQFP 144-TQFP 1000 hours 1000 hours 77 77 0 0 LCMXO2-1200 LCMXO2-1200 150°C 150°C 1000 hours 1000 hours 77 77 0 0 Lot #3 150°C 1000 hours 77 0 ASET Lot #1 150°C 1000 hours 77 0 256-ftBGA 256-ftBGA ASET ASET Lot #2 Lot #3 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFXP2-17 256-ftBGA ASET Lot #4A 150°C 1000 hours 77 0 LCMXO-2280 LCMXO-2280 324-ftBGA 324-ftBGA ASET ASET Lot #1 Lot #2 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LCMXO-2280 324-ftBGA ASET Lot #3 150°C 1000 hours 77 0 LCMXO2-1200 132-csBGA ASET Lot #1 150°C 1000 Hours 77 0 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA ASET ASET Lot #2 Lot #3 150°C 150°C 1000 Hours 1000 Hours 77 77 0 0 LCMXO2-7000 484-fpBGA ASET Lot #1 150°C 1000 hours 77 0 LCMXO2-7000 484-fpBGA ASET Lot #2 150°C 1000 hours 77 0 LCMXO2-7000 LFXP2-40 484-fpBGA 484-fpBGA ASET ASET Lot #3 Lot #1 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFXP2-40 LFXP2-40 484-fpBGA 484-fpBGA ASET ASET Lot #2 Lot #3 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFXP2-40 484-fpBGA ASET Lot #4A 150°C 1000 hours 77 0 LFE2M100 LFE2M100 900-fpBGA 900-fpBGA ASET ASET Lot #1 Lot #2 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFE2M100 900-fpBGA ASET Lot #3 150°C 1000 hours 77 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. Cumulative HTSL failure Rate = 0 / 2,079 Cumulative HTSL device hours = 2,079,000 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 42 Table 2.6.3 High Temperature Storage Life Data (ATP) Assembly Lot Site Number ATP Lot # 1 Stress Temperature 150°C Stress Duration 1000 hours Lot # 2 150°C 1000 hours ATP ATP Lot # 3 Lot # 4A 150°C 150°C 144-TQFP 144-TQFP ATP ATP Lot #1 Lot #2 Product Name Package LFXP2-5 144-TQFP LFXP2-5 144-TQFP ATP LFXP2-5 LFXP2-5 144-TQFP 144-TQFP LC4128 LC4128 Quantity # of Fails 77 0 77 0 1000 hours 1000 hours 77 77 0 0 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LC4128 144-TQFP ATP Lot #3 150°C 1000 hours 77 0 LCMXO2-1200 LCMXO2-1200 144-TQFP 144-TQFP ATP ATP Lot #1 Lot #2 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LCMXO2-1200 144-TQFP ATP Lot #3 150°C 1000 hours 77 0 LFXP2-17 256-ftBGA ATP Lot #1 150°C 1000 hours 77 0 LFXP2-17 LFXP2-17 256-ftBGA 256-ftBGA ATP ATP Lot #2 Lot #3 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFXP2-17 LC4512 256-ftBGA 256-ftBGA ATP ATP Lot #4A Lot #1 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LC4512 256-ftBGA ATP Lot #2 150°C 1000 hours 77 0 LC4512 LCMXO-2280 256-ftBGA 324-ftBGA ATP ATP Lot #3 Lot #1 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LCMXO-2280 LCMXO-2280 324-ftBGA 324-ftBGA ATP ATP Lot #2 Lot #3 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LCMXO2-1200 LCMXO2-1200 132-csBGA 132-csBGA ATP ATP Lot #1 Lot #2 150°C 150°C 1000 Hours 1000 Hours 77 77 0 0 LCMXO2-1200 132-csBGA ATP Lot #3 150°C 1000 Hours 77 0 LCMXO2-7000 484-fpBGA ATP Lot #1 150°C 1000 hours 77 0 LCMXO2-7000 LCMXO2-7000 484-fpBGA 484-fpBGA ATP ATP Lot #2 Lot #3 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFXP2-40 LFXP2-40 484-fpBGA 484-fpBGA ATP ATP Lot #1 Lot #2 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFXP2-40 484-fpBGA ATP Lot #3 150°C 1000 hours 77 0 #4A LFXP2-40 LFE2M100 484-fpBGA 900-fpBGA ATP ATP Lot Lot #1 150°C 150°C 1000 hours 1000 hours 77 77 0 0 LFE2M100 LFE2M100 900-fpBGA 900-fpBGA ATP ATP Lot #2 Lot #3 150°C 150°C 1000 hours 1000 hours 77 77 0 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. Cumulative HTSL failure Rate = 0 / 2,541 Cumulative HTSL device hours = 2,541,000 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 43 Table 2.6.4 High Temperature Storage Life Data (J-Devices) Product Name Package LFXP2-5 144-TQFP Assembly Lot Site Number J-Devices Lot # 1 Stress Temperature 150°C Stress Duration 1000 hours LFXP2-5 144-TQFP J-Devices Lot # 2 150°C 1000 hours LFXP2-5 LFXP2-5 144-TQFP 144-TQFP J-Devices J-Devices Lot # 3 Lot # 4A 150°C 150°C LCMXO2-1200 LCMXO2-1200 144-TQFP 144-TQFP J-Devices J-Devices Lot #1 Lot #2 LCMXO2-1200 144-TQFP J-Devices LFXP2-17 256-ftBGA LFXP2-17 LFXP2-17 Quantity # of Fails 109 0 109 0 1000 hours 1000 hours 109 109 0 0 150°C 150°C 1000 hours 1000 hours 109 108 0 0 Lot #3 150°C 1000 hours 109 0 J-Devices Lot #1 150°C 1000 hours 106 0 256-ftBGA 256-ftBGA J-Devices J-Devices Lot #2 Lot #3 150°C 150°C 1000 hours 1000 hours 107 107 0 0 LFXP2-17 256-ftBGA J-Devices Lot #4A 150°C 1000 hours 107 0 LC4512 LC4512 256-ftBGA 256-ftBGA J-Devices J-Devices Lot #1 Lot #2 150°C 150°C 1000 hours 1000 hours 90 90 0 0 LC4512 LCMXO-2280 256-ftBGA 324-ftBGA J-Devices J-Devices Lot #3 Lot #1 150°C 150°C 1000 hours 1000 hours 90 109 0 0 LCMXO-2280 324-ftBGA J-Devices Lot #2 150°C 1000 hours 109 0 LCMXO-2280 324-ftBGA J-Devices Lot #3 150°C 1000 hours 109 0 LCMXO2-1200 LCMXO2-1200 132-csBGA J-Devices 132-csBGA J-Devices Lot #1 Lot #2 150°C 150°C 1000 Hours 1000 Hours 125 125 0 0 LCMXO2-1200 132-csBGA J-Devices Lot #3 150°C 1000 Hours 125 0 A = Lot was b uilt using the worst-case wire b ond DOE parameters to ensure a rob ust process. Cumulative HTSL failure Rate = 0 / 2,161 Cumulative HTSL device hours = 2,161,000 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 44 3.0 ADDITIONAL PACKAGE FAMILY DATA Table 3.0.1 Copper (Cu) Bond Wire Bills of Material by Package Type and Assembly Site Attributes Saw-Singulated BGA TQFP Overmolded BGA ASEM / ASET / ATP / J-DEVICES ASEM / ASET / ATP / J-DEVICES ASEM / ASET / ATP ispMACH 4000ZE, LatticeECP3, LatticeXP2, MachXO and MachXO2 ispMACH 4000ZE, LatticeEC, LatticeECP, LatticeECP2, LatticeECP3, LatticeXP, LatticeXP2, MachXO and MachXO2 LatticeEC, LatticeECP, LatticeECP2M, LatticeECP3, LatticeXP, LatticeXP2, and MachXO2 65nm, 90nm, 130nm & 180nm 65nm, 90nm, 130nm & 180nm 65nm, 90nm, & 130nm ucBGA, csBGA, caBGA & ftBGA TQFP fpBGA 64/132, 56/64/100/132/144/328, 256/332 & 256/324 44, 48, 64, 100, 128 & 144 256, 388, 484, 672, 900, 1152 & 1156 Ablebond 2100A / Ablebond 2100A / Ablebond 2300 / Ablestik 84-3MV Sumitomo EME G750E / KEG-1250LKDS / GE-110 / Kyocera KE-G2250 Yizbond 8143 / CRM-1076WA / Ablebond 3230 / Sumitomo CRM1076WA Sumitomo EME G700Y / EME-G631H / G700SY / Kyocera KE-G6000 < 10 ppm / < 20 ppm < 20 ppm < 10 ppm / < 20 ppm 5 to 7 5 to 7 5 to 7 Wire Bond Material Palladium-coated Copper (PdCu) Copper (Cu) / Palladium-coated Copper (PdCu) Palladium-coated Copper (PdCu) Wire Bond Methods Thermosonic Ball Thermosonic Ball Thermosonic Ball Assembly Site Die Family (Product Line) Fabrication Process Technology Package Type Ball/Lead Counts Die Attach Material Mold Compound Supplier/ID Mold Compound Chlorine (Cl-) content Mold Compound pH level Ablebond 2100A / Ablebond 2100A / Ablebond 2300 Sumitomo EME G750SE / CEL-9750ZHF10AKL-U / GE-110 INDEX Return Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 45 4.0 REVISION HISTORY Table 4.0.1 Copper (Cu) Bond Wire Qualification Summary revisions Date May 2012 October 2012 Revision A B Section ----- June 2013 C --- July 2013 March 2014 D E October 2014 F March 2015 G Change Summary Initial document release covering PCN 09A-12 Update to include Extended Stress data Update document to include ASET second source packaging qual data and removed extended stress data (created new extended stress document) Correct typographical errors in prior data sets Update to include new subcontractor ATP Update ATP data and include new subcontractor J-Devices Corporation; add new Product Qualification Process flowchart Update Q4-14 data INDEX Return Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, Oregon 97124 U.S.A. Telephone: (503) 268-8000 www.latticesemi.com © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. w ww.latticesemi.com Lattice Semiconductor Corporation Doc. #25-106990 Rev . G 46