Page 1 May 14, 2012 Subject: Characterization Summary – Copper Bond Wire at ASEM SUMMARY Per PCN# 09A-12, Lattice is now offering alternate qualified material sets that utilize Copper bond wire (Cu-wire). This document will summarize the electrical characterization that supports that conversion. The scope of this document covers products manufactured at ASE Malaysia (ASEM). METHODOLOGY The characterization plan focused on three items: 1) Assembly Yield and Electrical Test Yield 2) Assessment of Critical Parameters 3) SSO (Simultaneous Switching Output) Characteristics 4) SERDES performance (LFE3-150EA only) Product/Package combinations were chosen to represent a cross-section of the BOM (Bill of Material) changes specified in the PCN. The product/packages and the critical BOM components are: Au-Wire (Control) Product/Pkg Cu-Wire (New) Mold Compound Wire/ Diameter Die Attach Mold Compound Wire/ Diameter Die Attach LFE3-150EA/ 1156-fpBGA Hitachi CEL9750HF10ALKU 0.9mil 2N Au Ablebond 2100A Sumitomo EME G750SE 0.8mil Pd Coated Cu Ablebond 2100A LFXP2-17E/ 256-ftBGA Hitachi CEL9750HF 0.9mil 2N Au Ablebond 2100A Sumitomo EME G750E 0.8mil Pd Coated Cu Ablebond 2100A LFXP2-5E/ 144-TQFP Hitachi CEL9510HF10-U 0.9mil 2N Au Ablebond 3230 Sumitomo EME G700Y 0.8mil Cu Yizbond 8143 Multiple lots of various product/package combinations were built as part of the qualification process for the new Cu-wire BOM. Samples from the qual lots were characterized and compared to comparable lots processed with the existing Au-wire BOM. Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 2 ASSEMBLY/ELECTRICAL TEST YIELDS The first step in the characterization process is an analysis of process yields. Yield information is critical to gauge the manufacturability of a new package. As Lattice considers yield information proprietary, the yield information below is normalized with respect to the control material, which in this case is the existing Au-wire BOM. Assembly Yield Au-wire (Control) Cu-wire Copper Lot 1 Qty= 203 Electrical Yield Au-wire (Control) 1.06 1.0 Cu-wire 1.03 1.0 Copper Lot 2 Qty= 214 1.05 1.00 LFE3-150EA 1156-fpBGA Yield Summary Assembly Yield Au-wire (Control) Cu-wire Copper Lot 1 Qty=414 Electrical Yield Au-wire (Control) 0.99 1.0 Cu-wire 0.99 1.0 Copper Lot 2 Qty= 867 1.01 1.00 LFXP2-17E 256-ftBGA Yield Summary Assembly Yield Copper Lot 1 Qty = 1682 Electrical Yield Au-wire (Control) Cu-wire Au-wire (Control) Cu-wire 1.0 0.99 1.0 1.00 LFXP2-5E 144-TQFP Yield Summary There are no discernable differences in either assembly yield or electrical final test yields between the Cu-wire and Au-wire assembly processes. Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 3 CRITICAL PARAMETERS For the purposes of this characterization, critical parameters are defined as speed, power and I/O leakage. Samples of the Cu-wire qualification lots were tested at the same time as comparative Auwire product. The tabulated statistics, Cpk values and histograms of the actual distributions are shown below. All of the critical parameters are from the device datasheet except for Tpdcounter. Tpdcounter is a Built-in Self Test (BIST) routine that is correlated to datasheet parameters. Higher counts equate to faster devices. Note that there is no significant change in the Cpk values between the various BOMs, which indicates that there is no significant parametric difference between Au-wire and Cu-wire. In most cases, the copper samples have better performance than the gold samples but the delta is small and not statistically significant. Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 4 Copper Lot #1 LFE3-150EA Copper Lot #2 1156 fpBGA Gold (Control) N 980 385 368 Mean 752.40 706.99 642.19 Icc (mA) Std Spec (max) 125.91 2693 107.23 2693 100.98 2693 Cpk 5.14 6.17 6.77 Copper Lot #1 LFXP2-17E Copper Lot #2 256 ftBGA Gold (Control) 393 394 1298 33.35 47.97 58.22 5.24 10.36 16.40 395 395 395 23.01 11.17 6.85 LFXP2-5E Copper Lot #1 144 TQFP Gold (Control) 1595 3117 34.13 50.06 7.44 13.08 172 172 6.18 3.11 Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 5 Tpdcount (counts) Std Spec (min) 597 26561 594 26561 620 26561 Copper Lot #1 LFE3-150EA Copper Lot #2 1156 fpBGA Gold (Control) N 980 385 368 Mean 33228 32904 33002 Copper Lot #1 LFXP2-17E Copper Lot #2 256 ftBGA Gold (Control) 393 394 1298 38094 41418 39024 1137 1676 1508 32000 32000 32000 1.79 1.87 1.55 LFXP2-5E Copper Lot #1 144 TQFP Gold (Control) 1595 3117 42582 43642 1363 1636 32000 32000 2.59 2.37 Lattice Semiconductor Home Page: http://www.latticesemi.com Cpk 3.72 3.56 3.46 Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 6 LFE3-150EA Copper Lot #1 1156 fpBGA Copper Lot #2 N 980 385 Mean -0.94 -0.92 IO Leakage (uA) Std Spec (max) 0.24 10 0.23 10 Cpk 15.19 15.83 Copper Lot #1 LFXP2-17E Copper Lot #2 256 ftBGA Gold (Control) 393 394 1298 -0.09 -0.1 -0.2 0.01 0.01 0.13 10 10 10 336.33 336.67 26.15 LFXP2-5E Copper Lot #1 144 TQFP Gold (Control) 1595 3117 -0.15 -0.22 0.02 0.04 10 10 169.17 85.17 Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 7 LFE3-150EA Copper Lot #1 1156 fpBGA Copper Lot #2 N 980 385 PullDown Leakage (uA) Mean Std Spec (max) 127.48 2.54 210 127.31 2.50 210 Copper Lot #1 LFXP2-17E Copper Lot #2 256 ftBGA Gold (Control) 393 394 1298 118.53 119.94 118.61 3.19 2.98 2.85 210 210 210 9.56 10.07 10.69 LFXP2-5E Copper Lot #1 144 TQFP Gold (Control) 1595 3117 121.01 120.28 2.92 2.88 210 210 10.16 10.38 Lattice Semiconductor Home Page: http://www.latticesemi.com Cpk 10.83 11.03 Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 8 SIMULTANEOUS OUTPUT SWITCHING PERFORMANCE Since the bond wire diameter is changing slightly as part of this BOM change, it is important to quantify the Simultaneous Switching Output (SSO) performance. This characteristic is also referred to as Ground Bounce, although it can affect both power and ground supply rails. Reduced bond wire diameter has the effect of increasing the inductance of the bond wire, which can affect SSO performance. Note that bond wire inductance is not a strong function of the bond wire material (Au vs. Cu). The main factor is simply the bond wire geometry (length and diameter). The following measurements are averages of 5 units per package type. All data with respect to ground. Device-Pkg LFE3-150EA 1156-fpBGA LFXP2-17E 256-ftBGA LFXP2-5E 144-TQFP Vcc # Output Switching Bondwire Diameter(mil) Material Ground Bounce Supply Bounce Overshoot Undershoot Overshoot Undershoot mV mV V V 60 0.9Au 233.4 -89.1 1.33 1.01 60 0.8Cu 230.9 -85.9 1.31 0.97 Delta -2.5 -3.2 -0.02 0.04 % Delta -1.10% -3.59% -1.68% 3.50% 1.2V 10 0.9Au 141.3 -29.0 0.67 0.42 10 0.8Cu 129.4 -31.4 0.70 0.43 Delta -11.8 2.4 0.02 -0.01 % Delta -8.38% 8.29% 3.27% -2.81% 1.2V 18 0.9Au 173.8 -80 0.95 0.41 18 0.8Cu 174.4 -84.2 0.95 0.37 Delta 0.6 4.2 -0.0052 0.04 % Delta 0.37% 5.20% -0.55% 9.03% 1.2V In the calculations above, a positive delta indicates that the Cu-wire BOM has more under or overshoot than the control Au-wire BOM. The biggest absolute change from Au-wire to Cu-wire was on the LFXP2-17E. That part had 8.38% less ground bounce with Cu-wire as compared to Au-wire. The Ground undershoot was Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 9 also 8.29% greater for Cu-wire than for Au-wire but this is the benign case where ground is going more negative. The largest adverse increase in SSO for the Cu-wire BOM was the supply undershoot of the LFXP2-5E which was 9% worse than Au-wire. This is within the calculated design tolerance of 10% and should not be an issue for a customer. SERDES PERFORMANCE Similar to SSO performance, increased inductance due to reduced wire diameter could affect high-speed operation. The LFE3-150EA was chosen as a characterization vehicle so that highspeed SERDES performance could be quantified. Three units each of Au-wire and Cu-wire were programmed with a BIST pattern that generated a PN7 pattern that was then transmitted over the SERDES channel. The eye diagrams below are at 3.125Gbps and are nearly indistinguishable. LFE3-150EA 1156fpBGA Eye diagrams (3.125Gbps) Au-Wire Cu-Wire Eye diagrams are a good qualitative measure of SERDES performance but a more quantitative approach is to compare parametric jitter measurements. Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 10 The table below compares Cu-wire and Au-wire jitter measurements at various bit rates. In all but one case, the slightly increased bond wire inductance appears to improve jitter of the Cuwire devices. Total Jitter (ps) Random Jitter (ps) Determinstic Jitter (ps) Cu-wire Units (sample of 3) 3.125Gbps 2.5Gbps 1.25Gbps 622Mbps 250Mbps 150Mbps 108.0 101.0 168.1 316.7 328.8 514.2 4.9 5.0 10.9 20.5 22.9 32.6 36.1 30.2 12.1 31.7 33.5 50.7 Total Jitter (ps) Random Jitter (ps) Determinstic Jitter (ps) Au-wire Control Units (sample of 3) 3.125Gbps 2.5Gbps 1.25Gbps 622Mbps 250Mbps 150Mbps 108.6 97.9 174.1 331.0 423.8 632.4 5.4 5.1 11.8 20.9 29.6 37.4 36.9 33.6 13.4 32.8 39.3 99.9 Total Jitter (ps) Random Jitter (ps) Determinstic Jitter (ps) Percentage Change (Red means Au was better than Cu) 1% -3% 3% 4% 22% 19% 9% 2% 8% 2% 23% 13% 2% 10% 9% 3% 15% 49% LFE3-150EA Jitter Measurements SUMMARY There are no significant electrical performance issues due to the conversion from Au-bond wire to Cu-bond wire. Lattice recommends immediate conversion to the Cu-wire material set. Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Page 11 REVISION HISTORY Date Revision Section Change Summary May 2012 1.0 --- Initial document release covering PCN 09A-12 Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation, Lattice (design), are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies.