APW8828 High-Performance Notebook PWM Controller Features General Description • Adjustable Output Voltage from +0.7V to +5.5V The APW8828 is a single-phase, constant-on-time, - 0.7V Reference Voltage synchronous PWM controller, which drives N-channel MOSFETs. The APW8828 steps down high voltage to - ±1% Accuracy Over-Temperature • generate low-voltage chipset or RAM supplies in notebook computers. Operates from an Input Battery Voltage Range of +1.8V to +28V • Power-On-Reset Monitoring on VCC Pin • Excellent Line and Load Transient Responses • PFM Mode for Increased Light Load Efficiency • Selectable PWM Frequency from 4 Preset Values • Integrated MOSFET Drivers • Integrated Bootstrap Forward P-CH MOSFET • Adjustable Integrated Soft-Start and Soft-Stop • Selectable Forced PWM or Automatic PFM/PWM The APW8828 provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. In Pulse Frequency Mode (PFM), the APW8828 provides very high efficiency over light to heavy loads with loadingmodulated switching frequencies. In PWM Mode, the converter works nearly at constant frequency for low-noise requirements. The APW8828 is equipped with accurate positive currentlimit, output under-voltage, and output over-voltage protections, perfect for NB applications. The Power-On- Mode • Power Good Monitoring • 70% Under-Voltage Protection • 125% Over-Voltage Protection • Adjustable Current-Limit Protection Reset function monitors the voltage on VCC to prevent wrong operation during power-on. The APW8828 has a 1ms digital soft-start and built-in an integrated output discharge method for soft-stop. An internal integrated soft-start ramps up the output voltage with programmable slew rate to reduce the start-up current. A soft-stop function - Using Sense Low-Side MOSFET’s RDS(ON) • Over-Temperature Protection • TDFN-10 3x3 Package actively discharges the output capacitors with controlled reverse inductor current. • Lead Free and Green Devices Available The APW8828 is available in 10pin TDFN 3x3 package. (RoHS Compliant) Simplified Application Circuit Applications • Notebook • Table PC • Hand-Held Portable • AIO PC VCC=5V EN VIN RPOK POK RRF ROCSET RF UGATE Q1 L PHASE OCSET LGATE VOUT Q2 APW8828 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 1 www.anpec.com.tw APW8828 Pin Configuration POK 1 10 BOOT OCSET 2 9 UGATE EN 3 APW8828 8 PHASE FB 4 7 VCC RF 5 6 LGATE TDFN3x3-10 Top View = GND and Thermal Pad (connected to GND plane for better heat dissipation) Ordering and Marking Information APW8828 Package Code QB : TDFN3x3-10 Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code APW8828 QB : APW 8828 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 2 www.anpec.com.tw APW8828 Absolute Maximum Ratings (Note 1) Symbol VCC VBOOT-GND VBOOT Parameter Rating Unit VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V BOOT Supply Voltage (BOOT to GND) -0.3 ~ 35 V BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 7 V -0.3 ~ VCC+0.3 V <400ns Pulse Width >400ns Pulse Width -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 V <400ns Pulse Width >400ns Pulse Width -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 V <400ns Pulse Width >400ns Pulse Width -5 ~ 35 -1 ~ 28 V All Other Pins (POK, OCSET, EN, FB, and RF to GND) UGATE Voltage (UGATE to PHASE) LGATE Voltage (LGATE to GND) PHASE Voltage (PHASE to GND) VPHASE TJ Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Soldering Temperature, 10 Seconds 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics Symbol θJA Parameter Typical Value Thermal Resistance-Junction to Ambient (Note2) 3mmx3mm TDFN-10 55 Unit °C/W Note 2: θJA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Recommended Operating Conditions (Note 3) Symbol Range Unit Converter Input Voltage 1.8 ~ 28 V VCC VCC Supply Voltage 4.5 ~ 5.5 V VOUT Converter Output Voltage 0.7 ~ 5.5 V IOUT Converter Output Current ~ 25 VIN Parameter A TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o C C Note 3: Refer to the typical application circuit. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 3 www.anpec.com.tw APW8828 Electrical Characteristics These specifications apply for TA=-40°C to +85°C, unless otherwise stated. All typical specifications TA=+25°C, VCC=5V. Symbol Parameter APW8828 Test Conditions Min. Unit Typ. Max. 0.7 - 5.5 V - 0.7 - V -0.5 - +0.5 % TA = 0 C ~ 85 C -0.8 - +0.8 % TA = -40 oC ~ 85 oC -1.0 - +1.0 % VOUT AND VFB VOLTAGE VOUT Output Voltage VREF Reference Voltage Adjustable output range TA = 25 oC Regulation Accuracy o o IFB FB Input Bias Current FB = 0.7V - 0.02 0.1 µA TDIS VOUT Discharge Time EN low to FB = 0V - 12 - ms SUPPLY CURRENT IVCC VCC Input Bias Current VCC Current, PWM, EN = 5V, VFB = 0.735V, PHASE = 0.5V - 250 520 µA IVCC_SHDN VCC Shutdown Current EN = GND, VCC = 5V - 0 1.0 µA 266 290 314 312 340 368 349 380 411 395 430 465 SWITCHING FREQUENCY AND SUTY AND INTERNAL SOFT-START FSW TON(MIN) TOFF(MIN) TSS Switching Frequency RRF = 470kΩ, TA = 25oC, VIN=8V, VOUT=1.1V, IOUT=10A RRF = 200kΩ, TA = 25oC, VIN=8V, VOUT=1.1V, IOUT=10A RRF = 100kΩ, TA = 25oC, VIN=8V, VOUT=1.1V, IOUT=10A RRF = 39kΩ, TA = 25oC, VIN=8V, VOUT=1.1V, IOUT=10A Minimum On Time kHz 80 110 140 ns Minimum Off Time VFB = 0.65V, VPHASE = -0.1V, OCSET = OPEN 350 450 550 ns Internal Soft-Start Time EN High to VOUT Regulation (95%) 0.7 1.0 1.3 ms GATE DRIVER UGATE Pull-Up Resistance BOOT-UGATE = 0.5V - 1.5 3 Ω UGATE Sink Resistance UGATE-PHASE = 0.5V - 0.7 1.8 Ω LGATE Pull-Up Resistance PVCC-LGATE = 0.5V - 1.0 2.2 Ω LGATE Sink Resistance LGATE-GND = 0.5V - 0.5 1.2 Ω UGATE to LGATE Dead-Time UGATE falling to LGATE rising - 20 - ns LGATE to UGATE Dead-Time LGATE falling to UGATE rising - 20 - ns BOOTSTRAP SWITCH VF Ron VVCC - VBOOT-GND, IF = 10mA - 0.5 0.8 V IR Reverse Leakage VBOOT-GND = 30V, VPHASE = 25V, VVCC = 5V - - 0.5 µA 4.2 4.35 4.45 V - 100 - mV 1.8 - - V - - 0.5 V VCC POR THRESHOLD VVCC_THR Rising VSS POR Threshold VCC POR Hysteresis CONTROL INPUTS EN Voltage Threshold Enable Shutdown Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 4 www.anpec.com.tw APW8828 Electrical Characteristics (Cont.) These specifications apply for TA=-40°C to +85°C, unless otherwise stated. All typical specifications TA=+25°C, VCC=5V. Symbol Parameter APW8828 Test Conditions Unit Min. Typ. Max. - 0.1 1.0 µA 1.8 - - V - - 0.5 V 87 90 93 % CONTROL INPUTS (CONT.) EN Leakage RF Setting Threshold EN = 0V Forced PWM Mode PFM/PWM Auto Skip Mode POWER-OK INDICATOR POK in from Lower (POK Goes High) VPOK IPOK POK Threshold POK Low Hysteresis (POK Goes Low) - 3 - % POK out from Normal (POK Goes Low) 120 125 130 % - 0.1 1.0 µA POK Leakage Current VPOK = 5V POK Sink Current VPOK = 0.5V 2.5 7.5 - mA POK Enable Delay Time EN High to POK High 1.4 2.0 2.6 ms CURRENT SENSE IOCSET OCP Threshold IOCSET Sourcing 9 10 11 µA TCIOCSET IOCSET Temperature Coefficient On The Basis of 25°C - 4500 - ppm/oC VROCSET Current-Limit Threshold Setting Range VOCSET-GND Voltage, Over All Temperature 0.24 - 1.6 V Over Current-Limit Comparator Offset (VOCSET-GND-VGND-PHASE) Voltage, VOCSET-GND=60mV -10 0 10 mV Zero Crossing Comparator Offset VGND-PHASE Voltage, EN=3.3V -9.5 0.5 10.5 mV UVP Threshold 60 70 80 % UVP Hysteresis - 3 - % UVP Debounce Interval - 16 - µs 1.4 2 2.6 ms 120 125 130 % - 1.5 - µs - 140 - o C - o C IOCSET PROTECTION VUV UVP Enable Delay VOVR OVP Rising Threshold OVP Propagation Delay TOTR EN High to UVP Workable VFB Rising, DV=10mV OTP Rising Threshold (Note 4) OTP Hysteresis (Note 4) - 25 Note 4: Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 5 www.anpec.com.tw APW8828 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. Enable Before End of Soft-Stop Enable at Zero Initial Voltage of VOUT ILOAD=5A No Load 1 1 2 2 3 3 CH1: VEN, 5V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: VPOK, 5V/Div, DC TIME: 500µs/Div CH1: VEN, 5V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: VPOK, 5V/Div, DC TIME: 500µs/Div Shutdown with Soft-Stop at No Load VOUT=1.1V, Load Transient 1A->18A->1A 1 1 2 2 3 3 4 CH1: VEN, 5V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: VLGATE, 5V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 5ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 CH1: VOUT, 50mV/Div, AC CH2: IL, 10A/Div, DC CH3: IOUT, 10A/Div, DC TIME: 100µs/Div 6 www.anpec.com.tw APW8828 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. Short Circuit Test Under-Voltage Protection Short Circuit Test In PFM Mode 1 1 2 2 3 3 4 4 CH1: VOUT, 1V/Div, DC CH2: VUGATE, 20V/Div, DC CH3: VLGATE, 5V/Div, DC CH4: IL, 20A/Div, DC TIME: 20µs/Div CH1: VOUT, 1V/Div, DC CH2: VUGATE, 20V/Div, DC CH3: VLGATE, 5V/Div, DC CH4: IL, 20A/Div, DC TIME: 20µs/Div Power On in Short Circuit Over-Voltage Protection 1 1 2 2 3 3 4 4 CH1: VOUT, 1V/Div, DC CH2: VUGATE, 20V/Div, DC CH3: VLGATE, 5V/Div, DC CH4: IL, 20A/Div, DC TIME: 1ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 CH1: VOUT, 1V/Div, DC CH2: VUGATE, 20V/Div, DC CH3: VLGATE, 5V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 50µs/Div 7 www.anpec.com.tw APW8828 Pin Description PIN FUNCTION NO. NAME TDFN3x3 TDFN2x2 1 1 POK Power Good Output. POK is an open drain output used to indicate the status of the output voltage. Connect the POK in to +5V through a pull-high resistor. 2 2 OCSET Current-Limit Threshold Setting Pin. There is an internal source current 10µA through a resistor from OCSET pin to GND. This pin is used to monitor the voltage drop across the Drain and Source of the low-side MOSFET for current-limit. 3 3 EN Enable Pin of The PWM Controller. When the EN is above enable logic level, the Device is workable. When the EN is below shutdown logic level, the device is in shutdown and only low leakage current is taken from VCC and VIN. 4 4 FB Output Voltage Feedback Pin. This pin is connected to the resistive divider that set the desired output voltage. The POK, UVP, and OVP circuits detect this signal to report output voltage status. 5 - RF This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor RRF to set switching frequency as show in Table1. The pin also controls forced PWM mode or PFM/PWM auto skip mode selection. When RF pin is pulled down to GND, the device is in automatic PFM/PWM Mode. When RF pin is pulled high to POK, the device is in force PWM mode. 6 6 LGATE Output of The Low-side MOSFET Driver. Connect this pin to Gate of the low-side MOSFET. Swings from GND to VCC. 7 7 VCC Supply Voltage Input Pin for Control Circuitry. Connect +5V from the VCC pin to the GND pin. Decoupling at least 1µF of a MLCC capacitor from the VCC pin to the GND pin. 8 8 PHASE Junction Point of The High-side MOSFET Source, Output Filter Inductor and The Low-side MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the UGATE high-side gate driver. 9 9 UGATE Output of The High-side MOSFET Driver. Connect this pin to Gate of the high-side MOSFET. 10 10 BOOT Supply Input for The UGATE Gate Driver and An Internal Level-shift Circuit. Connect to an external capacitor to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. Exposed Pad 5 GND Signal Ground for The IC Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 8 www.anpec.com.tw APW8828 Block Diagram POK PHASE GND 125% VREF Mean Value Circuit Current Limit Delay 10µA 90% VREF UV 70% VREF FB Frequency Adjustable OV Fault Latch Logic BOOT UGATE Thermal Shutdown On-Time Generator Digital Soft-Start/Soft-Stop VCC VCC EN ZC Error Comparator VREF POR PHASE Force PWM or Automatic PFM/PWM Selection/ Frequency Setting Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 PWM Signal Controller 125% VREF OCSET x 1/8 PHASE PVCC LGATE RF 9 www.anpec.com.tw APW8828 Typical Application Circuit VPOK POK Q1 APM4350 UGATE RPOK 100kΩ BOOT PHASE +5V OCSET LGATE CIN2 10µF LOUT 0.47µH ROCSET 1.1V/18A VOUT COUT1 COUT2 330µF 330µF 100kΩ,5% APW8828 RVCC 2.2 CBOOT 0.1µF CIN1 10µF VIN 19V Q2 APM4354 VCC CVCC 1µF GND RRF 470kΩ RF GND FB RGND 10kΩ,1% EN Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 RTOP 5.6kΩ,1% 10 www.anpec.com.tw APW8828 Function Description Constant-On-Time PWM Controller with Input Feed-For- Where FSW is the nominal switching frequency of the con- ward verter in PWM mode. The load current at handoff from PFM to PWM mode is The constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This architec- given by: 1 VIN − VOUT × × TON-PFM 2 L V − VOUT 1 V = IN × x OUT 2L FSW VIN ture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resistor, so ILOAD(PFM to PWM) = the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time controlled Forced-PWM Mode by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input volt- The RF pin should be pulled high to POK and the converter is in forced-PWM operation mode. The Forced-PWM age and directly proportional to output voltage. In PWM operation, the high-side switch on-time is determined by mode disables the zero-crossing comparator, which truncates the low-side switch on-time at the inductor current a switching frequency control circuit in the on-time generator block. zero crossing. This causes the low-side gate-drive waveform to become the complement of the high-side gate- The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulat- drive waveform. This in turn causes the inductor current to reverse at light loads while UGATE maintains a duty ing it at a constant frequency in PWM mode. The design improves the frequency variation and is more outstand- factor of VOUT/VIN. The benefit of Forced-PWM mode is to keep the switching frequency fairly constant. The Forced- ing than a conventional constant-on-time controller, which has large switching frequency variation over input voltage, output current, and temperature. Both in PFM and PWM, PWM mode is the most useful for reducing audio frequency noise, improving load-transient response, and the on-time generator, which senses input voltage on PHASE pin, provides very fast on-time response to input providing sink-current capability for dynamic output voltage adjustment. line transients. Another one-shot sets a minimum off-time (450ns, Power-On-Reset typical). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The POR function continually monitors the bias supply volt- current-limit threshold, and the minimum off-time oneshot has timed out. age on the VCC pin if at least one of the enable pins is set high. When the rising VCC voltage reaches the rising Pulse-Frequency Modulation (PFM) When VRF is below the RF low threshold (0.5V, maximum), VCC POR Threshold (4.35V, typical), the POR signal goes high and the chip initiates soft-start operations. There is the converter is in automatic PFM/PWM operation mode. In PFM mode, an automatic switchover to pulse-frequency almost no hysteresis to POR voltage threshold (about 100mV typical). When VCC voltage drops lower than modulation (PFM) takes place at light loads. This switchover is affected by a comparator that truncates the 4.25V (typical), the POR disables the chip. low-side switch on-time at the inductor current zero crossing. This mechanism causes the threshold between EN Pin Control PFM and PWM operation to coincide with the boundary between continuous and discontinuous inductor-current the converter is enabled. When VEN is below the EN low threshold (0.5V, typical), the chip is in the shutdown and operation (also known as the critical conduction point). The on-time of PFM is given by: only low leakage current is taken from VCC. TON-PFM = When VEN is above the EN high threshold (1.8V, typical), V 1 × OUT FSW VIN Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 11 www.anpec.com.tw APW8828 Function Description (Cont.) Digital Soft-Start Power OK Indicator The APW8828 integrates digital soft-start circuits to ramp up the output voltage of the converter to the programmed The APW8828 features an open-drain POK pin to indicate output regulation status. In normal operation, when the output voltage rises 90% of its target value, the POK regulation setpoint at a predictable slew rate. The slew rate of output voltage is internally controlled to limit the goes high after 63us internal delay. When the output voltage outruns 70% or 125% of the target voltage, POK sig- inrush current through the output capacitors during softstart process. The figure 1 shows soft-start sequence. nal will be pulled low immediately. Since the FB pin is used for both feedback and monitor- When the EN pin is pulled above the rising EN threshold voltage, the device initiates a soft-start process to ramp ing purposes, the output voltage deviation can be coupled directly to the FB pin by the capacitor in parallel with the up the output voltage. The soft-start interval is 1ms (typical) and independent of the UGATE switching frequency. voltage divider as shown in the typical applications. In order to prevent false POK from dropping, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. 2ms Under-Voltage Protection (UVP) VCC 1ms In the operational process, if a short-circuit occurs, the output voltage will drop quickly. When load current is big- VOUT ger than current-limit threshold value, the output voltage will fall out of the required regulation range. The under- EN voltage protection circuit continually monitors the FB voltage after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the undervoltage threshold, the under-voltage threshold is 70% of the nominal output voltage, the internal UVP delay counter starts to count. After 16µs debounce time, the device turns VPGOOD off both high-side and low-side MOSEFET with latched and starts a soft-stop process to shut down the output Figure 1. Soft-Start Sequence gradually. Toggling enable pin to low or recycling VCC, will clear the latch and bring the chip back to operation. During soft-start stage before the PGOOD pin is ready, the under-voltage protection is prohibited. The over-volt- Over-Voltage Protection (OVP) age and current-limit protection functions are enabled. If the output capacitor has residue voltage before start-up, The over-voltage function monitors the output voltage by both low-side and high-side MOSFETs are in off-state until the internal digital soft-start voltage equals to the VFB FB pin. When the FB voltage increases over 125% of the reference voltage due to the high-side MOSFET failure or voltage. This will ensure that the output voltage starts from its existing voltage level. for other reasons, the over-voltage protection comparator designed with a 1.5µs noise filter will force the low- In the event of under-voltage, over-temperature, or shutdown, the chip enables the soft-stop function. The side MOSFET gate driver fully turn on and latch high. This action actively pulls down the output voltage. soft-stop function discharges the output voltage to the GND. The duration of the discharge time is 8ms. This OVP scheme only clamps the voltage overshoot and does not invert the output voltage when otherwise activated with a continuously high output from low-side Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 12 www.anpec.com.tw APW8828 Function Description (Cont.) Over-Voltage Protection (OVP) (Cont.) MOSFET driver. It’s a common problem for OVP schemes Where R OCSET is the resistor of current-limit setting threshold. RDS(ON) is the low side MOSFETs conducive with a latch. Once an over-voltage fault condition is set, it can only be reset by toggling EN, VCC power-on-reset resistance. ILIMIT is the setting current-limit threshold. ILIMIT can be expressed as IOUT minus half of peak-to-peak in- signal. ductor current. The PCB layout guidelines should ensure that noise and DC errors do not corrupt the current-sense signals at PHASE. Place the hottest power MOSEFTs as close to Current-Limit The current-limit circuit employs a “valley” current-sens- the IC as possible for best thermal coupling. When combined with the under-voltage protection circuit, this cur- ing algorithm (See Figure 2). The APW8828 uses the low-side MOSFET’s RDS(ON) of the synchronous rectifier rent-limit method is effective in almost every circumstance. as a current-sensing element. If the magnitude of the current-sense signal at PHASE pin is above the current- Over-Temperature Protection (OTP) limit threshold, the PWM is not allowed to initiate a new cycle. The actual peak current is greater than the current- When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the over- limit threshold by an amount equals to the inductor ripple current. Therefore, the exact current-limit characteristic temperature protection state that suspends the PWM, which forces the UGATE and LGATE gate drivers output and maximum load capability are the functions of the sense resistance, inductor value, and input voltage. low. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 25oC. The OTP is designed with a 25oC hysteresis to lower the average TJ INDUCTOR CURRENT, IL IPEAK IOUT during continuous thermal overload conditions, which increases lifetime of the APW8828. ∆I Programming the On-Time Control and PWM Switch- ILIMIT ing Frequency 0 The APW8828 does not use a clock signal to produce PWM. The device uses the constant-on-time control ar- Time Figure 2. Current-Limit Algorithm chitecture to produce pseudo-fixed frequency with input voltage feed-forward. The on-time pulse width is propor- The PWM controller uses the low-side MOSFETs on-resistance R DS(ON) to monitor the current for protection tional to output voltage VOUT and inverses proportional to input voltage VIN. The switching frequency is selectable against shortened outputs. The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user from four preset values by a resistor connected to RF pin as shown in Table1. should determine the maximum RDS(ON) in manufacture’s datasheet. APW8828 doesn’t have VIN pin to calculate on-time pulse width. Therefore, monitoring VPHASE voltage as input volt- The OCSET pin can source 10µA through an external resistor for adjusting current-limit threshold. The voltage age to calculate on-time when the high-side MOSFET is turned on. And then, use the relationship between ontime at OCSET pin is equal to 10µA x ROCSET. The relationship between the sampled voltage VOCSET and the current-limit and duty cycle to obtain the switching frequency. threshold ILIMIT is given by: 1 × 10 µ A × R OCSET = ILIMIT × R DS ( ON ) 8 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 13 www.anpec.com.tw APW8828 Function Description (Cont.) Programming the On-Time Control and PWM Switching Frequency (Cont.) Table 1. Resistance RRF (kΩ) Switching Frequency FSW (kHz) 470 290 200 340 100 380 39 430 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 14 www.anpec.com.tw APW8828 Application Information Output Voltage Setting saturation. In some types of inductors, especially core The output voltage is adjustable from 0.7V to 5.5V with a that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output resistor-divider connected with FB, GND, and converter’s output. Using 1% or better resistors for the resistor-di- ripple voltage. Besides, the inductor needs to have low DCR to reduce the loss of efficiency. vider is recommended. The output voltage is determined by: R TOP V OUT = 0.7 × 1 + R GND Output Capacitor Selection Output voltage ripple and the transient voltage deviation are factors which have to be taken into consideration when selecting an output capacitor. Higher capaci- Where 0.7 is the reference voltage, RTOP is the resistor connected from converter’s output to FB, and RGND is the tor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high per- resistor connected from FB to GND. Suggested RGND is in the range from 1k to 20kΩ. To prevent stray pickup, locate formance low ESR capacitors is recommended for switching regulator applications. In addition to high resistors RTOP and RGND close to APW8828. frequency noise related to MOSFET turn-on and turnoff, the output voltage ripple includes the capacitance Output Inductor Selection The duty cycle (D) of a buck converter is the function of the voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused by the AC peak-to-peak inductor’s current. These two input voltage and output voltage. Once an output voltage is fixed, it can be written as: voltages can be represented by: V D = OUT VIN The inductor value (L) determines the inductor ripple IRIPPLE 8COUTFSW = IRIPPLE × RESR ∆VCOUT = ∆VESR current, IRIPPLE, and affects the load transient reponse. Higher inductor value reduces the inductor’s ripple cur- These two components constitute a large portion of the rent and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capaci- VIN - VOUT VOUT × FSW × L VIN Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (F SW ) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into IRIPPLE = Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 tors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor (1µF) in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load step change. Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the capacitor from over-heating. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, selecting the capacitor voltage rating to be at least 1.3 times 15 www.anpec.com.tw APW8828 Application Information (Cont.) 2 Input Capacitor Selection (Cont.) Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW higher than the maximum input voltage. The maximum Plow-side = IOUT (1+ TC)(RDS(ON))(1-D) Where 2 RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power-up, the input I is the load current OUT TC is the temperature dependency of RDS(ON) capacitors have to handle great amount of surge current. For low-duty notebook appliactions, ceramic capacitor is FSW is the switching frequency tSW is the switching interval recommended. The capacitors must be connected between the drain of high-side MOSFET and the source of D is the duty cycle Note that both MOSFETs have conduction losses while low-side MOSFET with very low-impeadance PCB layout. the high-side MOSFET includes an additional transition loss. The switching interval, tSW , is the function of the reverse MOSFET Selection transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should be used. The design has to trade off the gate charge with extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET. the RDS(ON) of the MOSFET: For the low-side MOSFET, before it is turned on, the body Layout Consideration diode has been conducting. The low-side MOSFET driver will not charge the miller capacitor of this MOSFET. In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. In the turning off process of the low-side MOSFET, the load current will shift to the body diode first. The high dv/ With power devices switching at higher frequency, the resulting current transient will cause voltage spike across dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver sinking current the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the path. This results in much less switching loss of the lowside MOSFETs. The duty cycle is often very small in high MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling battery voltage applications, and the low-side MOSFET will conduct most of the switching cycle; therefore, when by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike using smaller RDS(ON) of the low-side MOSFET, the converter can reduce power loss. The gate charge for this during the switching interval. In general, using short and wide printed circuit traces should minimize interconnect- MOSFET is usually the secondary consideration. The high-side MOSFET does not have this zero voltage switch- ing impedances and the magnitude of voltage spike. Besides, signal and power grounds are to be kept sepa- ing condition; in addition, because it conducts for less time compared to the low-side MOSFET, the switching rating and finally combined using ground plane construction or single point grounding. The best tie-point between loss tends to be dominant. Priority should be given to the MOSFETs with less gate charge, so that both the gate the signal ground and the power ground is at the negative side of the output capacitor on each channel, where driver loss and switching loss will be minimized. The selection of the N-channel power MOSFETs are there is less noise. Noisy traces beneath the IC are not recommended. Below is a checklist for your layout: determined by the R DS(ON), reversing transfer capacitance (CRSS) and maximum output current requirement. • Keep the switching nodes (UGATE, LGATE, BOOT, The losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as and low-side MOSFETs, the losses are approximately given by the following equations: possible and there should be no other weak signal traces in parallel with theses traces on any layer. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 16 www.anpec.com.tw APW8828 Application Information (Cont.) Layout Consideration (Cont.) • The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short and wide. • Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the MOSFETs (VIN and PHASE nodes) can • get better heat sinking. The GND is the current sensing circuit reference ground and also the power ground of the LGATE lowside MOSFET. On the other hand, the GND trace should be a separate trace and independently go to the source of the low-side MOSFET. Besides, the current sense resistor should be close to OCSET pin to avoid parasitic capacitor effect and noise coupling. • Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.) • The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capacitor’s ground should be close to the grounds of the output capacitors and low-side MOSFET. • Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces can’t be close to the switching signal traces (UGATE, LGATE, BOOT, and PHASE). Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 17 www.anpec.com.tw APW8828 Package Information TDFN3x3-10 D E A b Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e TDFN3x3-10 S Y M B O L A MIN. MAX. MIN. MAX. 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 INCHES MILLIMETERS A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 2.70 0.087 0.106 D2 2.20 E 2.90 3.10 0.114 0.122 E2 1.40 1.75 0.055 0.069 0.50 0.012 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.020 0.008 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 18 www.anpec.com.tw APW8828 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN3x3-10 A H T1 C d D 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 W E1 12.0±0.30 1.75±0.10 F 5.5±0.05 (mm) Devices Per Unit Package Type TDFN3x3-10 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 Quantity 3000 19 www.anpec.com.tw APW8828 Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 20 www.anpec.com.tw APW8828 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 21 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8828 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2011 22 www.anpec.com.tw