APW8868 DDR2 AND DDR3 SYNCHRONOUS BUCK CONTROLLER WITH 1.5A LDO SUPPORT LOW IQ & DROOP Features General Description Buck Controller (VDDQ) • • The APW8868 integrates a synchronous buck PWM con- High Input Voltages Range from 3V to 28V Input Power troller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT. It offers the lowest total Provide Adjustable Output Voltage from 0.75V to solution cost in system where space is at a premium. 5.5V +1% Accuracy over Temperature • The APW8868 provides excellent transient response and Integrated MOSFET Drivers and Bootstrap Forward accurate DC voltage output in either PFM or PWM Mode. In Pulse Frequency Mode (PFM), the APW8868 provides P-CH MOSFET • Low Quiescent Current (200µA) • Excellent Line and Load Transient Responses • PFM Mode for Increased Light Load Efficiency • Constant On-Time Controller Scheme very high efficiency over light to heavy loads with loadingmodulated switching frequencies. On TQFN-20 Package, the Forced PWM Mode works nearly at constant frequency for low-noise requirements. - Switching Frequency Compensation for PWM The APW8868 is equipped with accurate current-limit, output under-voltage, and output over-voltage protections. Mode - Adjustable Switching Frequency from 100kHz to A Power-On- Reset function monitors the voltage on VCC prevents wrong operation during power on. Droop func- 550kHz in PWM Mode with DC Output Current • S3 and S5 Pins Control The Device in S0, S3 or S4/ tion is allowed to adjust output voltage during light load period. S5 State • Power Good Monitoring • Extra Droop Voltage Control Function with • 70% Under-Voltage Protection (UVP) • The device integrates two power transistors to source or sink current up to 1.5A. It also incorporates current-limit 125% Over-Voltage Protection (OVP) and thermal shutdown protection. • Adjustable Current-Limit Protection The LDO is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination. Adjustable Current Setting The output voltage of LDO tracks the voltage at VREF pin. - Using Sense Low-Side MOSFET’s RDS(ON) • TQFN-20 3mmx3mm Thin package • Lead Free Available (RoHS Compliant) An internal resistor divider is used to provide a half voltage of VREF for VTTREF and VTT Voltage. The VTT output voltage is only requiring 20µF of ceramic output capacitance for stability and fast transient response. The S3 +1.5A LDO Section (VTT) • Sourcing or Sinking Current up to 1.5A • Fast Transient Response for Output Voltage • Output Ceramic Capacitors Support at least 10µF and S5 pins provide the sleep state for VTT (S3 state) and suspend state (S4/S5 state) for device, when S5 and S3 are both pulled low the device provides the soft-off for VTT and VTTREF. MLCC • VTT and VTTREF Track at Half the VDDQSNS by internal divider • +20mV Accuracy for VTT and VTTREF • Independent Over-Current Limit (OCL) • Thermal Shutdown Protection ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 1 www.anpec.com.tw APW8868 Simplified Application Circuit 5V RCS VIN +3V~28V VCC Q1 VDDQ Applications CS • DDR2, and DDR3 Memory Power Supplies • SSTL-2 SSTL-18 and HSTL Termination DROOP LOUT OFFSET PWM Q2 DDR LDO S3 VTT VDDQ/2 S5 Ordering and Marking Information APW8868 Package Code QB : TQFN3x3-20 Operating Ambient Temperature Range I : -40 to 85 °C Handling Code TR : Tape & Reel Lead Free Code G : Halogen and Lead Free Device Lead Free Code Handling Code Temperature Range Package Code APW8868 QB : APW 8868 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). PHASE BOOT UGATE LDOIN VTT Pin Configuration 20 19 18 17 16 15 LGATE VTTGND 1 VTTSNS 2 14 PGND 21 PGND DROOP 3 13 CS VTTREF 4 12 VCC VDDQSNS 5 9 10 PGOOD S3 8 TON 7 S5 6 VFB 11 OFFSET = Thermal Pad (connected to GND plane for better heat dissipation) Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 2 www.anpec.com.tw APW8868 Absolute Maximum Ratings (Note 1,2) Symbol VCC VBOOT VBOOT-GND Parameter Rating Unit VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 7 V BOOT Supply Voltage (BOOT to GND) -0.3 ~ 35 V -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 V -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 V -5 ~ 35 -0.3 ~ 28 V -0.3 ~ 0.3 V -0.3 ~ 7 V UGATE Voltage (UGATE to PHASE) <400ns pulse width >400ns pulse width LGATE Voltage (LGATE to GND) <400ns pulse width >400ns pulse width PHASE Voltage (PHASE to GND) <400ns pulse width >400ns pulse width PGND, VTTGND and CS_GND to GND Voltage All Other Pins (CS, OFFSET, DROOP, S3, S5, VTTSNS, VDDQSNS, VLDOIN, VFB, PGOOD, VTT, VTTREF GND) Tj Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Soldering Temperature, 10 Seconds 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2: The device is ESD sensitive. Handling precautions are recommended. Thermal Characteristics (Note 3) Symbol Parameter Typical Value θJA Thermal Resistance -Junction to Ambient 50 θJC Thermal Resistance -Junction to Case 8 Unit °C/W °C/W Note 3: θJA and θJCare measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 3 www.anpec.com.tw APW8868 Recommended Operating Conditions (Note 4) Symbol Parameter VCC VCC Supply Voltage VIN Converter Input Voltage VVDDQ Converter Output Voltage Range Unit 4.5 ~ 5.5 V 3 ~ 28 V 0.75 ~5.5V V 0.375 ~ 2.75 V 0 ~ 15 A -1.5 ~ +1.5 A 1~ µF VVTT LDO Output Voltage IOUT Converter Output Current IVTT LDO Output Current CVCC VCC Capacitance CVTT VTT Output Capacitance 10~100 µF VTTREF Output Capacitance 0.01~0.1 µF Ambient Temperature -40 ~ 85 o -40 ~ 125 o CVTTREF TA TJ Junction Temperature C C Note 4: Refer to the typical application circuit. Electrical Characteristics Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless otherwise specified. Typical values are at TA=25oC. Symbol Parameter APW8868 Test Conditions Unit Min Typ Max SUPPLY CURRENT VCC Supply Current TA = 25oC, VS3 = VS5 = 5V, no load, VCC Current - 180 200 µA IVCCSTB VCC Standby Current TA = 25oC, VS3 = 0V, VS5 = 5V, no load, VCC Current - 120 140 µA IVCCSDN VCC Shutdown Current TA =25oC, VS3 = VS5 = 0V, no load - 0.1 1 µA ILDOIN LDOIN Supply Current TA = 25oC, VS3 = VS5 = 5V, no load - 1 10 TA = 25oC, VS3 = 0V, VS5 = 5V, no load, - 0.1 10 - 0.1 1 4.15 4.3 4.45 V - 0.1 - V VLDOIN = VVDDQSNS = 1.8V - 0.9 - VLDOIN = VVDDQSNS = 1.5V - 0.75 - -20 - 20 -30 - 30 -20 - 20 -30 - 30 IVCC ILDOINSTB LDOIN Standby Current ILDOINSDN LDOIN Shutdown Current o TA = 25 C, VS3 = VS5 = 0V, no load µA POWER-ON-RESET VCC POR Threshold VCC Rising VCC POR Hysteresis VTT OUTPUT VVTT VTT Output Voltage VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT, IVTT = 0A VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT, VVTT VTT Output Tolerance IVTT = 1.5A mV VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT, IVTT = 0A VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT, IVTT = 1.5A Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 V 4 www.anpec.com.tw APW8868 Electrical Characteristics Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless otherwise specified. Typical values are at TA=25oC. Symbol Parameter APW8868 Test Conditions Unit Min Typ Max TJ=25oC 1.8 2 3 o TJ=125 C 1.6 - - TJ=25oC -2 -2.2 -3 TJ=125oC -1.6 - - TJ=25 C 1.6 1.8 2.6 TJ=125oC 1.1 - - TJ=25 C -1.6 -1.8 -2.6 TJ=125oC -1.1 - - Upper MOSFET - 350 500 Lower MOSFET - 350 500 -1.0 - 1.0 µA -1.00 0.01 1.00 µA 15 25 35 mA VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - 0.9 - VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - 0.75 - -18 - +18 VTT OUTPUT Sourcing Current (VIN=1.8V) Sinking Current (VIN=1.8V) ILIM Current-Limit o Sourcing Current (VIN=1.5V) o Sinking Current (VIN=1.5V) RDS(ON) IVTTLK VTT Power MOSFETs RDS(ON) VTT Leakage Current IVTTSNSLK VTTSNS Leakage Current VVTT = 1.25V, VS3 = 0V, VS5 = 5V, TA = 25oC VVTT = 1.25V, TA = 25oC A A mΩ o IVTTDIS VTT Discharge Current VVTT = 0.5V, VS3 = VS5 = 0V, TA = 25 C VVREF = 0V VTTREF OUTPUT VVTTREF VTTREF Output Voltage -10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF VTTREF Tolerance VLDOIN = VVTTREF =1.8V -10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF VLDOIN = VVDDQSNS = 1.5V V mV -20 - 20 IVTTREF VTTREF Source Current VVTTREF = 0V -10 -20 -40 mA IVTTREF VTTREF Sink Current VVTTREF = 1.8V 10 20 40 mA 0.745 0.75 0.755 V 0.7425 0.75 0.7575 V TA = 25 C, VVCC = 4.5V to 5.5V, VIN = 3V to 28V -0.1 - +0.1 % TA = 25 oC, Load = 0 to 10A, VVCC = 4.5V to 5.5V -1 - +1 % -0.1 - +0.1 µA VDDQ OUTPUT TA = 25 oC o o TA = -40 C to 85 C VVFB VFB Regulation Voltage o VFB Input Current VVFB= 0.78V VDDQ Discharge Current VS3 = VS5 = 0V, VVDDQSNS = 0.5V, 15 25 - mA IDROOP DROOP Input Current - 5 - µA IOFFSET OFFSET Input Current - 5 - µA Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 5 www.anpec.com.tw APW8868 Electrical Characteristics Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless otherwise specified. Typical values are at TA=25oC. Symbol Parameter APW8868 Test Conditions Unit Min Typ Max PWM CONTROLLERS FSW Operating Frequency Adjustable Frequency 100 - 550 KHz TSS Internal Soft Start Time S5 is High to VOUT Regulation 0.9 1.2 1.5 ms VIN =19V, VVDDQ=1.5V, RTON =1.2M 235 276 320 ns - 300 - ns 80 110 140 ns -9.5 0.5 10.5 mV 4 5 6 µA - 4500 - ppm/ o C -10 0 +10 mV VDDQ Current Limit Setting Range VVCC-VCS 30 - 200 mV VDDQ OVP Trip Threshold 120 125 130 % PWM CONTROLLERS TO Fast on time TOFF(MIN) Minimum off time TON(MIN) Slow on time Zero-Crossing Threshold VDDQ PROTECTIONS TA = 25 oC CS Pin Sink Current Temperature Coefficient, On The Basis of 25°C OCP Comparator Offset (VVCC – VCS) – (VPHASE – PGND), VVCC – VCS = 60mV VVDDQ Rising - 1.5 - µs 60 70 80 % - 3 - % - 10 - µs - 2 - ms PGOOD in from Lower (PGOOD Goes High) 87 90 93 % PGOOD in from Higher (PGOOD Goes High) 120 125 130 % PGOOD High Hysteresis (PGOOD Goes Low) - 3 - % PGOOD Leakage Current VPGOOD=5V - 0.1 1.0 µA PGOOD Sink Current VPGOOD=0.5V 2.5 7.5 - mA - 63 - µs VDDQ OVP Debounce Delay VFB Rising, DV=10mV VDDQ UVP Trip Threshold VVDDQ Falling VDDQ UVP Trip Hysteresis VDDQ UVP Debounce (TI : 32Cycles) VDDQ UVP Enable Delay PGOOD VPGOOD IPGOOD PGOOD Threshold PGOOD Debounce Time GATE DRIVERS UGATE Pull-Up Resistance BOOT-UGATE=0.5V - 5 7 Ω UGATE Sink Resistance UGATE-PHASE=0.5V - 1 2.5 Ω LGATE Pull-Up Resistance PVCC-LGATE=0.5V - 5 7 Ω LGATE Sink Resistance LGATE-PGND=0.5V - 1 2.5 Ω UGATE to LGATE Dead time UGATE falling to LGATE rising, no load - 20 - ns LGATE to UGATE Dead time LGATE falling to UGATE rising, no load - 20 - ns Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 6 www.anpec.com.tw APW8868 Electrical Characteristics Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless otherwise specified. Typical values are at TA=25oC. Symbol Parameter APW8868 Test Conditions Unit Min Typ Max - 0.1 0.2 V - - 0.5 µA 1.6 - - V BOOTSTRAP DIODE Forward Voltage Reverse Leakage VVCC – VBOOT, IF = 10mA, TA = 25 oC o VBOOT = 30V, VPHASE = 25V, VVCC=5V, TA = 25 C LOGIC THRESHOLD VIH S3, S5 High Threshold Voltage S3, S5 Rising VIL S3, S5 Low Threshold Voltage S3, S5 Falling - - 0.3 V IILEAK Logic Input Leakage Current VS3 = VS5 = 5V, TA =25oC -1 - 1 µA TJ Rising - 160 - o - 25 - o THERMAL SHUTDOWN TSD Thermal Shutdown Temperature Thermal Shutdown Hysteresis Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 7 C C www.anpec.com.tw APW8868 Pin Description NO. NAME 1 VTTGND Power ground output for the VTT LDO. 2 VTTSNS Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor. 3 DROOP DROOP voltage is allowed to lower VREF and VDDQ output voltage during light load period. 4 VTTREF 5 FUNCTION VTTREF buffered reference output. VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current VDDQSNS sinking terminal for VDDQ non-tracking discharge. 6 VFB VDDQ output voltage setting pin. 7 S3 S3 signal input. 8 S5 S5 signal input. 9 TON 10 PGOOD 11 OFFSET 12 VCC 13 CS 14 PGND 15 LGATE 16 PHASE 17 UGATE 18 BOOT 19 LDOIN 20 VTT This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor RTON = 100KΩ ~ 1.2MΩ from TON pin to PHASE pin. Power-good output pin. PGOOD is an open drain output used to Indicate the status of the output voltage. When VDDQ output voltage is within the target range, it is in high state. OFFSET pin is set the low power mode current threshold and trigger DROOP current after 6 times zero-crossing. 5V power supply voltage input pin for both internal control circuitry and low-side MOSFET gate driver. Over-current trip voltage setting input for RDS(ON) current sense scheme if connected to GND through the voltage setting resistor. Power ground of the LGATE low-side MOSFET driver. Connect the pin to the Source of the low-side MOSFET. Output of the low-side MOSFET driver for PWM. Connect this pin to Gate of the low-side MOSFET. Swings from PGND to VCC. Junction point of the high-side MOSFET Source, output filter inductor and the low-side MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the UGATE high-side gate driver. Output of the high-side MOSFET driver for PWM. Connect this pin to Gate of the high-side MOSFET. Supply Input for the UGATE Gate Driver and an internal level-shift circuit. Connect to an external capacitor and diode to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. Supply voltage input for the VTT LDO. Power output for the VTT LDO. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 8 www.anpec.com.tw APW8868 Block Diagram 0.5 x VDDQ VDDQSNS VTTREF VLDOIN Thermal Shutdown S3 Current Limit S3,S5 Control Logic VTT S5 0.5 x VDDQ +5/10% VTTSNS 0.5 x VDDQ 5/10% VTTGND 5uA OFFSET Non-Tracking Discharge COUNTER ZC PHASE LGATE 5uA VCC Soft Start DROOP POR VCC 1.25V VREF DROOP 0.75V Current Limit CS VREF VFB 5uA 125% x VREF OV Error Comparator BOOT UGATE UV TON PWM Signal Controller 70% x VREF PHASE TON Generator PHASE VCC ZC LGATE VREF x 125%/122% PGOOD PGND Delay VREF x 90%/87% Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 9 www.anpec.com.tw APW8868 Typical Application Circuit CBOOT VIN 7V~25V CIN 0.1uF Q1 LOUT 1uH PHASE VDDQ 10uF x 2 VTT VDDQ/2 VDDQ 10A COUT 22uF x 4 (MLCC) PHASE UGATE BOOT CVTT 10uF x 2 LDOIN VTT Q2 LGATE VTTGND PGND VTTSNS RDROOP RCS APW8868 DROOP TQFN3x3-20 VTTREF VDDQ/2 VCC CS RVCC 5.1K, 1% VCC VTTREF 2.2 ROFFSET OFFSET CVCC 1uF PGOOD TON S5 S3 VDDQSNS VFB CVTTREF 0.033uF CPVCC 4.7uF RPGOOD PGOOD RTON VDDQ RTOP 75K, 1% 100k VIN or PHASE RGND 75K, 1% Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 1.2M 10 www.anpec.com.tw APW8868 Function Description The APW8868 integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO Both in PFM and PWM, the on-time generator, which senses input voltage on PHASE pin, provides very fast on-time response to input line transients. linear regulator to generate VTT. It provides a complete power supply for DDR2 and DDR3 memory system in a Another one-shot sets a minimum off-time (typical: 300ns). The on-time one-shot is triggered if the error com- 20-pin TQFN package. User defined output voltage is also possible and can be adjustable from 0.75V to 5.5V. parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- Input voltage range of the PWM converter is 3V to 28V. The converter runs an adaptive on-time PWM operation shot has timed out. Power-On-Reset at high-load condition and automatically reduces frequency to keep excellent efficiency down to several mA. A Power-On-Reset (POR) function is designed to prevent The VTT LDO can source and sink up to 1.5A peak current with only 10µF ceramic output capacitor. VTTREF wrong logic controls when the VCC voltage is low. The POR function continually monitors the bias supply volt- tracks VDDQ/2 within 1% of VDDQ. VTT output tracks VTTREF within 20 mV at no load condition while 40 mV at age on the VCC pin if at least one of the enable pins is set high. When the rising VCC voltage reaches the rising full load. The LDO input can be separated from VDDQ and optionally connected to a lower voltage by using POR voltage threshold (4.3V typical), the POR signal goes high and the chip initiates soft-start operations. Should VLDOIN pin. This helps reducing power dissipation in sourcing phase. The APW8868 is fully compatible to this voltage drop lower than 4.2V (typical), the POR disables the chip. JEDEC DDR2/DDR3 specifications at S3/S5 sleep state (see Table 1). When both VTT and VDDQ are disabled, Soft- Start the non-tracking discharge mode discharges outputs using internal discharge MOSFETs that are connected to The APW8868 integrates digital soft-start circuits to ramp up the output voltage of the converter to the programmed VDDQSNS and VTT. regulation set point at a predictable slew rate. The slew rate of output voltage is internally controlled to limit the inrush current through the output capacitors during soft- Constant-On-Time PWM Controller with Input Feed-Forward start process. The figure 1 shows VDDQ soft-start sequence. When the S5 pin is pulled above the rising S5 The constant on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This ar- threshold voltage, the device initiates a soft-start process to ramp up the output voltage. The soft-start interval is 1. chitecture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resistor, 2ms (typical) and independent of the UGATE switching frequency. so the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time controlled by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input 2ms VCC and VPVCC voltage and directly proportional to output voltage. In PWM operation, the high-side switch on-time is determined by 1.2ms VOUT a switching frequency control circuit in the on-time generator block. The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulating it at a constant frequency in PWM S5 mode. The design improves the frequency variation and be more outstanding than a conventional constant ontime controller which has large switching frequency variation over input voltage, output current and temperature. VPGOOD Fig1. Soft-Start Sequence Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 11 www.anpec.com.tw APW8868 Function Description (cont.) Soft- Start (cont.) Over Voltage Protection (OVP) During soft-start stage before the PGOOD pin is ready, The feedback voltage should increase over 125% of the the under voltage protection is prohibited. The over voltage and current limit protection functions are enabled. If reference voltage due to the high-side MOSFET failure or for other reasons, and the over voltage protection com- the output capacitor has residue voltage before startup, both low-side and high-side MOSFETs are in off-state parator designed with a 1.5µs noise filter will force the low-side MOSFET gate driver to be high. This action ac- until the internal digital soft start voltage equal the internal feedback voltage. This will ensure the output voltage tively pulls down the output voltage and eventually attempts to blow the battery fuse. starts from its existing voltage level. The VTT LDO part monitors the output current, both sourc- When the OVP occurs, the PGOOD pin will pull down and latch-off the converter. This OVP scheme only clamps the ing and sinking current, and limits the maximum output current to prevent damages during current overload or voltage overshoot, and does not invert the output voltage when otherwise activated with a continuously high output short circuit (shorted from VTT to GND or VLDOIN) conditions. from low-side MOSFET driver. It’s a common problem for OVP schemes with a latch. Once an over-voltage fault The VTT LDO provides a soft-start function, using the constant current to charge the output capacitor that gives condition is set, toggling VCC power-on-reset signal can only reset it. a rapid and linear output voltage rise. If the load current is above the current limit start-up, the VTT cannot start PWM Converter Current Limit successfully. APW8868 has an independent counter for each output, The current-limit circuit employs a unique “valley” current sensing algorithm (Figure 2). CS pin should be con- but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT power good externally. nected to VCC through the trip voltage-setting resistor, RCS. CS terminal sinks 5mA current, ICS, and the current limit threshold is set to the voltage across the RCS. The voltage between or CS_GND pin and PHASE pin moni- Power-Good Output (PGOOD) PGOOD is an open-drain output and the PGOOD comparator continuously monitors the output voltage. PGOOD tors the inductor current so that PHASE pin should be connected to the drain terminal of the low side MOSFET. is actively held low in shutdown, and standby. When PWM converter’s output voltage is greater than 95% of its tar- PGND is used as the positive current sensing node so that PGND should be connected to the proper current get value, the internal open-drain device will be pulled low. After 63µs debounce time, the PGOOD goes high. sensing device, i.e. the sense resistor or the source terminal of the low side MOSFET. The PGOOD goes low if VVDDQ output is 10% below or above its nominal regulation point. If the magnitude of the current-sense signal is above the current-limit threshold, the PWM is not allowed to initiate Under Voltage Protection In the process of operation, if a short-circuit occurs, the a new cycle. The actual peak current is greater than the current-limit threshold by an amount equal to the induc- output voltage will drop quickly. When load current is bigger than current limit threshold value, the output voltage tor ripple current. Therefore, the exact current- limit characteristic and maximum load capability are a function of will fall out of the required regulation range. The undervoltage continually monitors the setting output voltage the sense resistance, inductor value, and input voltage. The equation for the current limit threshold is as follows: after 2ms of PWM operations to ensure startup. If a load step is strong enough to pull the output voltage lower ILIMIT= than the under voltage threshold (70% of normal output voltage), APW8868 shuts down the output gradually and 1/10×RCS×5uA (VIN− VVDDQ) VVDDQ + × RDS(ON) 2×L×fsw VIN latches off both high and low side MOSFETs. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 12 www.anpec.com.tw APW8868 Function Description (cont.) PWM Converter Current Limit(cont.) DROOP voltage is set as same as OFFSET voltage with a source current 5µA and a resistor RDROOP. Then, VREF is Where ILIMIT is the desired current limit threshold, RCS is the value of the current sense resistor connected to CS created by minus DROOP voltage and output voltage is adjustable during user defined light load operation. Note and GND pins VCS is the voltage across the RCS resistor IRIPPLE is inductor peak to peak current FSW is the PWM that, connect OFFSET/DROOP pins to GND disables their function behavior and leave OFFSET/DROOP pins float- switching frequency. In a current limit condition, the current to the load ex- ing are forbidden. ceeds the current to the output capacitor thus the output voltage tends to fall down. If the output voltage becomes VTT Sink/Source Regulator The output voltage at VTT pin tracks the reference voltage applied at VTTREF pin. Two internal N-channel MOSFETs less than power good level, the VCS is cut into half and the output voltage tends to be even lower. Eventually, it controlled by separate high bandwidth error amplifiers regulate the output voltage by sourcing current from INDUCTOR CURRENT crosses the under voltage protection threshold and shutdown. VLDOIN pin or sinking current to GND pin. To prevent two pass transistors from shoot-through, a small voltage off- IPEAK set is created between the positive inputs of the two error amplifiers. The VTT with fast response feedback loop ILIMIT keeps tracking to the VTTREF within +40 mV at all conditions including fast load transient. IVALLEY S3, S5 Control In the DDR2/DDR3 memory applications, it is important 0 to keep VDDQ always higher than VTT/VTTREF including both start-up and shutdown. The S3 and S5 signals con- Time trol the VDDQ, VTT, VTTREF states and these pins should be connected to SLP_S3 and SLP_S5 signals Fig2. Current Limit Algorithm respectively. The table1 shows the truth table of the S3 and S5 pins. When both S3 and S5 are above the logic DROOP/OFFSET DROOP function is designed for increasing power efficiency during light load. The APW8868 enables the threshold voltage, the VDDQ, VTT and VTTREF are turned on at S0 state. When S3 is low and S5 is high, the VDDQ DROOP function to adjust output voltage while internal LPM current threshold is triggered for six times and VTTREF are kept on while the VTT voltage is disabled and left high impedance in S3 state. When both S3 continuously. A resistor (ROFFSET), connected from OFFSET to GND, programs the LPM current threshold. The and S5 are low, the VDDQ, VTT and VTTREF are turned off and discharged to the ground. OFFSET terminal sources 5µA through the ROFFSET to develop the VOFFSET Voltage. The LPM current threshold is given by : STATE S3 5µA × ROFFSET = ILPM × RDS( ON) _ LGATE While the LGATE turns on, the inductor current flows through the low side MOSFET. If the inductor current triggers the LPM current threshold six times continuously, in S5 VDDQ VTTREF VTT S0 H H 1 1 1 S3 L H 1 1 0 (high-Z) S4/5 L L 0 (discharge) 0 (discharge) 0 (discharge) Table1. The Truth Table of S3 and S5 pins. other words, once PHASE voltage and OFFSET voltage have zero-crossing six times continuously, the DROOP function is enabled. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 13 www.anpec.com.tw APW8868 Function Description (cont.) Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APW8868. When the junction temperature exceeds +160oC, PWM converter, VTTLDO and VTTREF are shut off, allowing the device to cool down. The regulator regulates the output again through initiation of a new softstart cycle after the junction temperature cools by 25oC, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown designed with a 25oC hysteresis lowers the average junction temperature during continuous thermal overload conditions, extending life time of the device. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed +125oC. Programming the On-Time Control and PWM Switching Frequency The APW8868 does not use a clock signal to produce PWM. The device uses the constant on-time control architecture to produce pseudo-fixed frequency with input voltage feed-forward. The on-time pulse width is proportional to output voltage VOUT and inverse proportional to input voltage VIN. In PWM, the on-time calculation is written as below equation. 2 × VVDDQ + 75mV − 50ns TON = 11.5 × 10 −12 × R TON × 3 VIN Where: RTON is the resistor connected from TON pin to PHASE pin. Furthermore, The approximate PWM switching frequency is written as: TON = D VOUT / VIN = FSW = FSW TON Where: FSW is the PWM switching frequency APW8868 doesn’t have VIN pin to calculate on-time pulse width. Therefore, monitoring VPHASE voltage as input voltage to calculate on-time when the high-side MOSFET is turned on. And then, use the relationship between ontime and duty cycle to obtain the switching frequency. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 14 www.anpec.com.tw APW8868 Application Information (cont.) Output Voltage Selection PWM can be also adjusted from 0.75V to 5.5V with a In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it resistor-driver at VFB between VDDQSNS and GND. Using 1% or better resistors for the resistive divider is saturates. This will be result in a larger output ripple voltage. recommended. The VFB pin is the inverter input of the error amplifier, and the reference voltage is 0.75V. Take Output Capacitor Selection the example, the output voltage of PWM is determined by: Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting an output capacitor. Higher capacitor value and R V OUT = 0.75 × 1 + TOP R GND lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low Where RTOP is the resistor connected from VOUT to VVFB and RGND is the resistor connected from VFB to GND. ESR capacitors is intended for switching regulator applications. In addition to high frequency noise related Output Inductor Selection MOSFET turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop and ESR voltage The duty cycle of a buck converter is the function of the drop caused by the AC peak-to-peak current. These two voltages can be represented by: input voltage and output voltage. Once an output voltage is fixed, it can be written as: D= ∆VCOUT = VOUT VIN The inductor value determines the inductor ripple current ∆VESR = IRIPPLE × RESR and affects the load transient response. Higher inductor value reduces the inductor’s ripple current and induces These two components constitute a large portion of the lower output ripple voltage. The ripple current and ripple voltage can be approximated by: IRIPPLE = IRIPPLE 8C OUT FSW total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired VIN − VOUT VOUT × FSW × L VIN ESR value. If the output of the converter has to support another load with high pulsating current, more capaci- Where FSW is the switching frequency of the regulator. Although increase the inductor value and frequency re- tors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A duce the ripple current and voltage, there is a tradeoff between the inductor’s ripple current and the regulator small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the load transient response time. A smaller inductor will give the regulator a faster load output capacitors must also be considered. To support a load transient that is faster than the switch- transient response at the expense of higher ripple current. Increasing the switching frequency (FSW ) also reduces ing frequency, more capacitors have to be used to reduce the voltage excursion during load step change. An- the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipa- other aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than tion of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to the rated RMS current specified on the capacitors to prevent the capacitor from over-heating. choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, selecting an inductor is capable of carrying the required peak current without going into saturation. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 15 www.anpec.com.tw APW8868 Application Information (cont.) Phigh-side = IOUT2(1+TC)(RDS(ON))D+(0.5)(IOUT)(VIN)(tSW )FSW Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times Plow-side = IOUT2(1+TC)(RDS(ON))D(1-D) higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, Where I is the load current where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. TC is the temperature dependency of RDS(ON) FSW is the switching frequency In low-duty notebook applications, ceramic capacitors are recommended. The capacitors must be connected be- tSW is the switching interval D is the duty cycle tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impedance PCB layout. Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss. The switching internal, tSW , is the function of the MOSFET Selection The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should reverse transfer capacitance CRSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET: can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. - For the low-side MOSFET, before it is turned on, the body diode has been conducted. The low-side MOSFET Layout Consideration driver will not charge the miller capacitor of this MOSFET. - In the turning off process of the low-side MOSFET, the In any high switching frequency converter, a correct layout is important to ensure proper operation of the load current will shift to the body diode first. The high dv/ dt of the phase node voltage will charge the miller ca- regulator. With power devices switching at higher frequency, the resulting current transient will cause volt- pacitor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the age spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the low-side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the low-side turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. MOSFET will conduct most of the switching cycle; therefore, the RDS(ON) of the low-side MOSFET, the less During turn-off, current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode. the power loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFET Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, does not have this zero voltage switching condition, and because it conducts for less time compared to the low- using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude of side MOSFET, the switching loss tends to be dominant. Priority should be given to the MOSFETs with less gate voltage spike. And signal and power grounds are to be kept separating and finally combined to use the ground charge, so that both the gate driver loss and switching loss will be minimized. plane construction or single point grounding. The best tie-point between the signal ground and the power ground The selection of the N-channel power MOSFETs are determined by the RDS(ON), reversing transfer capacitance is at the negative side of the output capacitor on each channel, where there is less noise. Noisy traces beneath (CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduc- the IC are not recommended. Below is a checklist for your layout: tion loss and transition loss. For the high-side and lowside MOSFETs, the losses are approximately given by the following equations: Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 16 www.anpec.com.tw APW8868 Application Information (cont.) Layout Consideration 3mm - Keep the switching nodes (UGATE, LGATE, BOOT, and PHASE) away from sensitive small signal nodes(VFB, VTTREF, and CS) since these nodes are fast moving signals. Therefore, keep traces to these nodes as short 0.5mm * as possible and there should be no other weak signal traces in parallel with theses traces on any layer. 1.66 mm 0.2mm - The signals going through theses traces have both high dv/dt and high di/dt, with high peak charging and discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short and wide. 3mm 0.4mm 1.66 mm - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimiz- 0.17mm 0.5mm ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, the resistor dividers, boot capacitors, and current limit stetting resistor should be TQFN3x3-20 close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET * Just Recommend Figure3. Recommended Minimum Footprint as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of the upper MOSFET; the high quality ceramic decoupling capacitor can be put close to the VCC and GND pins; the VTTREF decoupling capacitor should be close to the VTTREF pin and GND; the VDDQ and VTT output capacitors should be located right across their output pin as close as possible to the part to minimize parasitic. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. - The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking. And PHASE pin traces are also the return path for UGATE. Connect this pin to the converter’s upper MOSFET source. - The APW8868 used ripple mode control. Build the resistor divider close to the VFB pin so that the high impedance trace is shorter. And the VFB pin traces can’t be closed to the switching signal traces (UGATE, LGATE, BOOT, and PHASE). - The PGND trace should be a separate trace, and independently go to the source of the low-side MOSFETs for current limit accuracy. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 17 www.anpec.com.tw APW8868 Package Information TQFN3x3-20 D E b A Pin 1 A1 A3 D2 NX aaa C L K E2 Pin 1 Corner e S Y M B O L TQFN3x3-20 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.25 0.006 0.010 0.122 A3 b 0.20 REF 0.15 0.008 REF D 2.90 3.10 0.114 D2 1.50 1.80 0.059 0.071 0.122 0.071 E 2.90 3.10 0.114 E2 1.50 1.80 0.059 0.50 0.012 e 0.40 BSC L 0.30 K 0.20 0.016 BSC 0.008 0.08 aaa 0.020 0.003 Note : 1. Followed from JEDEC MO-220 WEEE Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 18 www.anpec.com.tw APW8868 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN3x3-20 A H T1 C d D W E1 F 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.00±0.20 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type TQFN3x3-20 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 Quantity 3000 19 www.anpec.com.tw APW8868 Taping Direction Information TQFN3x3-20 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 20 www.anpec.com.tw APW8868 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 21 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8868 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2013 22 www.anpec.com.tw