THCV233-THCV234_Main-Link_Rev.2.02_E THCV233 and THCV234 Main-Link V-by-One®HS High-speed video data transmitter and receiver with bi-directional transceiver Width Link 24bit Si/DDo 0°C~ 70°C 1.62V~ 1.98V 40MHz to 100MHz 9MHz to 85MHz -40°C~ 105°C 40MHz to 85MHz Si/So 9MHz to 100MHz 40MHz to 100MHz Si/So 9MHz to 75MHz 40MHz to 75MHz Si/So 9MHz to 100MHz 40MHz to 100MHz Si/So 9MHz to 81MHz 40MHz to 81MHz Si/So 9MHz to 100MHz Si/So:Single-in/Single-out, Si/Do:Single-in/Dual-out Si/DDo:Single-in/Distributed Dual-out Di/So:Dual-in/Single-out, Di/SSo:Dual-in/Selected Single-out 1.7V~ 1.98V 20MHz to 100MHz Di/So 40MHz to 100MHz Si/So 9MHz to 85MHz 20MHz to 85MHz Di/So 40MHz to 85MHz Si/So 9MHz to 95MHz 24bit Si/DDo -40°C~ 105°C 20MHz to 81MHz Si/Do 32bit Di/SSo THCV234 20MHz to 100MHz Si/Do 24bit Di/SSo 1.62V~ 1.98V 20MHz to 75MHz Si/Do 32bit Si/DDo 0°C~ 70°C 20MHz to 100MHz Si/Do 24bit Si/DDo 1.7V~ 1.98V 20MHz to 85MHz Si/Do 32bit Si/DDo LVDS Input internal termination CORE 1.8V, LVDS 3.3V Package: 48 pin QFN EU RoHS Compliant Main-Link Data width selectable: 24/32 bit Single/Dual Link selectable AC coupling Wide frequency range CDR requires no external freq. reference Supports Spread Spectrum Clocking: Up to 30kHz/0.5%(center spread) Sub-Link Concerning Sub-Link and GPIO detail specification, please refer to “THCV233-THCV234_Sub-Link”. 20MHz to 100MHz Si/So 24bit Si/DDo THCV233 LVDS Clock Freq. 9MHz to 100MHz Si/Do 32bit Si/DDo 2. Features VDL Si/So THCV233 and THCV234 are V-by-One® HS High-speed video data transmitter/receiver with bi-directional transceiver. They convey not only video data (Main-Link), but also bi-directional system control data (Sub-Link) that is driven by 2-wire serial interface. HOST CPU-side of Sub-Link is selectable on each device and the other side of Sub-Link* integrates I/O expander. THCV233-234 system is able to watch and control peripheral devices via 2-wire serial interface or GPIOs. They also can report interrupt events caused by change of GPIO inputs and internal statuses. TMP Product 1. General Description 20MHz to 95MHz Si/Do 40MHz to 95MHz Si/So 9MHz to 71.25MHz 32bit Si/DDo Si/Do 20MHz to 71.25MHz 40MHz to 71.25MHz Table 1 3.Block Diagram GPIO * 4 Controls TCMP RCMP TCMN RCMN 2-wire serial I/F LVDS Serializer Deserializer Deserializer TX1P RX1P TX1N RX1N Deskew & Formatter TX0P RX0P TX0N RX0N CDR Serializer Formatter OSC Serializer ・ ・ ・ THCV234 PLL TLA +/・ ・ ・ TLE +/TLCLK +/- LVDS Deserializer THCV233 ・ ・ ・ RLA +/・ ・ ・ RLE +/RLCLK +/- OSC Controls GPIO * 5 2-wire serial I/F Figure 1 THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 1/39 THCV233-THCV234_Main-Link_Rev.2.02_E 4. Pin Configuration THCV234 LAVDH LAGND AIN [1] AIN [0] MODE [1] MODE [0] VDD PRE IOSEL BET PDN [1] PDN [0] DGLOCK/GPIO[4] PDN[0] PDN[1] IOSEL RS VDD MODE[0] MODE[1] AIN [0] AIN [1] LAGND LAVDH THCV233 36 35 34 33 32 31 30 29 28 27 26 25 TLATLA+ TLBTLB+ TLCTLC+ TLCLKTLCLK+ TLDTLD+ TLETLE+ 37 38 39 40 41 42 43 44 45 46 47 48 THCV233 QFN-48pin Exposed PAD (TOP VIEW) 49 EXPGND 24 23 22 21 20 19 18 17 16 15 14 13 36 35 34 33 32 31 30 29 28 27 26 25 HTPDN/GPIO[1] LOCKN/GPIO[0] CAVDL CAGND TX0N TX0P CAGND TX1N TX1P CAGND CAVDL CPVDL HTPDN/GPIO[1] LOCKN/GPIO[0] CAGND RX0N RX0P CAVDL CAGND RX1N RX1P CAGND CAVDL BET 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 THCV234 QFN-48pin Exposed PAD (TOP VIEW) 49 EXPGND 24 23 22 21 20 19 18 17 16 15 14 13 RLARLA+ RLBRLB+ RLCRLC+ RLCLKRLCLK+ RLDRLD+ RLERLE+ Figure 2 LAVDH LAGND COL ALNOUT/GPIO[3] INT/GPIO[2] VSS VDD SDA SCL RCMP RCMN MSSEL MSSEL TCMN TCMP SCL SDA VDD VSS INT/GPIO[2] ALNIN/GPIO[3] COL LAGND LAVDH 1 2 3 4 5 6 7 8 9 10 11 12 THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 2/39 THCV233-THCV234_Main-Link_Rev.2.02_E 5. Pin Description Table 2 THCV233 Pin Description Pin Name TLA -/+ TLB -/+ TLC -/+ TLCLK -/+ TLD -/+ TLE -/+ TX0N/P TX1N/P 37,38 39,40 41,42 43,44 45,46 47,48 20,19 17,16 Type* LI LI LI LVDS signal input. LI LI LI CO High-speed CML signal output (Main-Link). CO LOCKN/GPIO[0] 23 BO Lock detect input (LOCKN) or GPIO[0]. When IOSEL=L, used as LOCKN, it must be connected to Rx LOCKN with a Tx side 10kΩ pull-up resistor. LOCKN is input only. When IOSEL=H without any register setting, used as GPIO[0] input, no external component is required. When IOSEL=H and used as GPIO[0] output, it must be connected with a pull-up resistor to 3.3V as an open-drain output pin. HTPDN/GPIO[1] 24 BO Hot plug detect input (HTPDN) or GPIO[1]. When IOSEL=L, used as HTPDN, it must be connected to Rx HTPDN with a Tx side 10kΩ pull-up resistor. HTPDN is input only. When IOSEL=H without any register setting, used as GPIO[1] input, no external component is required. When IOSEL=H and used as GPIO[1] output, it must be connected with a pull-up resistor to 3.3V as an open-drain output pin. TCMN/P 11,10 CB CML bi-directional input/output (Sub-Link). When PDN[1]=L, Sub-Link power down, it can be left open. B Interrupt signal output for Sub-Link (INT) or GPIO[2]. When MSSEL=L, used as INT output, it must be connected with a pull-up resistor to 3.3V. INT can monitor changes of GPIO input pins and internal statuses and reports event set by register (default : no monitor). H : Steady state, L : Interrupt occured When MSSEL=H without any register setting, used as GPIO[2] input, no external component is required. When used as GPIO[2] open-drain output, it must be connected with a pull-up resistor to 3.3V. When used as GPIO[2] input or push pull output, no external component is required. INT/GPIO[2] Pin # 5 Description ALNIN/GPIO[3] 4 B Data alignment enable input for LVDS data sets (ALNIN) or GPIO[3]. ALNIN is default without any register setting. ALNIN is external DE input pin. When input LVDS does not contain DE signal, DE can be provided as external input. Activation of ALNIN function follow the following settings. When PDN[1:0]=LH, Main-Link Only Active,SCL pin is worked as "choice of DE input" selector; therefore, SCL=L activates ALNIN. H : DE input from LVDS is used for processing, L : DE input from ALNIN is used for processing When PDN[1:0]=HH, Main-Link and Sub-Link active,register setting determines whether ALNIN is activated and its polarity. When used as ALNIN, no external component is required. ALNIN is input only. When used as GPIO[3] open-drain output, it must be connected with a pull-up resistor to 3.3V. When used as GPIO[3] input or push pull output, no external component is required. SDA 8 BO Data Schmitt input/output for 2-wire serial interface. When PDN[1]=H, Sub-Link active, it must be connected with a pull-up resistor to 3.3V. When PDN[1:0]=LH, Main-Link Only Active, it must be connected with a pull-up resistor to 3.3V. SCL 9 BO Clock Schmitt input/output for 2-wire serial interface. When PDN[1]=H, Sub-Link active, it must be connected with a pull-up resistor to 3.3V. When PDN[1:0]=LH, Main-Link Only Active, SCL pin is worked as "choise of DE input" selector. H : DE input from LVDS is used for processing, L : DE input from ALNIN is used for processing *Type symbol I=3.3V CMOS input, B= CMOS Bi-directional buffer, BO= OpenDrain CMOS Bi-directional buffer LI=LVDS input, CO=CML output, CB=CML Bi-directional buffer P33=Power 3.3V, P18=Power 1.8V, GND=GND Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 3/39 THCV233-THCV234_Main-Link_Rev.2.02_E THCV233 Pin Description (Continued) Pin Name MSSEL AIN [1:0] Pin # 12 34,33 Type* Description I Master-side/Slave-side selector for Sub-Link and 2-wire serial interface. H : Sub-Link Slave side (inside 2-wire serial I/F is master), L : Sub-Link Master side (inside 2-wire serial I/F is slave) Sub-Link Master is connected to HOST MPU. Forbid the same setting between THCV233 and THCV234. I Address setting for 2-wire serial interface. When using 2-wire serial interface, it must be set the same value as THCV234's one. AIN[1:0] =LL : 7'b0001011 =LH : 7'b0110100 =HL : 7'b1110111 =HH : Reserved (Forbidden) MODE [1:0] 32,31 I Operation mode select input for Main-Link. MODE[1:0] =LL : Single-in/Distribution dual-out =LH : Single-in/Single-out =HL : Single-in/Dual-out =HH : Reserved (Forbidden) IOSEL 28 I HTPDN, LOCKN pin enable input for Main-Link. H : HTPDN, LOCKN pin disable (GPIO[1:0] enable), L : HTPDN, LOCKN pin enable (GPIO[1:0] disable) When IOSEL inputs H, HTPDN and LOCKN state in THCV234 are brought by Sub-Link. PDN [1:0] 26,25 I Power down Schmitt input. PDN[1]: For Sub-Link power down control (2-wire serial interface + Sub-Link) H: Normal operation, L: Power down PDN[0]: For Main-Link power down control (LVDS-Rx + Main-Link) H: Normal operation, L: Power down PRE 29 I Pre-Emphasis level select input for Main-Link. H : 100%, L : 0% COL 3 I Data width setting for Main-Link. H : 24bit, L : 32bit BET 27 I LAVDH LAGND CAVDL CAGND CPVDL VDD VSS EXPGND 1,36 2,35 22,14 21,18,15 13 7,30 6 49 P33 GND P18 GND P18 P18 GND GND Field-BET entry. H : Field BET Operation, L : Normal Operation LVDS power supply (3.3V) LVDS GND High-speed signal analog power supply (1.8V) High-speed signal analog GND High-speed signal PLL power supply (1.8V) Logic power supply (1.8V) Logic GND EXPOSED PAD GND *Type symbol I=3.3V CMOS input, B= CMOS Bi-directional buffer, BO= OpenDrain CMOS Bi-directional buffer LI=LVDS input, CO=CML output, CB=CML Bi-directional buffer P33=Power 3.3V, P18=Power 1.8V, GND=GND Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 4/39 THCV233-THCV234_Main-Link_Rev.2.02_E Table 3 THCV234 Pin Description Pin Name Pin # RLA -/+ RLB -/+ RLC -/+ RLCLK -/+ RLD -/+ RLE -/+ RX0N/P RX1N/P 24,23 22,21 20,19 18,17 16,15 14,13 40,41 44,45 Type* LO LO LO LVDS signal output. LO LO LO CI High-speed CML signal input (Main-Link). CI Description LOCKN/GPIO[0] 38 BO Lock detect output (LOCKN) or GPIO[0]. When IOSEL=L, used as LOCKN, it must be connected to Tx LOCKN with a Tx side10kΩ pull-up resistor. LOCKN is output only. When IOSEL=H without any register setting, used as GPIO[0] input, no external component is required. When IOSEL=H and used as GPIO[0] output, it must be connected with a pull-up resistor to 3.3V as an open-drain output pin. HTPDN/GPIO[1] 37 BO Hot plug detect output (HTPDN) or GPIO[1]. When IOSEL=L, used as HTPDN, it must be connected to Tx HTPDN with a Tx side 10kΩ pull-up resistor. HTPDN is output only. When IOSEL=H without any register setting, used as GPIO[1] input, no external component is required. When IOSEL=H and used as GPIO[1] output, it must be connected with a pull-up resistor to 3.3V as an open-drain output pin. RCMN/P 2,3 CB CML bi-directional input/output (Sub-Link). When PDN[1]=L, Sub-Link power down, it can be left open. B Interrupt signal output for Sub-Link (INT) or GPIO[2]. When MSSEL=L, used as INT output, it must be connected with a pull-up resistor to 3.3V. INT can monitor changes of GPIO input pins and internal statuses and reports event set by register (default : no monitor). H : Steady state, L : Interrupt occured When MSSEL=H without any register setting, used as GPIO[2] input, no external component is required. When used as GPIO[2] open-drain output, it must be connected with a pull-up resistor to 3.3V. When used as GPIO[2] input or push pull output, no external component is required. B Data alignment enable output (ALNOUT) for LVDS data sets or GPIO[3]. ALNOUT is default without any register setting. When used as ALNOUT, no external component is required. It is push pull output. ALNOUT output DE timing depending upon data stream state. ALNOUT is output only. When used as GPIO[3] open-drain output, it must be connected with a pull-up resistor to 3.3V. When used as GPIO[3] input or push pull output, no external component is required. Bit Error Test (BET) result output under Field-BET operation H : No error, L : Bit error occured INT/GPIO[2] ALNOUT/GPIO[3] 8 9 DGLOCK/GPIO[4] 36 BPU Multiple-chip configuration total Rx side LOCKN indicator (DGLOCK) or GPIO[4]. DGLOCK is default without any register setting. When used as DGLOCK, it is internally connected with a pull-up resistor to 3.3V. No external component is required. LOCKN arrange among Rx Multiple-chip configuration is achieved by connecting all DGLOCK pins. When used as GPIO[4] output, which is open-drain output only. It must be connected with a pull-up resistor to 3.3V. When used as GPIO[4] input, no external component is required. SDA 5 BO Data Schmitt input/output for 2-wire serial interface. When PDN[1]=H, Sub-Link active, it must be connected with a pull-up resistor to 3.3V. When PDN[1]=L, Sub-Link power down, it can be directly connected to GND. SCL 4 BO Clock Schmitt input/output for 2-wire serial interface. When PDN[1]=H, Sub-Link active, it must be connected with a pull-up resistor to 3.3V. When PDN[1]=L, Sub-Link power down, it can be directly connected to GND. *Type symbol I=3.3V CMOS input, B= CMOS Bi-directional buffer, BO= OpenDrain CMOS Bi-directional buffer BPU =CMOS Bi-directional buffer with an on-chip pullup resistor LO=LVDS output, CO=CML output, CB=CML Bi-directional buffer P33=Power 3.3V, P18=Power 1.8V, GND=GND Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 5/39 THCV233-THCV234_Main-Link_Rev.2.02_E THCV234 Pin Description (Continued) Pin Name MSSEL AIN [1:0] Pin # 1 27,28 Type* I I MODE [1:0] 29,30 I IOSEL 33 I Description Master-side/Slave-side selector for Sub-Link and 2-wire serial interface. H : Sub-Link Slave side (inside 2-wire serial I/F is master), L : Sub-Link Master side (inside 2-wire serial I/F is slave) Sub-Link Master is connected to HOST MPU. Forbid the same setting between THCV233 and THCV234. Address setting for 2-wire serial interface. When used 2-wire serial interface, it must be set the same value as THCV233's one. AIN[1:0] =LL : 7'b0001011 =LH : 7'b0110100 =HL : 7'b1110111 =HH : Reserved (Forbidden) Operation mode select input for Main-Link. MODE [1:0] =LL : Dual-in/Selected single-out (Lane0) =LH : Dual-in/Single-out =HL : Dual-in/Selected single-out (Lane1) =HH : Single-in/Single-out HTPDN, LOCKN pin enable output for Main-Link. H : HTPDN, LOCKN pin disable (GPIO[1:0] enable), L : HTPDN, LOCKN pin enable (GPIO[1:0] disable) When IOSEL inputs H, HTPDN and LOCKN state in THCV234 are brought by Sub-Link. Power down Schmitt input. PDN[1]: For Sub-Link power down control (2-wire serial interface + Sub-Link) H: Normal operation, L: Power down PDN[0]: For Main-Link power down control (LVDS-Rx + Main-Link) H: Normal operation, L: Power down PDN [1:0] 34,35 I RS 32 I LVDS output swing range select input. H : Normal swing (350mv@typ.), L : Reduced swing (200mv@typ.) Latch select input under Field-BET operation H : Latched result, L : NOT Latched result COL 10 I Data width setting for Main-Link. H : 24bit, L : 32bit BET 48 I LAVDH LAGND CAVDL CAGND VDD VSS EXPGND 12,25 11,26 42,47 39,43,46 6,31 7 49 P33 GND P18 GND P18 GND GND Field-BET entry. H : Field BET Operation, L : Normal Operation LVDS power supply (3.3V) LVDS GND High-speed signal analog power supply (1.8V) High-speed signal analog GND Logic power supply (1.8V) Logic GND Exposed PAD GND *Type symbol I=3.3V CMOS input, B= CMOS Bi-directional buffer, BO= OpenDrain CMOS Bi-directional buffer BPU =CMOS Bi-directional buffer with an on-chip pullup resistor LO=LVDS output, CO=CML output, CB=CML Bi-directional buffer P33=Power 3.3V, P18=Power 1.8V, GND=GND Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 6/39 THCV233-THCV234_Main-Link_Rev.2.02_E 6. General Operation Mode Table 4 Operation Mode Schematic Diagram of Operation THCV233 THCV234 Main-Link Data Input Main-Link(V-by-One® HS compliant) Main-Link Block Main-Link Block Clock Input Clock Output LOCKN/HTPDN Sub-Link Block Sub-Link Block THCV233 THCV234 Main-Link Data Input Main-Link & Data Output Main-Link Block Main-Link Block Data Output Clock Output Clock Input Sub-Link(with up to 8 GPIO port) Sub-Link Block Sub-Link Block Sub-Link THCV233 THCV234 Main-Link Block Main-Link Block Sub-Link(with up to 8 GPIO port) Sub-Link Block Sub-Link Block Sub-Link Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 7/39 THCV233-THCV234_Main-Link_Rev.2.02_E 7. Main-Link Operation Mode Table 5 THCV233 THCV234 Single-In/Single-Out Single-In/Single-Out 3.4G 3.4G 32bit 32bit @85MHz @85MHz LVDS LVDS MODE[1:0]=HH MODE[1:0]=LH Single-In/Dual-Out Dual-In/Single-Out 1.7G 32bit 1.7G 32bit @85MHz @85MHz LVDS LVDS 1.7G 1.7G MODE[1:0]=HL MODE[1:0]=LH Single-In/Single-Out * 2 Dual-In/Selected Single-Out 3.4G 32bit 3.4G @85MHz 32bit LVDS @85MHz 3.4G 32bit 3.4G LVDS @85MHz LVDS MODE[1:0]=LH MODE[1:0]=LL / HL Single-In/Distributed Dual-Out Single-In/Single-Out * 2 3.4G 3.4G 32bit @85MHz 32bit LVDS @85MHz 3.4G 3.4G LVDS 32bit @85MHz LVDS MODE[1:0]=LL MODE[1:0]=HH THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 8/39 THCV233-THCV234_Main-Link_Rev.2.02_E 8. Function Description Functional Overview With High Speed CML SerDes, proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV233 and THCV234 enable transmission of 24/32bit video data, 2bit control data and Data Enable (DE) through Main-Link by single/dual differential pair cable with minimal external components. In addition, THCV233 and THCV234 has Sub-Link which enables bi-directional transmission of 2-wire interface signals, GPIO signals and also HTPDN/LOCKN signals for Main-Link through the other 1-pair of CML-Line. It does not need any external frequency reference, such as a crystal oscillator. THCV233, transmitter of Main-Link, inputs LVDS data (including video data, control data and DE) and serializes video data and control data separately, depending on polarity of DE. DE is a signal which indicates whether video or control data are active. When DE is high, it serializes video data inputs into CML data streams. And it transmits serialized control data when DE is low. Instead of DE in the LVDS format, THCV233 has ALNIN LVCMOS-input pin, which enables to transfer LVDS input data with external DE input via ALNIN. THCV234, receiver of Main-Link, automatically extracts clock from the incoming data streams and converts high-speed serial data into video data with DE being high or control data with DE being low, recognizing which type of serial data is being sent by transmitter. And it outputs the recovered data in the form of LVDS data. THCV234 has ALNOUT output pin which transmits DE signal in LVCMOS. THCV234 can seamlessly operate for a wide range of a serial bit rate from 270Mbps to 3.4Gbps/lane. Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 9/39 THCV233-THCV234_Main-Link_Rev.2.02_E Data Enable Requirement (DE) There are some requirements for DE signal as described in Figure 3, Figure 4 Figure 14 and Table 31. If DE=Low, control data of same cycle and particular assigned data bit ‘CTL’ except the first and the last pixel are transmitted. Otherwise video data are transmitted during DE=High. Control data from receiver in DE=High period are previous data of DE transition. See Figure 4. The length of DE being low and high is at least 2 clock cycles long, as described in Figure 14 and Table 31. Data Enable must be toggled like High -> Low -> High at regular interval. THCV233 THCV234 DE=H R/G/B,CONT DE=L, CTL* except the 1st and the last pixel other R/G/B,CONT=Low Fixed Data bit : R/G/B, CONT R/G/B, CONT, CTL H DE=H, V,HSYNC=Fixed DE=L, V,HSYNC Control bit : V,HSYNC Data bit : CTL* V, HSYNC L DE DE *CTL are particular assigned bit among R/G/B, CONT that can carry arbitrary data during DE=Low period. Figure 3 Conceptual diagram of the basic operation of the chipset DE input via LVDS THCV233 input DE=High Active period Data : Low fixed H, V : Keep the last data of blanking period DE=Low Blanking period Data : Particular assigned bit ‘CTL’ is transmitted except the first and the last pixel of Blanking period. / Others are Low fixed. TLn +/n=A,B,D,E 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 TLC +/- D E V H 3 2 1 0 D E V H 3 2 1 0 D E V H 3 2 1 0 D E V H 3 2 1 0 D E V H 3 2 1 0 D E V H 3 2 1 0 TLCLK +/Indefinite region RLn +/n=A,B,D,E 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 RLC +/- H V H 3 2 1 0 L V H 3 2 1 0 L V H 3 2 1 0 L V H 3 2 1 0 H V H 3 2 1 0 H V H 3 2 1 0 THCV234 output RLCLK +/- ALNOUT (CMOS) tRALN tRALN Typ;5tTCIP/7 Typ;5tTCIP/7 Indefinite region Indefinite region ±3/7tTCIP ±3/7tTCIP Figure 4 Data bit and control bit transmission when DE is from LVDS (default) THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 10/39 THCV233-THCV234_Main-Link_Rev.2.02_E Data alignment indicator input of THCV233 (ALNIN) ALNIN is external DE input. When input LVDS does not contain DE signal, DE can be provided via ALNIN. Activation setting of ALNIN function is described in the following “Data Enable Select of THCV233”. Data alignment indicator output of THCV234 (ALNOUT) ALNOUT output DE timing depending upon data stream state. Data Enable Select of THCV233 Depending on pin or register setting THCV233 can deal with several DE alternatives. When PDN[1:0]=LH, SCL pin is worked as "choice of DE input" selector. H : DE input from LVDS is used for processing, L : DE input from ALNIN is used for processing When PDN[1:0]=HH, register setting determines the following. Default “From LVDS, normal polarity, TLC[6]” See register mapping. When DE input bit is from TLC[5] or TLC[4], operation follows Figure 4. Whether DE input from LVDS or from ALNIN is used for processing DE input polarity Whether DE input from LVDS used for processing is TLC[6] or TLC[5] or TLC[4] Figure 5 indicate ALNIN operation. User must take care of data indefinite region and had better ignore them. DE input via ALNIN THCV233 input DE=High Active period Data : Low fixed H, V : Keep the last data of blanking period DE=Low Blanking period Data : Particular assigned bit ‘CTL’ is transmitted except the first and the last pixel of Blanking period. / Others are Low fixed. X Ignored TLn +/n=A,B,D,E 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 TLC +/- X V H 3 2 1 0 X V H 3 2 1 0 X V H 3 2 1 0 X V H 3 2 1 0 X V H 3 2 1 0 X V H 3 2 1 0 TLCLK +/tTALN tTALN ALNIN (CMOS) Indefinite region THCV234 output Indefinite region RLn +/n=A,B,D,E 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 RLC +/- H V H 3 2 1 0 L V H 3 2 1 0 L V H 3 2 1 0 L V H 3 2 1 0 H V H 3 2 1 0 H V H 3 2 1 0 RLCLK +/tRALN ALNOUT (CMOS) tRALN Typ;5tTCIP/7 Typ;5tTCIP/7 ±3/7tTCIP ±3/7tTCIP Figure 5 Data bit and control bit transmission when DE is from ALNIN THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 11/39 THCV233-THCV234_Main-Link_Rev.2.02_E HTPDN, LOCKN transmission route setting (IOSEL) IOSEL determine the HTPDN/LOCKN signal transmission route. If HTPDN and LOCKN are transmitted by Sub-Link, remained pins become GPIO. Table 6 HTPDN/LOCKN Transmission Route Setting IOSEL HTPDN/LOCKN L HTPDN/LOCKN are transmitted via external DC signal. HTPDN/LOCKN are transmitted via Sub-Link. H Remained pins become GPIO, driven via 2-wire serial. Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. Power Down (PDN[1:0]) PDN[1:0] turn off internal circuitry of Main-Link and Sub-Link separately. Table 7 Power Down Setting PDN[1:0] Operation LL Both Main-Link and Sub-Link power down LH Only Main-Link is active HL Only Sub-Link is active HH Both Main-Link and Sub-Link active Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. Color depth or data width setting function for Main-Link (COL) COL pin enables to select data width for Main-Link. E-ch. (TLE-/+ and RLE-/+) is disable with COL=H. Table 8 Data Width Setting Function COL Mode Function L 32bit-Data width H 24bit-Data width Operation mode function of THCV233 (MODE[1:0]) MODE[1:0] pins select data transfer mode of THCV233 as Table 2. Table 9 Operation Mode Setting Function for THCV233 MODE[1:0] Operation mode LL Single-in / Distribution Dual-out LH Single-in / Single-out HL Single-in / Dual-out HH Reserved (forbidden) Operation mode function of THCV234 (MODE[1:0]) MODE[1:0] pins select data transfer mode of THCV234 as Table 2. Table 10 Operation Mode Setting Function for THCV234 MODE[1:0] Operation mode LL Dual-in / Selected single-out (Lane 0) LH Dual-in / Single-out HL Dual-in / Selected single-out (Lane 1) HH Single-in /Single-out THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 12/39 THCV233-THCV234_Main-Link_Rev.2.02_E 2-wire serial interface master/slave setting (MSSEL) MSSEL selects Master / Slave side of Sub-Link and 2-wire serial interface in the devices. THCV233 and THCV234 should be with different setting. Table 11 Master / Slave Setting MSSEL Sub-Link Master / Slave (2-wire serial master / slave) L Sub-Link Master side (2-wire serial slave) H Sub-Link Slave side (2-wire serial master) Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. 2-wire serial interface interrupt output (INT) INT outputs interrupt event indicator on Sub-Link Master side of the system. As default setting, INT does not monitor any event. Being set by 2-wire serial interface, THCV233 and THCV234 can monitor any changes of GPIO input pins and internal statuses as an interrupt. Table 12 Interrupt output INT State L Interrupt occurred H Steady state Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. 2-wire serial interface address setting (AIN[1:0]) AIN[1:0] pins determine address setting of THCV233 and THCV234. Both devices should have the same address setting. Table 13 2-wire serial interface address setting select AIN[1:0] 2-wire interface address setting LL 7’b0001011 LH 7’b0110100 HL 7’b1110111 HH Reserved (forbidden) Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 13/39 THCV233-THCV234_Main-Link_Rev.2.02_E Multiple-chip configuration total Rx side LOCKN indicator (DGLOCK) In order to reduce the number of cables needed for HTPDN and LOCKN in multiple-Rx chip configuration, THCV234 is equipped with the DGLOCK pin. When all the DGLOCK pins are connected as in Figure 6, the connected Rx chips can share the CDR lock status, making all the Rx chips in the same operation status. HTPDN HTPDN LOCKN LOCKN RX0P/N V-by-One® HS Transmitter THCV234 RX1P/N DGLOCK RX2P/N RX3P/N Open Open HTPDN LOCKN THCV234 DGLOCK Figure 6 Usage of DGLOCK in multiple-Rx configuration THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 14/39 THCV233-THCV234_Main-Link_Rev.2.02_E LVDS Mapping LVDS data (video data, control data, DE) are mapped as Figure 7. TLC[6] is special bit for DE(data enable), and TLC[5:4] are for control data bits and the other bits are for video data. Among video data there are special assigned bit ‘CTL’ are defined for the data transmission under DE=low condition. The number of LVDS channel depends on color depth mode(COL). TLD[6] is not available in 24bit Data-width mode. Vdiff = (TLCLK +) - (TLCLK-) Vdiff = 0V tTCIP Data width 32, 24 previous cycle current cycle next cycle TLA +/- TLA2 TLA1 TLA6 TLA5 TLA4 TLA3 TLA2 TLA1 TLA0 TLA6 TLA5 TLA4 TLA3 TLA2 TLA1 TLB +/- TLB2 TLB1 TLB6 TLB5 TLB4 TLB3 TLB2 TLB1 TLB0 TLB6 TLB5 TLB4 TLB3 TLB2 TLB1 TLC +/- TLC2 TLC1 TLC6 (DE) TLC5 (V) TLC4 (H) TLC3 TLC2 TLC1 TLC0 TLC6 (DE) TLC5 (V) TLC4 (H) TLC3 TLC2 TLC1 TLD +/- TLD2 TLD1 TLD6 TLD5 TLD4 TLD3 TLD2 TLD1 TLD0 TLD6 TLD5 TLD4 TLD3 TLD2 TLD1 TLE +/- TLE2 TLE1 TLE6 TLE5 TLE4 TLE3 TLE2 TLE1 TLE0 TLE6 TLE5 TLE4 TLE3 TLE2 TLE1 Data Enable Control data bit Figure 7 LVDS Data mapping timing diagram THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 15/39 THCV233-THCV234_Main-Link_Rev.2.02_E Table 14 LVDS Color Data Mapping Table THCV233 Input TLA[0] TLA[1] TLA[2] TLA[3] TLA[4] TLA[5] TLA[6] TLB[0] TLB[1] TLB[2] TLB[3] TLB[4] TLB[5] TLB[6] TLC[0] TLC[1] TLC[2] TLC[3] TLC[4] TLC[5] TLC[6] TLD[0] TLD[1] TLD[2] TLD[3] TLD[4] TLD[5] TLD[6] TLE[0] TLE[1] TLE[2] TLE[3] TLE[4] TLE[5] TLE[6] THCV234 Output RLA[0] RLA[1] RLA[2] RLA[3] RLA[4] RLA[5] RLA[6] RLB[0] RLB[1] RLB[2] RLB[3] RLB[4] RLB[5] RLB[6] RLC[0] RLC[1] RLC[2] RLC[3] RLC[4] RLC[5] RLC[6] RLD[0] RLD[1] RLD[2] RLD[3] RLD[4] RLD[5] RLD[6] RLE[0] RLE[1] RLE[2] RLE[3] RLE[4] RLE[5] RLE[6] COL H (8bit) R[2] R[3] R[4] R[5] R[6] R[7] G[2] G[3] G[4] G[5] G[6] G[7] B[2]*2 B[3]*2 B[4]*2 B[5]*2 B[6]*2 B[7]*2 HSYNC VSYNC DE R[0] R[1] G[0] G[1] B[0]*2 B[1]*2 N/A*1 Channel Power Down L (10bit) R[4] R[5] R[6] R[7] R[8] R[9] G[4] G[5] G[6] G[7] G[8] G[9] B[4]*2 B[5]*2 B[6]*2 B[7]*2 B[8]*2 B[9]*2 HSYNC VSYNC DE R[2] R[3] G[2] G[3] B[2]*2 B[3]*2 CONT[1]*2*3 R[0]*2 R[1]*2 G[0]*2 G[1]*2 B[0]*2 B[1]*2 CONT[2]*2*3 Symbol defined by V-by-One® HS D2 D3 D4 D5 D6 D7 D10 D11 D12 D13 D14 D15 D18 D19 D20 D21 D22 D23 Hsync Vsync DE D0 D1 D8 D9 D16 D17 D25*3 D30 D31 D28 D29 D26 D27 D24*3 *1 N/A: Not available, THCV234 output RLDn[6]=Low. *2 CTL bits, which are carried during DE=Low except the 1st and the last pixel *3 3D flags defined in the V-by-One® HS Standard are assigned to the following bit. V-by-One® HS Standard Packer/Unpacker D[24](3DLR) <=> LVDS T/RLE[6] V-by-One® HS Standard Packer/Unpacker D[25](3DEN) <=> LVDS T/RLD[6] THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 16/39 THCV233-THCV234_Main-Link_Rev.2.02_E THCV234 LVDS Reduced swing output function (RS) RS controls THCV234 LVDS output swing level. RS L H Table 15 LVDS output swing level Output swing Reduced swing (200mV typical) Normal swing (350mV typical) THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 17/39 THCV233-THCV234_Main-Link_Rev.2.02_E CML Buffer THCV233 CAVDL THCV234 CAVDL 50W 50W C=75~ 200nF TXnP C=75~ 200nF Zdiff=100W TXnN RXnP RXnN 50W n=0,1 50W Vterm~1.3v CAGND CML Transmitter CML Receiver Capacitor on transmitter side is mandatory, while receiver side is optional and recommended. Figure 8 High-Speed CML Buffer Scheme THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 18/39 THCV233-THCV234_Main-Link_Rev.2.02_E Lock detect and Hot-plug function When IOSEL=L, LOCKN and HTPDN are both open drain outputs from THCV234. Pull-up resistors are needed at THCV233 side to 3.3V. See Figure 9. If THCV234 is not active (power down mode (PDN[0]=L) or powered off), HTPDN is open. Otherwise, HTPDN is pulled down by THCV234. HTPDN of THCV233 side is high when THCV234 is not active or the receiver board is not connected. Then THCV233 enters into the power down mode. When HTPDN transits from High to Low, THCV233 starts up and transmits training pattern for link training. LOCKN indicates whether THCV234 is in the lock state or not. If THCV234 is in the unlock state, LOCKN is open. Otherwise (in the lock state), it’s pulled down by THCV234. THCV233 keeps transmitting training pattern until LOCKN transits to Low. After training done, THCV234 sinks current and LOCKN is Low. Then THCV233 starts transmitting normal video pattern. When IOSEL=H, equivalent training processes are driven by Sub-Link. THCV233 THCV234 3.3V (THCV233 side) 10kΩ HTPDN 3.3V (THCV233 side) 10kΩ LOCKN Figure 9 Hot-plug and Lock Detect Scheme No HTPDN connection option Even when IOSEL=L, HTPDN connection between THCV233 and THCV234 can be omitted as an application option. In this case, HTPDN at the Transmitter side should always be taken as Low. See Figure 10. THCV233 THCV234 HTPDN HTPDN 3.3V (THCV233 side) 10kΩ LOCKN Figure 10 HTPDN is not Connected Scheme THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 19/39 THCV233-THCV234_Main-Link_Rev.2.02_E THCV233 Pre-emphasis function (PRE) Pre-emphasis can equalize severe signal degradation caused by long distance or high-speed transmission. PRE, select the strength of pre-emphasis. Table 16 Pre-emphasis function table PRE Description L without Pre-emphasis with 100% Pre-emphasis H Field BET Operation In order to help users to check validity of high speed serial lines (Main-link), THCV233/THCV234 has an operation mode in which they act as a bit error tester (BET). In this mode, THCV233 internally generates test pattern which is then serialized onto the Main-link. THCV234 receives the data stream and checks bit errors. This "Field BET" mode is activated by setting BET= H both on THCV233 and THCV234. Pattern Generator CLK is from LVDS-CLK and the pattern is then 8b/10b encoded, scrambled, and serialized onto the Main-link. As for THCV234, the internal test pattern check circuit gets enabled and reports result on ALNOUT pin. The ALNOUT pin goes LOW whenever bit errors occur, or it stays HIGH when there is no bit error. Please refer to Figure 11. User can select 2 kinds of check result, “Latched-result” or “NOT latched result”. The latch is reset by setting RS=L. Table 17 THCV233-234 Field BET operation pin settings THCV233 BET L H H THCV234 BET RS L H L H H Condition Operation Output Latch select Normal Operation NOT latched result FieldBET Operation Latched result Table 18 THCV234 Field BET result ALNOUT Output L Bit error occurred H No error THCV233 LVDS-CLK THCV234 Test Pattern Checker Test Pattern Generator ALNOUT Test Point for Field BET BET=H BET=H Latch select Figure 11 Field BET Configuration THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 20/39 THCV233-THCV234_Main-Link_Rev.2.02_E 9. Absolute Maximum Ratings Table 19 THCV233 Absolute Maximum Ratings Parameter 1.8v Supply Voltage(CAVDL,CPVDL,VDD) 3.3v Supply Voltage(LAVDH) CMOS Input Voltage CMOS Bi-directional buffer Input / Output Voltage LVDS Receiver Input Voltage CML Transmitter Output Voltage CML Bi-directional buffer Input / Output Voltage Output Current Storage Temperature Junction Temperature Reflow Peak Temperature/Time Maximum Power Dissipation @+25°C Symbol VDL VDH - Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -50 -55 - Typ. - Max. +2.1 +4.0 VDH+0.3 3.6 VDH+0.3 VDL+0.3 VDL+0.3 50 +125 +125 +260/10sec 3.2 Units V V V V V V V mA °C °C °C W Typ. - Max. +2.1 +4.0 VDH+0.3 3.6 VDL+0.3 VDL+0.3 VDH+0.3 30 +125 +125 +260/10sec 3.2 Units V V V V V V V mA °C °C °C W Table 20 THCV234 Absolute Maximum Ratings Parameter 1.8v Supply Voltage(CAVDL,VDD) 3.3v Supply Voltage(LAVDH) CMOS Input Voltage CMOS Bi-directional buffer Input / Output Voltage CML Receiver Input Voltage CML Bi-directional buffer Input / Output Voltage LVDS Transmitter Output Voltage Output Current Storage Temperature Junction Temperature Reflow Peak Temperature/Time Maximum Power Dissipation @+25°C Symbol VDL VDH - Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -30 -55 - “Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 21/39 THCV233-THCV234_Main-Link_Rev.2.02_E 10. Operating Conditions There are two types of operating temperature ranges as shown below. 1. From 0°C to 70°C 2. From -40°C to 105°C Details are shown in the table below. Table 21 THCV233 Operating Conditions (0°C≤TMP≤70°C) Parameter 1.8v Supply Voltage(CAVDL,CPVDL,VDD) 3.3v Supply Voltage(LAVDH) Operating Temperature Symbol VDL VDH TMP Min. 1.62 3.00 0 Typ. 1.80 3.30 - Max. 1.98 3.60 70 Units V V °C Typ. Max. Units 1.80 3.30 - 1.98 3.60 105 V V °C Max. 1.98 3.60 70 Units V V °C Max. 1.98 3.60 105 Units V V °C Table 22 THCV233 Operating Conditions (-40°C≤TMP≤105°C) Parameter Symbol 1.8v Supply Voltage(CAVDL,CPVDL,VDD) 3.3v Supply Voltage(LAVDH) Operating Temperature VDL VDH TMP Min. 1.62 or 1.70 (1) 3.00 -40 Table 23 THCV234 Operating Conditions (0°C≤TMP≤70°C) Parameter 1.8v Supply Voltage(CAVDL,CPVDL,VDD) 3.3v Supply Voltage(LAVDH) Operating Temperature Symbol VDL VDH TMP Min. 1.62 3.00 0 Typ. 1.80 3.30 - Table 24 THCV234 Operating Conditions (-40°C≤TMP≤105°C) Parameter 1.8v Supply Voltage(CAVDL,CPVDL,VDD) 3.3v Supply Voltage(LAVDH) Operating Temperature (1) Symbol VDL VDH TMP Min. 1.70 3.00 -40 Typ. 1.80 3.30 - Maximum value of LVDS CLK Frequency depends on minimum value of VDL. Please refer to page 1. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 22/39 THCV233-THCV234_Main-Link_Rev.2.02_E 11. Electrical Specifications DC Specifications Table 25 THCV233 and THCV234 3.3V CMOS DC Specifications Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage VOL Low Level Output Voltage IIH IIL Input Leak Current High Input Leak Current Low Symbol VTTH VTTL Parameter LVDS Differential Input High Threshold LVDS Differential Input Low Threshold ITIH LVDS Input Leak Current High ITIL LVDS Input Leak Current Low RTIN VTOD LVDS Differential Input Resistance CML Differential Mode Output Voltage PRE CML Pre-emphasis Level VTOC CML Common Mode Output Voltage ITOH ITOS CML Output Leak Current High CML Output Short Circuit Current Symbol VRTH VRTL Parameter CML Differential Input High Threshold CML Differential Input Low Threshold IRIH CML Input Leak Current High IRIL CML Input Leak Current Low IRRIH IRRIL RRIN IROS CML Input Current High CML Input Current Low CML Differential Input Resistance LVDS Differential Mode Output Voltage (Normal Swing) LVDS Differential Mode Output Voltage (Reduced Swing) Change in VROD between Complementary Output States LVDS Common Mode Output Voltage Change in VROC between Complementary Output States LVDS Output Short Circuit Current IROZ LVDS Output TRI-STATE Current Conditions I,B,BO,BPU I,B,BO,BPU B IOH=-8mA B IOL=8mA BO,BPU IOL=4mA VIN=VDH VIN=GND Min. 2.1 0 2.4 -10 -10 Typ. - Max. VDH 0.7 VDH 0.4 0.4 +10 +10 Units V V V V V uA uA Min. -100 Typ. - Max. 100 - Units mV mV - - ±10 uA Table 26 THCV233 LVDS, CML DC Specifications Conditions TLx+/-=VDH, PDN[0]=L x=A~E,CLK TLx+/-=GND, PDN[0]=L x=A~E,CLK PDN[0]=L PRE=L PRE=H PRE=L PRE=H PDN[0]=L VDL=1.8V - - ±10 uA 80 200 80 100 300 0 100 VDL-VTOD VDL-2×VTOD - 120 400 120 ±10 - Ω mV % % mV mV uA mA -90 Table 27 THCV234 LVDS, CML DC Specifications VROD ΔVROD VROC ΔVROC Conditions PDN[0]=L, RXnP/N=VDL n=0,1 PDN[0]=L, RXnP/N=GND n=0,1 Min. -50 Typ. - Max. 50 - Units mV mV - - ±10 uA - - ±10 uA RXnP/N=VDL, n=0,1 RXnP/N=GND, n=0,1 - -6 80 100 2 120 mA mA Ω RL=100Ω, RS=H 250 350 450 mV RL=100Ω, RS=L 100 200 300 mV RL=100Ω - - 35 mV RL=100Ω 1.125 1.25 1.375 V RL=100Ω RLx+/-=GND PDN[0]=L, RLx+/-=GND, VDH x=A~E,CLK - - 35 mV -30 - - mA - - ±10 uA THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 23/39 THCV233-THCV234_Main-Link_Rev.2.02_E Table 28 THCV233-234 CML Bi-Directional DC Specifications Symbol VBTH Parameter Bi-Directional Buffer Differential Input High Threshold Min. Typ. Max. Units - Conditions - - 175 mV VBTL Bi-Directional Buffer Differential Input Low Threshold - -175 - - mV VBTC Bi-Directional Buffer Input Terminated Common Voltage - VDL-0.6 - VDL-0.3 V 500 - 800 mV VDL-0.6 - VDL-0.3 V -30 - - mA - - ±10 uA 390 - 550 Ω VBOD VBOC IBOS IBIZ RBIN Bi-Directional Buffer Differential Output Voltage Bi-Directional Buffer Output Voltage Bi-Directional Buffer Output Short Circuit Current Bi-Directional Buffer Output Leak Current Bi-Directional Buffer Differential Input Resistance RLB=390Ω xCMP/N=VDL, GND PDN=L - THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 24/39 THCV233-THCV234_Main-Link_Rev.2.02_E Supply Currents Table 29 THCV233 Supply Currents Symbol ITCCW ITCCW_M Parameter Transmitter Supply Current for VDL Main-Link & Sub-Link are active (Worst Case Pattern as shown in Figure 11) Transmitter Supply Current for VDL Only Main-Link is active (Worst Case Pattern as shown in Figure 11) ITCCW_S Transmitter Supply Current for VDL Only Sub-Link is active ITCCW33 Transmitter Supply Current for VDH Main-Link & Sub-Link are active (Worst Case Pattern as shown in Figure 11) Transmitter Supply Current for VDH ITCCW33_M Only Main-Link is active (Worst Case Pattern as shown in Figure 11) Conditions SiSo 10bit, PRE=H PDN[1:0]=HH SiDo 10bit, PRE=H PDN[1:0]=HH SiDDo 10bit, PRE=H PDN[1:0]=HH SiSo 10bit, PRE=H PDN[1:0]=LH SiDo 10bit, PRE=H PDN[1:0]=LH SiDDo 10bit, PRE=H PDN[1:0]=LH PDN[1:0]=HL SiSo 10bit, PRE=H PDN[1:0]=HH SiDo 10bit, PRE=H PDN[1:0]=HH SiDDo 10bit, PRE=H PDN[1:0]=HH SiSo 10bit, PRE=H PDN[1:0]=LH SiDo 10bit, PRE=H PDN[1:0]=LH SiDDo 10bit, PRE=H PDN[1:0]=LH Min. Typ. Max. Units - - 175 mA - - 210 mA - - 250 mA - - 150 mA - - 185 mA - - 225 mA - - 25 mA - - 12 mA - - 12 mA - - 12 mA - - 12 mA - - 12 mA - - 12 mA ITCCW33_S Transmitter Supply Current for VDH Only Sub-Link is active PDN[1:0]=HL - - 1 mA ITCCS Transmitter Power Down Supply Current PDN[1:0]=LL All Inputs =Fixed LorH - - 170 uA THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 25/39 THCV233-THCV234_Main-Link_Rev.2.02_E Table 30 THCV234 Supply Currents Symbol IRCCW IRCCW_M Parameter Receiver Supply Current for VDL Main-Link & Sub-Link are active (Worst Case Pattern as shown in Figure 11) Receiver Supply Current for VDL Only Main-Link is active (Worst Case Pattern as shown in Figure 11) IRCCW_S Receiver Supply Current for VDL Only Sub-Link is active IRCCW33 Receiver Supply Current for VDH Main-Link & Sub-Link are active (Worst Case Pattern as shown in Figure 11) Conditions SiSo 10bit, PDN[1:0]=HH DiSo 10bit, PDN[1:0]=HH DiSSo 10bit, PDN[1:0]=HH SiSo 10bit, PDN[1:0]=LH DiSo 10bit, PDN[1:0]=LH DiSSo 10bit, PDN[1:0]=LH Min. Typ. Max. Units - - 115 mA - - 120 mA - - 115 mA - - 90 mA - - 90 mA - - 90 mA - - 25 mA - - 100 mA - - 100 mA - - 100 mA - - 90 mA - - 90 mA - - 90 mA PDN[1:0]=HL Receiver Supply Current for VDH IRCCW33_M Only Main-Link is active (Worst Case Pattern as shown in Figure 11) SiSo 10bit, PDN[1:0]=HH DiSo 10bit, PDN[1:0]=HH DiSSo 10bit, PDN[1:0]=HH SiSo 10bit, P PDN[1:0]=LH DiSo 10bit, PDN[1:0]=LH DiSSo 10bit, PDN[1:0]=LH IRCCW33_S Receiver Supply Current for VDH Only Sub-Link is active PDN[1:0]=HL - - 5 mA IRCCS Receiver Power Down Supply Current PDN[1:0]=LL All Inputs =Fixed LorH - - 150 uA Vdiff = (TLCLK +) - (TLCLK -) Vdiff = 0V tTCIP previous cycle current cycle next cycle TLA +/TLB +/TLC +/- H H TLD +/TLE +/- Data Enable Control bit Figure 12 Worst Case Pattern THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 26/39 THCV233-THCV234_Main-Link_Rev.2.02_E Switching Characteristics Table 31 DE requirement Symbol tDEH Parameter DE=High Duration tDEL DE=Low Duration Conditions SiSo, SiDDo SiDo Min. 2×tTCIP 2×tTCIP 4×tTCIP Typ. - Max. - Units sec sec sec Max. 111 50 25 111 50 25 5×tTCIP/7 5×tTCIP/7 440(1) 390(1) 330(1) +tSK tTCIP/7+tSK 2×tTCIP/7+tSK 3×tTCIP/7+tSK 4×tTCIP/7+tSK 5×tTCIP/7+tSK 6×tTCIP/7+tSK 3×tTCIP/7 150 2 150.2 10 20 10 10 Units ns ns ns ns ns ns ns ns ps ps ps ns ns ns ns ns ns ns ns ps UI ns ns ns ms ms ns ms ms Table 32 THCV233 Switching Characteristics (0°C≤TMP≤70°C) Symbol Parameter tTCIP TLCLK Period tTCIH tTCIL LVDS Differential Clock High Time LVDS Differential Clock Low Time tSK LVDS Receiver Skew Margin tTIP1 tTIP0 tTIP6 tTIP5 tTIP4 tTIP3 tTIP2 tTALN tTRF tTOSK tTCD tTLH tTPD tTPDL tTPLL0 tTPLL1 tTNP0 tTNP1 LVDS Input Data Position1 LVDS Input Data Position0 LVDS Input Data Position2 LVDS Input Data Position3 LVDS Input Data Position4 LVDS Input Data Position5 LVDS Input Data Position6 LVDS-ALNIN timing tolerance CML Output Rise and Fall Time(20%-80%) CML Lane0/1 Output Inter Pair Skew Input Clock to Output Data Delay VDL On to VDH On Delay Power On to PDN High Delay PDN Low Pulse Width PDN High to CML Output Delay PDN Low to CML Output High Fix Delay LOCKN High to Training Pattern Output Delay LOCKN Low to Data Pattern Output Delay Conditions COL=H, Si/So COL=H, Si/DDo COL=H, Si/Do COL=L, Si/So COL=L, Si/DDo COL=L, Si/Do tTCIP=75MHz tTCIP=85MHz tTCIP=100MHz SiDDo 10bit 85MHz - Min. 10 10 10 11.76 11.76 11.76 2×tTCIP/7 2×tTCIP/7 -440(1) -390(1) -330(1) -tSK tTCIP/7-tSK 2×tTCIP/7-tSK 3×tTCIP/7-tSK 4×tTCIP/7-tSK 5×tTCIP/7-tSK 6×tTCIP/7-tSK 0 50 -2 143.4 0 0 1 - Typ. 4×tTCIP/7 3×tTCIP/7 0 tTCIP/7 2×tTCIP/7 3×tTCIP/7 4×tTCIP/7 5×tTCIP/7 6×tTCIP/7 - THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 27/39 THCV233-THCV234_Main-Link_Rev.2.02_E Table 33 THCV233 Switching Characteristics (-40°C≤TMP≤105°C) Symbol tTCIP Parameter TLCLK Period tTCIH tTCIL LVDS Differential Clock High Time LVDS Differential Clock Low Time tSK LVDS Receiver Skew Margin tTIP1 tTIP0 tTIP6 tTIP5 tTIP4 tTIP3 tTIP2 tTALN tTRF tTOSK tTCD tTLH tTPD tTPDL tTPLL0 tTPLL1 LVDS Input Data Position1 LVDS Input Data Position0 LVDS Input Data Position2 LVDS Input Data Position3 LVDS Input Data Position4 LVDS Input Data Position5 LVDS Input Data Position6 LVDS-ALNIN timing tolerance CML Output Rise and Fall Time(20%-80%) CML Lane0/1 Output Inter Pair Skew Input Clock to Output Data Delay VDL On to VDH On Delay Power On to PDN High Delay PDN Low Pulse Width PDN High to CML Output Delay PDN Low to CML Output High Fix Delay LOCKN High to Training Pattern Output Delay LOCKN Low to Data Pattern Output Delay tTNP0 tTNP1 Conditions COL=H, Si/So COL=H, Si/DDo COL=H, Si/Do COL=L, Si/So VDL=1.62V~1.98V COL=L, Si/DDo VDL=1.62V~1.98V COL=L, Si/Do VDL=1.62V~1.98V COL=L, Si/So VDL=1.7V~1.98V COL=L, Si/DDo VDL=1.7V~1.98V COL=L, Si/Do VDL=1.7V~1.98V tTCIP=75MHz tTCIP=85MHz tTCIP=100MHz SiDDo 10bit 85MHz - Min. 10 10 10 Typ. - Max. 111 50 25 Units ns ns ns 13.33 - 111 ns 13.33 - 50 ns 13.33 - 25 ns 12.35 - 111 ns 12.35 - 50 ns 12.35 - 25 ns 2×tTCIP/7 2×tTCIP/7 -440(1) -390(1) (1) -330 -tSK tTCIP/7-tSK 2×tTCIP/7-tSK 3×tTCIP/7-tSK 4×tTCIP/7-tSK 5×tTCIP/7-tSK 6×tTCIP/7-tSK 0 50 -2 143.4 0 0 1 - 4×tTCIP/7 3×tTCIP/7 0 tTCIP/7 2×tTCIP/7 3×tTCIP/7 4×tTCIP/7 5×tTCIP/7 6×tTCIP/7 - 5×tTCIP/7 5×tTCIP/7 440(1) 390(1) (1) 330 +tSK tTCIP/7+tSK 2×tTCIP/7+tSK 3×tTCIP/7+tSK 4×tTCIP/7+tSK 5×tTCIP/7+tSK 6×tTCIP/7+tSK 3tTCIP/7 150 2 150.2 10 20 ns ns ps ps ps ns ns ns ns ns ns ns ns ps UI ns ns ns ms ms ns - - - 10 ms - - - 10 ms THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 28/39 THCV233-THCV234_Main-Link_Rev.2.02_E Table 34 THCV234 Switching Characteristics (0°C≤TMP≤70°C) Symbol Parameter tRBIT Unit Interval tRISK tRLVT tROP1 tROP0 tROP6 tROP5 tROP4 tROP3 tROP2 tRALN tRDC tRLH tRPD tRPDL tRHPD0 tRHPD1 CML Lane0/1 Input Inter Pair Skew Margin LVDS Differential Output Transition Time LVDS Output Data Position1 LVDS Output Data Position0 LVDS Output Data Position6 LVDS Output Data Position5 LVDS Output Data Position4 LVDS Output Data Position3 LVDS Output Data Position2 LVDS-ALNOUT timing accuracy Input Data to Output Clock Delay VDL On to VDH On Delay Power On to PDN High Delay PDN Low Pulse Width PDN High to HTPDN Low Delay PDN Low to HTPDN High Delay Training Pattern Input to LOCKN Low Delay PDN Low to LOCKN High Delay LOCKN Low to LVDS Output Delay LOCKN High to LVDS HighZ Delay tRPLL0 tRPLL1 tRLCK0 tRLCK1 Conditions COL=H COL=L SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit - Min. 333 294 -0.2 tTCIP/7-0.2 2×tTCIP/7-0.2 3×tTCIP/7-0.2 4×tTCIP/7-0.2 5×tTCIP/7-0.2 6×tTCIP/7-0.2 2×tTCIP/7 808×tRBIT+8 0 0 1.0 - Typ. tTCIP/30 tTCIP/40 0.6 0 tTCIP/7 2×tTCIP/7 3×tTCIP/7 4×tTCIP/7 5×tTCIP/7 6×tTCIP/7 5×tTCIP/7 - Max. 3704 2778 15 1.5 0.2 tTCIP/7+0.2 2×tTCIP/7+0.2 3×tTCIP/7+0.2 4×tTCIP/7+0.2 5×tTCIP/7+0.2 6×tTCIP/7+0.2 8tTCIP/7 808×tRBIT+14.5 1 1 Units ps ps UI ns ns ns ns ns ns ns ns ns ns ns ns ms us us - - - 10 ms - - - 10 1 0 us ms ns Table 35 THCV234 Switching Characteristics (-40°C≤TMP≤105°C) Symbol Parameter tRBIT Unit Interval tRISK tRLVT tROP1 tROP0 tROP6 tROP5 tROP4 tROP3 tROP2 tRALN tRDC tRLH tRPD tRPDL tRHPD0 tRHPD1 CML Lane0/1 Input Inter Pair Skew Margin LVDS Differential Output Transition Time LVDS Output Data Position1 LVDS Output Data Position0 LVDS Output Data Position6 LVDS Output Data Position5 LVDS Output Data Position4 LVDS Output Data Position3 LVDS Output Data Position2 LVDS-ALNOUT timing accuracy Input Data to Output Clock Delay VDL On to VDH On Delay Power On to PDN High Delay PDN Low Pulse Width PDN High to HTPDN Low Delay PDN Low to HTPDN High Delay Training Pattern Input to LOCKN Low Delay PDN Low to LOCKN High Delay LOCKN Low to LVDS Output Delay LOCKN High to LVDS HighZ Delay tRPLL0 tRPLL1 tRLCK0 tRLCK1 Conditions COL=H COL=L SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit 85MHz SiSo 10bit - Min. 351 351 -0.2 tTCIP/7-0.2 2×tTCIP/7-0.2 3×tTCIP/7-0.2 4×tTCIP/7-0.2 5×tTCIP/7-0.2 6×tTCIP/7-0.2 2×tTCIP/7 808×tRBIT+8 0 0 1.0 - Typ. tTCIP/30 tTCIP/40 0.6 0 tTCIP/7 2×tTCIP/7 3×tTCIP/7 4×tTCIP/7 5×tTCIP/7 6×tTCIP/7 5×tTCIP/7 - Max. 3704 2778 15 1.5 0.2 tTCIP/7+0.2 2×tTCIP/7+0.2 3×tTCIP/7+0.2 4×tTCIP/7+0.2 5×tTCIP/7+0.2 6×tTCIP/7+0.2 8×tTCIP/7 808×tRBIT+14.5 1 1 Units ps ps UI ns ns ns ns ns ns ns ns ns ns ns ns ms us us - - - 10 ms - - - 10 1 0 us ms ns Table 36 THCV233-234 CML Bi-Directional Switching Characteristics Symbol tBUI tBRF tBPJTX tBPJRX Parameter Bi-Directional Buffer Unit Interval Bi-Directional Buffer Rise and Fall Time(20%-80%) Bi-Directional Buffer Transmitter Period Jitter Accuracy (peak to peak) Bi-Directional Buffer Receiver Period Jitter Tolerance (peak to peak) - Conditions Min. 80 Typ. 100 Max. 120 Units ns - 150 - 500 ps - - - 1 ns - 8 - - ns THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 29/39 THCV233-THCV234_Main-Link_Rev.2.02_E 12. AC Timing Diagrams and Test Circuits LVDS Input Switching Characteristics Vdiff = (TLCLK+) - (TLCLK-) Vdiff = 0V tTCIP Vdiff = (TLx +) - (TLx -) TLx6 TLx5 TLx4 TLx3 TLx2 TLx1 TLx0 TLx6 TLx5 TLx4 TLx3 TLx2 TLx1 x=A,B,C,D,E tTIP1 tTIP0 tTIP6 tTIP5 tTIP4 tTIP3 tTIP2 tTCIL tTCIH Vdiff = (TLCLK +) - (TLCLK -) Vdiff = 0V Figure 13 LVDS Input Switching Timing Diagrams Vdiff = (TLCLK0+) – (TLCLK0-) DE DE DE DE DE DE Vdiff = (TLC0+) – (TLC0-) tDEH tDEL Figure 14 DE period requirement THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 30/39 THCV233-THCV234_Main-Link_Rev.2.02_E LVDS Output Switching Characteristics tROP2 tROP3 tROP4 tROP5 tROP6 tROP0 tROP1 Vdiff = (RLx +) - (RLx-) RLx6 RLx5 RLx4 RLx3 Vdiff = (RLCLK +) - (RLCLK-) RLx2 RLx1 RLx0 RLx6 RLx5 RLx4 RLx3 RLx2 RLx1 Vdiff = 0V tTCIP x=A,B,C,D,E Figure 15 LVDS Output Switching Timing Diagrams RLx+ 5pF RL=100W RLxx=A,B,C,D,E 80% Vdiff = (RLx +) - (RLx-) 20% tRLVT tRLVT Figure 16 LVDS Output Switching Timing Diagram and Test Circuit. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 31/39 THCV233-THCV234_Main-Link_Rev.2.02_E CML Output Switching Characteristics TXnP 100nF 50W 100nF 50W TXnN < 5mm n=0,1 80% Vdiff = (TXnP) - (TXnN) 20% tTRF tTRF Vdiff = (TX0P) - (TX0N) Vdiff = 0V tTOSK Vdiff = (TX1P) - (TX1N) Vdiff = 0V Vdiff = (RX0 +) - (RX0-) Vdiff = 0V tRISK Vdiff = (RX1 +) - (RX1-) Vdiff = 0V Figure 17 High-Speed CML Output Switching Timing Diagrams and Test Circuit THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 32/39 THCV233-THCV234_Main-Link_Rev.2.02_E CML Bi-directional Output Switching Characteristics xCMP 100nF 240W 100nF 240W xCMN 80% Vdiff = (xCMP) - (xCMN) X=T,R 20% tBRF tBRF Figure 18 Bi-directional CML Switching Timing Diagrams and Test Circuit xCMP 5pF RLB=390W xCMN x=T,R Figure 19 Bi-directional CML VBOD/VBOC Test Circuit THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 33/39 THCV233-THCV234_Main-Link_Rev.2.02_E Latency Characteristics Vdiff = (TLCLK +) - (TLCLK -) Vdiff = 0V tTCD Vdiff = (TX0 +) - (TX0-) pixel 1st bit pixel 1st bit Vdiff = (RX0 +) - (RX0-) tRDC Vdiff = (RLCLK +) - (RLCLK -) Vdiff = 0V Figure 20 THCV233 and THCV234 Latency THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 34/39 THCV233-THCV234_Main-Link_Rev.2.02_E Lock and Unlock Sequence 1.62V VDL Power On 3.0V tTLH VDH Power On TLCLK +/TLx +/- THCV233 Data Pattern HTPDN Low-level tTPD tTPDL PDN LOCKN tTPLL0 TX0P/N tTNP1 Training pattern Fix to VDL tTNP0 Normal pattern tTPLL1 Training pattern x=A,B,C,D,E 1.62V VDL Power On 3.0V tRLH VDH Power On tRPD tRPDL PDN tRHPD0 tRHPD1 HTPDN THCV234 Training pattern RX0P/N Normal pattern tRPLL0 tRPLL1 LOCKN tRLCK1 tRLCK0 RLCLK +/- High Z RLx +/- High Z Valid Data Pattern x=A,B,C,D,E Figure 21 THCV233 and THCV234 Lock/Unlock Sequence VDH must not precedes VDL, while tTLH and tRLH min. is 0sec; therefore, VDL/H can be at the same time. tTPD and tRPD minimum is 0sec; therefore, PDN can be applied at the same time as VDL and VDH. tTPLL0 is the time from “both PDN=High and HTPDN=Low“ moment to Training pattern ignition. HTPDN could transit from High to Low under PDN=High condition at THCV233, which is different from what Figure 21 indicates but is natural situation. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 35/39 THCV233-THCV234_Main-Link_Rev.2.02_E Note 1)LVDS input pin connection When LVDS line is not driven from the previous device, the line is pulled up to 3.3V internally in THCV233.This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose operating condition is lower voltage power supply than 3.3V. This phenomenon may happen at power on phase of the whole system including THCV233. One solution for this problem is PDN[0]=L control during no LVDS input period because pull-up resistors are cut off at power down state. LVDS Tx side PCB LVDS Rx side PCB VDD Low VDD THCV233 LVDS Tx or LVDS Tx integrated device LVDS input buffer Internal circuit of THCV233 2)Power On Sequence Do not apply VDH before VDL. VDL and VDH can be applied at the same time. 3)Data Input Sequence Don’t input TLCLK+/- before THCV233 is on in order to keep absolute maximum ratings. 4)Cable Connection and Disconnection Don’t connect and disconnect the LVDS cable, when the power is supplied to the system. 5)GND Connection Connect the each GND of the PCB which Transmitter, Receiver and THCV215 on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 6)Low Input Pulse into PDN[1:0] Period Requirement Don’t Input Low Pulse within 1msec into PDN[1:0]. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 36/39 THCV233-THCV234_Main-Link_Rev.2.02_E 7)Multiple device connection HTPDN and LOCKN signals are supposed to be connected proper for their purpose like the following figure. HTPDN should be from just one Rx to multiple Tx because its purpose is only ignition of all Tx. LOCKN should be connected so as to indicate that all Rx CDR become ready to receive normal operation data. LOCKN of Tx side can be simply split to multiple Tx. THCV234 DGLOCK connection is appropriate for multiple Rx use. Also possible time difference of internal processing time (p.26 THCV233 tTCD and p.27 THCV234 tRDC) on multiple data stream must be accommodated and compensated by the following destination device connected to multiple THCV234, which may have internal FIFO. THCV233 THCV234 HTPDN HTPDN LOCKN LOCKN clkin.1 clkout.1 FIFO DGLOCK Source Device Ex. synchronized Time diff. comes up THCV233 THCV234 HTPDN HTPDN LOCKN LOCKN Destination Device FIFO clkin.2 clkout.2 DGLOCK Internal processing time tTCD Internal processing time tRDC THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 37/39 THCV233-THCV234_Main-Link_Rev.2.02_E Package 0.85 0.65 7.00 0.20 0.025 7.00 0.10 1 PIN INDEX SEATING PLANE TOP VIEW SIDE VIEW 4.03 1.085 13 24 12 25 1 36 4.03 0.125 R 0.40 48 1.085 0.450 1 PIN ID 0.20 R 37 0.50 0.40 0.25 BOTTOM VIEW Unit:mm Exposed PAD is GND and must be soldered to PCB. THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 38/39 THCV233-THCV234_Main-Link_Rev.2.02_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. Product Application 5.1 Application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. This product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s request, testing of all functions and performance of the product is not necessarily performed. 9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. 10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. THine Electronics, Inc. [email protected] THine Electronics, Inc. Security E Copyright©2016 THine Electronics, Inc. 39/39