E2A0039-16-X2 ¡ Semiconductor MSM7532 ¡ Semiconductor This version: Jan. 1998 MSM7532 Previous version: Nov. 1996 Single Chip MSK Modem with Compandor for Cordless Telephone GENERAL DESCRIPTION The MSM7532 is a baseband device with a modem function and a baseband voice signal processing function for analog cordless telephone. The voice signal transmitter in this IC consists of a high-pass filter, compressor, scrambler, pre-emphasis, limiter, and splatter filter. The voice signal receiver consists of a bandpass filter, a de-scrambler , a de-emphasis, an expander, an electronic volume, and a ceramic receiver driving circuit. The MODEM in this IC transmits and receives MSK (Minimum Shift Keying) modem signals. FEATURES • Built-in ceramic receiver drive amplifiers • The compander input reference level, limiter level, and modem transmit level are easy to be externally adjusted. • Built-in 2-bit electronic volume • A microphone amplifier and an amplifier available for users are built in. • Mode settings using parallel interfaces • Built-in compander dynamic range: 70 dB • Built-in maximum gain limit circuit for expander • The bit rate of MSK modem is switchable between 2400 bps and 1200 bps. • Scrambler and emphasis can be used by serially connecting them or can be used separately with each other. • Three kinds of the reverse frequency of the scrambler are selectable. • The modem receiver functions detect bit synchronous signals and frame synchronous signals. • Four-step power down modes • Built-in crystal oscillation circuit • Wide range of power supply (1.8 V to 5.5 V) • Package: 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name : MSM7532GS-2K) 1/21 – – COMPRESSOR + SW1 PREEMPHASIS HPF1 SW2 MICO MICN – MICP + PRE BPF SCR SW3 + LIMITER SW5 LPF1 SW4 SPLATTER FILTER MOD MIX-LPF MIXER MODL RAIO RCLPF RCLPF SHAPER SD ST BR SW6 DEMOD TAO FRAME DET DEMBPF SW8 ¡ Semiconductor TVI BLOCK DIAGRAM UAO UAI LIML CC3P CC3N CC2 CC1 CMPI TVIO RD RT FD FPS BIT FDE CSH RCP RCN – RAI SW7 – + RBPF DE-SCR SW3 LPF2 SW4 DEEMPHASIS SW2 + HPF2 – RVBU + PDRC OSC SW7 EXPANDER SW1 VOLUME SW9 RCLPF RVO 2/21 MSM7532 VOL2 VOL1 CONT CE3P CE3N CE2 CE1 X2 X1 VOLTAGE REF. CPDL PDN BYP EMP RCK2 RCK1 SEC ME RVE TVE SG VREF VDD GND SGO SGI ¡ Semiconductor MSM7532 43 X1 44 X2 45 SD 46 FD 47 RD 48 RT 49 VDD 50 BIT 51 FPS 52 RCK2 53 RCK1 54 SEC 55 ME 56 ST PIN CONFIGURATION (TOP VIEW) TVE 1 42 PDRC RVE 2 41 RCN PDN 3 40 RCP FDE 4 39 RVBU BYP 5 38 CSH TVIO 6 37 VOL1 TVI 7 36 VOL2 CE3N 28 29 CE3P BR 27 UAO 14 SGO 26 30 CE2 SGI 25 UAI 13 CPDL 24 31 CE1 LIML 23 TAO 12 GND 22 32 EMP (VDD) 21 CMPI 11 MODL 20 33 RAIO VREF 19 MICP 10 CC2 18 34 RAI CC1 17 MICN 9 CC3N 16 35 RVO CC3P 15 MICO 8 56-Pin Plastic QFP Notes: The pin 49 should be used for VDD. The pin 21 should be connected to VDD or opened. 3/21 ¡ Semiconductor MSM7532 PIN AND FUNCTIONAL DESCRIPTIONS TVE Transmit voice signal output control pin. Refer to the TAO pin description. RVE Receive voice signal output control pin. Refer to the RVO pin description. PDN Power down control pin. The four-step power down modes are controlled by the PDN, ME, RVE, and TVE pins. Voice signal Crystal PDN RVE TVE ME Processing Section Transmit Modem Receive Modem Oscillation Circuit Mode 1 1 0 1 X OFF OFF OFF OFF Mode 2 1 0 0 X OFF OFF OFF ON Mode 3 1 1 X X OFF OFF ON ON Mode 4 0 0 0 1 OFF ON ON ON ON ON ON ON Mode 5 Other than above X: Don't care In Mode 5, all the circuits are ON. The MODEM demodulation circuit and FD pin are reset to zero by setting to Mode 1 or Mode 2 (PDN = “1”, RVE = “0”). After turning the power ON, set the LSI into one of these modes, then reset it before using. To hold the voice signal processing section ON during transmission of MSK signals, set the ME and TVE pins to "1". In this case, the input from TVI is not output to TAO. Refer to the TAO pin description. FDE Pin used to control the function of frame synchronous signal detection circuit. If digital "0" is entered in this pin, the FD pin remains reset at "0" level. The RT and RD pins are always active. If digital "1" is entered in this pin, the frame synchronous signal detection circuit becomes active. And the RT and RD pins are fixed at "1" level until the FD pin goes to "1" level by detecting the frame synchronous signals. Refer to Figure 3 "Receive Signal Timing". BYP Compander path selection pin. BYP Transmit side Receive side 0 Compressor is connected to the path. Expander is connected to the path. 1 Compressor is bypassed to the path. Expander is bypassed to the path. Note SW1 When the expander is used, the maximum gain of expander is limited to approximately +12 dB. This tendency will appear as the input signal level is increased when VDD is larger (e. g., 5 V) and VCPDL is smaller (e,g., 0.1 V); the input/output characteristics then change automatically from expander characteristics to linear characteristics with constant gain. 4/21 ¡ Semiconductor MSM7532 TVI, TVIO Pins used to constitute an RC-active filter on the transmit input side. If input signals have frequency components over 50 kHz, these components are output as aliasing noises from the built-in SCF circuit. In order to remove these noises, insert the first or second order RC-active filter with about 10 kHz cut-off frequency, as shown below. <Second order RC-active filter configuration> CMPI C5 R9 C4 R11 Compressor TVIO C7 TVI C6 – + R10 VTVI SGO C4, C5 for DC cutoff In the case of fc = 10 kHz, gain : 0 dB R9 = R10 = R11 = 68 kW C5 = 0.22 mF, C6 = 510 pF, C7 = 110 pF <First order RC-active filter configuration> CMPI C5 R32 C26 C4 Compressor TVIO R33 TVI – + In the case of fc = 10 kHz, gain : 0 dB VTVI R32 = R33 = 51 kW C5 = 0.22 mF, C26 = 300 pF 5/21 ¡ Semiconductor MSM7532 MICO, MICN, MICP MICN is the microphone amplifier inverting input pin, MICP is the non-inverting input pin, and MICO is the output pin. Only during power down mode 1 or 2, the amplifier is powered down and the MICO potential is undefined. These pins can also be used for applications other than microphone amplifier. MICO VDD Output MICN – + MICP CMPI Input pin to the compressor. Connect this pin to the TVIO pin with a 0.1 mF capacitor in order to prevent the malfunction of the compressor which may occur if DC input offset exists. TAO Transmit analog signal output pin. According to control data on ME and TVE, TAO is set as shown below. TAO Note ME TVE 0 0 No signal output (potential = VSG) 0 1 Voice signal output (signal from TVI, TVIO) 1 X MSK modulator output SW6 SW5 X: Don't care UAI, UAO Inverting input pin (UAI) and output pin (UAO) for the amplifier available for users. These pins are used as a gain control amplifier that can match the internal signal level of the LSI with the input level of the radio circuit. The amplifier can drive a resistance over 2 kW. In the power down mode 1 and 2, the amplifier enters power down mode. Since the amplifier uses the power supply for the built-in transmitter, the amplifier should be used to control signals for the transmitter. C28 is a capacitor for oscillation prevention. Be sure to use a capacitor of 20 pF or more. If this amplifier is not used, connect UAI to UAO directly and remove R1, R2, C1, and C28. C1 UAO UAI R1 R2 + – C28 TAO 6/21 ¡ Semiconductor MSM7532 CC3P, CC3N Pins used to connect a capacitor for defining a time constant of output transient response for the compressor. Insert a 0.22 mF capacitor between CC3N and CC3P. CC2, CC1 Pins used to connect capacitors for removing DC offset in the compressor. Insert a 0.22 mF capacitor between CC2 and SGO, and between CC1 and SGO. VREF Output pin for internal reference voltage source. The VREF output voltage is VSG +0.5 V. The voltages into which the voltage between VREF pin and SGO pin is divided by the resistors should be supplied to the LIML, MODL, and CPDL pin, respectively. The VREF pin can be directly connected to the LIML pin, MODL pin, or CPDL pin. VREF Limiter MOD Compressor Expander LIML R3 R5 R7 R4 R6 R8 MODL CPDL SGO MODL DC voltage input pin used to define a transmit output level for MODEM. One of the voltages into which the voltage between VREF pin and SGO pin is divided by the resistors should be supplied to this pin. Refer to the VREF description for voltage division by the resistors. If the potential difference between this pin and the SGO pin is VMODL (V), the TAO output level is expressed as follows. VOX = 20 · log (VMODL) + 0.5 (dBV) GND Ground pin (0V). LIML Clamp voltage input pin for deviation limiter. The voice signal maximum RF modulation can be controlled by supplying, to this pin, one of the voltages into which the voltage between VREF pin and SGO pin is divided by the resistors. Refer to the VREF description for voltage division by the resistors. If the potential difference between this pin and the SGO pin is VLIML (V), the limiter level is expressed as follows. VLIML = 20 · log (VLIML) – 3.0 (dBV) 7/21 ¡ Semiconductor MSM7532 The DC clamp level is VSG ±VLIML. LIML + – Inverter Limiter From LPF1 To splatter filter CPDL Input DC voltage reference level definition pin for compander. One of the voltages into which the voltage between VREF pin and SGO pin is divided by the resistors should be supplied to this pin. Refor to the VREF description for voltage division by the resistors. If the potential difference between this pin and the SGO pin is VCPDL, the compressor and expander input reference levels are expressed as follows. VICS = VIES = 20 · log (VCPDL) – 5.8 (dBV) The compressor input reference level and expander input reference level change simultaneously. SGI Built-in signal ground that is reference voltage to be supplied to analog circuit. The DC voltage is one half of the supply voltage. When the power has fewer noises and fewer ripples, the idle noise can be improved by inserting a bypass capacitor over 1 mF between SGI and GND, and between SGI and VDD. If the power has a lot of noises, do not insert a bypass capacitor between SGI and VDD to reduce supply noises. Other capacitors and resistors should be connected to the SGO pin. SGO Signal ground voltage output pin for LSI external circuits. The DC voltage is one half of the supply voltage. Insert a 1 mF capacitor between SGO and GND. VDD To internal circuit C2 SGI SG voltage generation circuit C3 + – SGO C25 BR MODEM data signaling rate switching input. BR Data Signaling Rate 0 1200 bps 1 2400 bps Note SW8 CE3P, CE3N Pins used to connect a capacitor for defining a time constant of output transient response for the expander. Insert a 0.22 mF capacitor between CE3N and CE3P. 8/21 ¡ Semiconductor MSM7532 CE1, CE2 Pins used to connect a capacitor for removing DC offset in the expander. Insert a 0.22 mF capacitor between CE1 and SGO, an 1 mF capacitor between CE2 and SGO. EMP Emphasis path selection pin. EMP Receive side Transmit side 0 Pre-emphasis circuit is bypassed to the path De-emphasis circuit is bypassed to the path 1 Pre-emphasis circuit is connected to the path De-emphasis circuit is connected to the path Note SW2 RAIO, RAI Pins used to constitute RC-active filter on the receive signal input side. Refer to the TVIO and TVI description. If the Scrambler circuit is used, using the first order RC-active filter is recommended. In this case, configure the filter so that either R34 or R35, or both of them, is 60 kW or less. <First order RC-active filter configuration> C27 C19 R34 RAIO R35 RAI In the case of fc = 10 kHz, gain : 0dB – + VRAI R34 = R35 = 51 kW C19 = 0.22 mF, C27 = 300 pF RVO Receive voice signal output pin. The RVO state is controlled depending on the digital data set to RVE. RVO RVE Note 0 No signal output (voltage = VSG) 1 Output of signals input to RAI and RAIO SW7 VOL1, VOL2 Pins used to set up a gain for the electronic volume. The volume at the stage next to expander is controlled by the pins. VOL2 VOL1 Gain 0 1 +6 dB 0 0 0 dB 1 1 –6 dB 1 0 –12 dB CSH Pin used to connect a capacitor for removing DC offset in shaper of modem receiver. Insert a 1 mF capacitor between this pin and GND. 9/21 ¡ Semiconductor MSM7532 RVBU Ceramic receiver amplifier input pin. Refer to the RCN, RCP description. RCP, RCN Ceramic receiver amplifier output pins. R16 RCN – + Ceramic receiver (Equivalent capacitance : 68 nF) RCP C29 R17 R18 RVBU – + R19 RVO RC LPF R16 = R17 = 1.5 kW R18 ≥ 10 kW C29 is a capacitor for oscillation prevention. Be sure to use a capacitor of 20 pF or more. If no ceramic receiver amplifier is used, RVBU should be directly connected to RCP, RCN be open, and R16 to R19, and C29 be removed. PDRC Pin used to control power down of the ceramic receiver amplifier. If digital "1" is input in this pin, the two ceramic receiver amplifiers are powered down. If the LSI is in power-down mode 1 or 2 (PDN = "1", RVE = "0"), the ceramic receiver amplifiers are powered down even when the PDRC is at "0". X1, X2 Crystal oscillator connection pins. 3.6864 MHz crystal oscillator should be connected. If the load capacitance of the crystal oscillator is 16 pF, insert a 12 pF capacitor between X1 and GND and between X2 and GND. If an external clock is used, with X1 opened, the clock should be input from X2 through a 200 pF capacitor. High-speed CMOS or TTL, etc C21 X2 3.6864 MHz X2 200 pF C22 3.6864 MHz X1 Open X1 10/21 ¡ Semiconductor MSM7532 SD Transmit data input pin. The data on the SD pin is accepted as the modulator input signals in synchronization with the rising edges of ST. ME SD Input tMS ST Modulator Input Data At the start of data transmission, the synchronization with the receive modem is required. Therefore bit synchronous signals (the alternating patterns of "1" and "0") more than 18 bits should be input in SD. If a radio transmission path is better in S/N ratio, the receive section can properly operate with bit synchronous signals more than 11 bits. FD Frame synchronous detection signal output pin. If the contents of received data in the LSI matches the patterns defined by FPS and BIT in a state where FDE is at "1" level, FD holds "1" level. If FDE is at"0" level, FD is fixed at "0" level. FD is also fixed at "0" in power-down mode 1 or 2 (PDN = "1", RVE = "0"). Take the following procedure to detect frame synchronization: (1) Set the synchronous patterns to be detected at BIT and FPS. (2) Drive FDE at "0" level for 1 ms or more, and then at "1" level. FD is reset to "0" and RT and PD are fixed at "1" level. (3) When a frame synchronous signal has been detected, FD is driven at "1" level and RT and RD become active. To ensure detection of frame synchronous signals, lock in PLL of the receive modem. At the beginning of transmission, transmit synchronous patterns after synchronizing with the opposite modem using a bit synchronous signal of 18 bits or more. Refor to "Receiver Signal Timing" in Fig. 3. RD Receive data output pin. Outputs demodulation serial data for receive signals. Since the RD data is output in synchronization with the falling edges of re-generated timing clock pulse RT, it is recommended that the data be latched on the rising edge of RT. If FDE is at "1" level and FD is at "0" level, RD remains set at "1" level. 11/21 ¡ Semiconductor MSM7532 RT Receive data timing re-generation clock output pin. Outputs synchronous clock re-generated by built-in PLL. The data from RD and signals from FD are output in synchronization with falling edges of signals from the RT pin. If FDE is at "1" level and FD is at "0" level, RD remains set at "1" level. Refer to "Receive Signal Timing" in Fig. 3. VDD Power supply pin. A bypass capacitor more than 10 mF should be inserted between this pin and GND. BIT Bit synchronous signal detector control input pin. The FD pin goes to "1" level when the BIT pin and FDE pin are at "1" level, and a 4-bit synchronous signal and 16-bit frame synchronous signal are successively detected. The FD pin goes to "1" level when the BIT pin is at "0" level and the FDE pin is at "1" level, and a 16bit frame synchronous signal is detected. Refer to the FPS description. FPS Frame synchronous pattern setup input pin. BIT FPS 0 0 1001 0011 0011 0110 ( = 9336H) Detection Pattern Receiver Handset 0 1 1100 0100 1101 0110 ( = C4D6H) Base station 1 0 1010 1001 0011 0011 0110 ( = A9336H) Handset 1 1 1010 1100 0100 1101 0110 ( = AC4D6H) Base station (These synchronous patterns are for Japanese cordless telephones.) RCK1, RCK2, SEC Reverse frequency selection pins of voice scrambler. These pins are also used to select filter and scrambler bypass mode. SEC PCK1 PCK2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 RCK1 RCK2 Transmit side Receive side Note Pre-BPF, SCR and LPF1 are bypassed DE-SCR and LPF2 are bypassed SW4 Pre-BPF and LPF1 are connected but Scrambler circuit (SCR) is bypassed LPF2 is connected but De-scrambler (DE-SCR) is bypassed SW3 Pre-BPF, SCR and LPF1 are bypassed DEM-BPF output is connected to RVO pin via RC-LPF (for IC test) Scrambler works De-scrambler circuit works SW4 SW9 SW3 SW4 Reverse freq. 0 1 3200 Hz 1 0 3291 Hz 1 1 3388 Hz 12/21 ¡ Semiconductor MSM7532 ME Pin used to control MSK modulator output. If digital "1" is entered to this pin, MSK modulator output is connected to splatter filter input. Refer to the TAO description. If digital "1" is entered to the ME pin and digital "0" to the PDN, RVE and TVE pins, the voice signal processing system is powered down. Refer to the PDN pin description. ST Transmit data timing clock output pin. Signals on the SD pin are accepted in synchronization with the leading edges of the signals from the ST pin. If ME is at "0" level, ST remains set at "1" level. 13/21 ¡ Semiconductor MSM7532 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage VDD Analog Input Voltage *1 VIA Digital Input Voltage *2 VID Condition Rating Unit –0.3 to 7 Ta = 25°C Referred to GND –0.3 to VDD+0.3 Operating Temperature Top — –30 to +70 Storage Temperature TSTG — –55 to +150 V °C *1: TVI, MICN, MICP, CMPI, UAI, MODL, LIML, CPDL, RAI, RVBU *2: TVE, RVE, PDN, FDE, BYP, BR, EMP, VOL1, VOL2, PDRC, X2, SD, BIT, FPS, RCK1, RCK2, SEC, ME RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min Typ Max Power Supply Voltage VDD Referred to GND +1.8 +2.4 +5.5 V Operating Temperature Top — –30 +25 +70 °C Data Signaling Rate Ts BR = "0" — 1200 — BR = "1" — 2400 — — — –6 Analog Signal Input Level VIA — — 0 MODL 0.05 0.25 LIML 0.1 0.25 CPDL 0.1 0.25 TVIO, VDD = 2.1 V to 5.5 V RAIO level VDD = 4.5 V to 5.5 V VMODL DC Input Range VLIML Referred to VSG VCPDL Unit bit/sec dBV 1 V 3 DD –0.2 1 V 2 DD –0.3 0.5 Microphone Amplifier Common Mode Input Voltage Range VIM MICN, MICP 0.85 — VDD –0.8 C2, C3, C13, C15, C25 — — — 1.0 — C10, C11, C12, C14, C16 C4 — — — — — — 0.22 0.1 — — C20 — — — 10 — C21, C22 — — — 12 — C28, C29 — — 20 — — V mF pF Frequency — — — 3.6864 — Freq, Tolerance — 25 ±5°C –100 — 100 Crystal Temp, Coefficient — –30 to 70°C –100 — 100 Resonator Equivalent — — — — 100 W — — — 16 — pF Series Resistance Load Capacitance MHz ppm 14/21 ¡ Semiconductor MSM7532 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics Parameter Power Supply Current *1 Input Leakage Current *2 (VDD = 2.1 V to 5.5 V, Ta = –30 to 70°C) Symbol Condition Min Typ Max IDD Normal mode 2.4 V (mode 5) 5.5 V — 10 17 — 16 33 IDDS1 Power Down mode 1 5.5 V — 1.0 50 IDDS2 Power Down mode 2 — 120 220 IDDS3 Power Down mode 3 2.4 V — 5.3 9.2 IDDS4 Power Down mode 4 — 6.0 10.5 –5.0 — 5.0 IIL VIN = 0 V IIH VIN = VDD VIL Input Voltage *2 — VIH Output Voltage *3 0 — 0.2VDD 0.8VDD — VDD VOL IOL = –20 mA 0 — 0.1 VOH IOH = 20 mA VDD–0.1 — VDD Unit mA mA mA mA V *1: Refer to PDN in the PIN AND FUNCTIONAL DESCRIPTIONS. *2: TVE, RVE, PDN, FDE, BYP, BR, EMP, VOL1, VOL2, PDRC, SD, BIT, FPS, RCK1, RCK2, SEC, ME *3: FD, RD, RT, ST MODEM AC Characteristics Parameter Transmit Carrier Frequency Transmit Carrier Level (VDD = 2.1 V to 5.5 V, Ta = –30 to 70°C) Symbol *1 Max SD = "1" BR = "0" 1199 1200 1201 SD = "0" ME = "1" 1799 1800 1801 fM2 SD = "1" BR = "1" 1199 1200 1201 fS2 SD = "0" ME = "1" 2399 2400 2401 VOX BER 2400 bps Number of PLL Lock-in data bits Typ fS1 1200 bps Bit Error Rate Min fM1 VIR Receive Carrier Level Condition –30 — –3 VDD = 4.5 V to 5.5 V –30 — +4 — 8 dB — 1 ¥ 10–3 10 dB — 5 ¥ 10–5 — 11 dB — 1 ¥ 10–3 — 13 dB — 5 ¥ 10–5 — — — 18 Number of data bits required for the PLL to be Locked in within the phase difference of 22.5˚ or less BN Hz –12.7 –11.5 –10.3 R5 = R6 VDD = 2.1 V to 5.5 V S/N values measured at RAIO Unit dBV — bit Number of data bits required for the PLL to be Locked in within the phase difference of 90˚ or less — — 11 *1: In the case where receive MSK signals are bit synchronous signals (modulated signals with the alternating pattern of "0" and "1") 15/21 ¡ Semiconductor MSM7532 Voice Signal Processing Characteristics Parameter (VDD = 2.1 V to 5.5 V, Ta = –30 to 70°C) Symbol VLIM Condition R3 = R4, VDD = 2.4 V Min –16 Typ –15 Max –14 Transmit Output Distortion HDT –48 –40 HDR fIN = 1 kHz, –18 dBV BYP = EMP = "0", R7 = R8 — Receive Output Distortion — –45 –38 BYP = EMP = "0" R7 = R8 — –62 –52 — –80 — BYP = EMP = "0" fIN = 1 kHz, –15 dBV — –60 –50 — –90 — SEC = "0" –1.5 0 +1 SEC = "1" –1.5 0 +1 SEC = "0" –1.5 0 +1 SEC = "1" –1.5 0 +1 3200 Hz 3197 3200 3203 3291 Hz 3288 3291 3294 3388 Hz 3385 3388 3391 No signal input BYP = RCK2 = "0" SEC = RCK1 = "1" R7 = R8 — –88 –60 — –110 — fIN = 1 kHz, –15 dBV BYP = RCK2 = "0" SEC = RCK1 = "1", R7 = R8 — –55 –48 — –55 –48 — –28 –23 Limiter Clamp Level Transmit Idle Noise NIT Receive Idle Noise NIR Crosstalk (Receive to transmit) CTT (Transmit to receive) CTR Transmit Gain Receive Gain GT1 GT2 GR1 fIN = 1 kHz BYP = "1" GR2 Reverse Frequency of Voice Scrambler fR Transmit Reverse Frequency Leak Level LRT Receive Reverse Frequency Leak Level LRR Transmit Input Signal Leak Level LIT Receive Input Signal Leak Level LIR Common to transmit and receive FT1 Transmit Filter FT3 300 Hz –12.5 –10.5 –8.5 2.5 kHz +6.5 +8.0 +9.5 3 kHz +7 +9 +11 5 kHz — –32 –27 100 Hz +1.0 +2.5 +4.0 300 Hz +7.5 +9.0 +10.5 FT50 FR1 FR3 Receive Filter 100 Hz FR25 EMP = "1" BYP = "1" SEC = "0" RCK1 = "0" RCK2 = "0" Reference = 1 kHz dB dBV dB Hz dBV FT25 FT30 Unit dBV 2.5 kHz –9.5 –8.0 –6.5 FR30 3 kHz –11.5 –9.5 –7.5 FR50 5 kHz — –35 –30 dB 16/21 ¡ Semiconductor MSM7532 Voice Signal Processing Characteristics (Continued) Parameter Ceramic Receiver Amplifier (RCP, RCN) UserAvailable Amplifier (UAO) Symbol Output Resistance ROC Output Load Resistance RLC Receiver Equivalent Capacitance CCR Output Level VCR Output Distortion HDC Output Resistance ROU Output Load Resistance RLU Output Level VOU Output Distortion Ratio Input Reference Level HDU VICS GC2 Compressor Expander (VDD = 2.1 V to 5.5 V, Ta = –30 to 70°C) Condition Min Typ Max Unit — 40 — W 1.35 1.5 — kW — 68 75 nF fIN = 1 kHz, Distortion Ratio £ –30 dB, VDD = 2.4 V — — –4 dBV fIN = 1 kHz, –18 dBV — –68 –45 dB — 40 — W 2 — — kW — — –6 — — 0 — — Distortion Ratio VDD = 2.1 V to 5.5 V £ –30 dB VDD = 4.5 V to 5.5 V fIN = 1 kHz, –18 dBV fIN = 1 kHz, R7 = R8 –20 dB fIN = 1 kHz, R7 = R8 –10.7 –10 –9.3 –40 dB –21.2 –20 –18.8 –60 dB — — –30 3.0 — — — 16 — Output Level *1 GC4 Attack Time GC6 TAT1 Recovery Time TRE1 Input Level, –34 dBV Æ –22 dBV Input Level, –22 dBV Æ –34 dBV Input Reference Level VIES fIN = 1 kHz, R7 = R8 Maximum Input Level VIEM1 VIEM2 R7 = R8 GE2 — — –15 VDD = 4.5 V to 5.5 V — — –12 –10 dB –21.5 –20 –18.5 –20 dB –42.2 –40 –37.8 Attack Time GE25 TAT2 –25 dB — — –50 3.0 — — Recovery Time TRE2 — 16 — GEV1 Electronic Volume Gain GEV2 +6 dB +5.5 +6.0 +6.5 –6 dB –6.5 –6.0 –5.5 GEV3 –12 dB –12.5 –12.0 –11.5 fIN = 1 kHz, R7 = R8 Input Level, –26 dBV Æ –20 dBV Input Level, –20 dBV Æ –26 dBV VOL1 = VOL2 = "0" Referenced to RVO level at "0" dB dBV dB ms –19.8 –17.8 –15.8 VDD = 2.1 V to 5.5 V GE1 Output Level *1 — –64 –45 –19.8 –17.8 –15.8 dBV dBV dB ms dB *1: 0 dB is defined as the input level and the output level when the standard input level is input. 17/21 ¡ Semiconductor MSM7532 Common Characteristics (VDD = 2.1 V to 5.5 V, Ta = –30 to 70°C) Symbol Condition Min Typ Max Unit Input Resistance RIA *1 — 10 — MW Output Resistance ROX fO £ 4 kHz, *2 — 200 — W 10 — — 40 — — 12 — — VDD = 2.1 V to 5.5 V — — –6 VDD = 4.5 V to 5.5 V — — 0 0.45 0.5 0.55 Parameter Output Load Resistance RLX1 Output Level: less than –12 dBV RLX2 Output Level: within the range of V01 and V02 VREF, SGO RLX3 Analog Signal Output Level V01 V02 *3 RLX2 = 40 kW*3 kW dBV VREF Output DC Voltage VRF With respect to VSG SG Output DC Potential VSG SGO, SGI VDD/2 VDD/2 VDD/2 –0.1 +0.1 Analog Output DC Potential VAO TAO, RVO VDD/2 VDD/2 VDD/2 –0.15 +0.15 V *1: On TVI, MICN, MICP, UAI, MODL, LIML, CPDL, RAI, RVBU *2: On TVIO, MICO, TAO, RAIO, RVO *3: When the distortion ratio is less than or equal to –30 dB on TVIO, MICO, TAO, RAIO, RVO Digital Timing Characteristics Parameter (VDD = 2.1 V to 5.5 V, Ta = –30 to 70°C) Symbol Condition Min Typ Max 1 — — 1 — — Unit Data Setup Time tS Data Hold Time tH Receive Data Output (RTÆRD, FD) tD Refer to Fig. 2 –300 — 300 ns Synchronous Signal Output (MEÆST) tMS Refer to SD pin description 0 — 834 ms Refer to Fig. 1 ms 18/21 ¡ Semiconductor MSM7532 TIMING DIAGRAM ST 50% SD 50% tS tH Figure 1 Input Data Timing RT 50% FD, RD 50% tD Figure 2 Output Data Timing FDE RT Internal RD N-2 N-1 N D1 D2 D3 D1 D2 D3 FD RD N-2, N-1, N : Frame synchronous signal Figure 3 Receive Signal Timing 19/21 ¡ Semiconductor MSM7532 C21 SD Receive Data RD Receive Timing Re-generation Clock RT C16 R35 CE3P CE1 EMP CE2 C27 RAIO RAI RVO VOL2 VOL1 + – C13 CSH RVBU C15 C14 R34 C19 Emphasis Selection Receive Signal Input Electronic Volume Control R19 R18 R17 BR MODEM Signaling Rate Swiching SGO FD C2 R4 SGI CPDL VDD R8 R6 C3 LIML GND BIT R3 MODL FPS R7 R5 VREF RCK2 CC2 RCK1 CC1 SEC C12 TAO UAI UAO CMPI MICP C10 C11 R24 Microphone C28 C1 Transmit Signal Output R1 R2 C9 R14 C24 R15 R12 R23 C23 C8 R13 R10 VDD C5 C6 C7 C4 MICN MICO BYP Compander Bypass Control R11 R9 TVI FDE Frame Synchronous Detection Control TVIO PDN CC3P Power Down Control ST RVE CC3N Receive Voice Output Control ME TVE + – VDD Transmit Voice Output Control Power Supply Scrambler and Bypass Switching MSK Modulator Control Transmit Data Timing Clock CE3N X2 Transmit Data Frame Synchronous Detection Output C20 Bit Synchronous Detection Control Synchronous Pattern Setup Input Reverse Frequency Select RCP X1 RCN C22 PDRC C29 R16 Ceramic Receiver Receiver Amplifier Power-Down Control APPLICATION CIRCUIT Note: An arrow mark ( ) indicates connection to the SGO pin. 20/21 C25 ¡ Semiconductor MSM7532 PACKAGE DIMENSIONS (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 21/21