3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module HYS64(72)V4200GU HYS64(72)V8220GU PC66 & PC100 168 pin unbuffered DIMM Modules • 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications • One bank 4M x 64, 4Mx72 and two bank 8M x 64, 8M x 72 organisation • Optimized for byte-write non-parity and ECC applications • JEDEC standard Synchronous DRAMs (SDRAM) • Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification • SDRAM Performance: • fCK Clock frequency (max.) tAC Clock access time -8 -8B -10 Units 100 100 66 MHz 6 6 8 ns Programmed Latencies : Product Speed CL tRCD tRP -8 PC100 2 2 2 -8B PC100 3 2 3 -10 PC66 2 2 2 • Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E2PROM • Utilizes 4M x16 SDRAMs in TSOPII-54 packages • 4096 refresh cycles every 64 ms • 133,35 mm x 29,31 mm x 4,00 mm card size with gold contact pads Semiconductor Group 1 8.98 HYS64(72)V4200/8220GU SDRAM-Modules The HYS64(72)V4200 and HYB64(72)V8220 are an industry standard 168-pin 8-byte Dual in-line Memory Module (DIMM) which are organised as 4M x 64, 4M x 72 in an one bank and 8M x 64, 8M x72 in two banks high speed memory arrays designed with 64Mbit Synchronous DRAMs (SDRAMs Die Rev.B) for non-parity and ECC application. The DIMMs use -8 and -8B speed sort 4M x 16 SDRAM devices in TSOP54 packages to meet the PC100 requirements and -10 parts for 66 MHz bus speed applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s module specification. The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint, with t.d.b. height. Ordering Information Type Ordering Code Package Descriptions Module Height HYS 64V4200GU-8 PC100-222-620 L-DIM-168-31 100 Mhz 4M x 64 1 bank SDRAM module 1,15” HYS 72V4200GU-8 PC100-222-620 L-DIM-168-31 100 MHz 4M x 72 1 bank SDRAM module 1,15” HYS 64V8220GU-8 PC100-222-620 L-DIM-168-31 100 Mhz 8M x 64 2 bank SDRAM module 1,15” HYS 64V8220GU-8 PC100-222-620 L-DIM-168-31 100 MHz 8M x 72 2 bank SDRAM module 1,15” HYS 64V4200GU-8B PC100-323-620 L-DIM-168-31 100 Mhz 4M x 64 1 bank SDRAM module 1,15” HYS 64V8220GU-8B PC100-323-620 L-DIM-168-31 100 Mhz 8M x 64 2 bank SDRAM module 1,15” HYS 64V4200GU-10 PC66-222-620 L-DIM-168-31 66 Mhz 4M x 64 1 bank SDRAM module 1,15” HYS 72V4200GU-10 PC66-222-620 L-DIM-168-31 66 MHz 4M x 72 1 bank SDRAM module 1,15” HYS 64V8220GU-10 PC66-222-620 L-DIM-168-31 66 Mhz 8M x 64 2 bank SDRAM module 1,15” HYS 64V8220GU-10 PC66-222-620 L-DIM-168-31 66 MHz 8M x 72 2 bank SDRAM module 1,15” Pin Names A0-A11 BA0 , BA1 DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0, CKE1 Address Inputs CLK0 - CLK3 (RA0~ RA11 / CA0 ~ CA7, CA10) Bank Select DQMB0 - DQMB7 Data Input/Output CS0 - CS3 Check Bits (x 72 organisation Vcc only) Row Address Strobe Vss Column Address Strobe SCL Read / Write Input SDA Clock Enable N.C. / DU Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Pres. Detect No Connection Address Format: 4M x 64 4M x 72 8M x 64 8M x 72 Part Number HYS64V4200GU HYS72V4200GU HYS64V8220GU HYS72V8220GU Semiconductor Group Rows 12 12 12 12 Columns 8 8 8 8 2 Bank Select 2 2 2 2 Refresh 4k 4k 4k 4k Period 64 ms 64 ms 64 ms 64 ms Interval 15,6 µs 15,6 µs 15,6 µs 15,6 µs HYS64(72)V4200/8220GU SDRAM-Modules Pin Configuration PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC (CB0) NC (CB1) VSS NC NC VCC WE DQMB0 DQMB1 CS0 DU VSS A0 A2 A4 A6 A8 A10 BA1 VCC VCC CLK0 PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol PIN # VSS DU CS2 DQMB2 DQMB3 DU VCC NC NC NC (CB2) NC (CB3) VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Note : Pinnames in brackets are for the x72 ECC versions Semiconductor Group 3 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC (CB4) NC (CB5) VSS NC NC VCC CAS DQMB4 DQMB5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 NC VCC CLK1 NC PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS CKE0 CS3 DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC HYS64(72)V4200/8220GU SDRAM-Modules CS0 CS CS DQMB0 LDQM DQMB4 LDQM DQ(7:0) DQ0-DQ7 DQ32-DQ39 DQ0-DQ7 DQMB1 UDQM DQMB5 UDQM DQ(15:8) DQ8-DQ15 DQ40-DQ47 DQ8-DQ15 D0 D2 CS LDQM CB(7:0) DQ0-DQ7 Vcc UDQM DQ8-DQ15 D4 CS2 CS CS DQMB2 LDQM DQMB6 LDQM DQ(23:16) DQ0-DQ7 DQ(55:48) DQ0-DQ7 DQMB3 UDQM DQMB7 UDQM DQ(31:24) DQ8-DQ15 DQ(63:56) DQ8-DQ15 D1 D3 E2PROM (256wordx8bit) A0-A11, BA0, BA1 D0 - D3, (D4) VCC D0 - D3, (D4) SA0 SA1 SA2 SCL C VSS D0 - D3, (D4) RAS, CAS, WE D0 - D3, (D4) CKE0 CLK1,CLK3 D0 - D3, (D4) CLK0 CLK1 CLK2 CLK3 10 pF SA0 SA1 SA2 SCL SDA WP 47k Clock Wiring 4M x 64 4M x 72 2 SDRAM+15pF 3 SDRAM+10pF Termination Termination 2 SDRAM+15pF 2 SDRAM+15pF Termination Termination notes: 1) all resistors are 10 Ohms 2) D4 is only used in the x72 ECC version 3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous board layout to obtain minimum DQ trance length Block Diagram for 4M x 64 and 4M x 72 1 bank SDRAM DIMM modules (HYS64V4200GU) Semiconductor Group 4 HYS64(72)V4200/8220GU SDRAM-Modules CS0 CS1 CS CS CS CS DQMB0 LDQM LDQM DQMB4 LDQM LDQM DQ(7:0) DQ0-DQ7 DQ0-DQ7 DQ(39:32) DQ0-DQ7 DQ0-DQ7 DQMB1 UDQM UDQM DQMB5 UDQM UDQM DQ(15:8) DQ8-DQ15 DQ8-DQ15 D0 D4 DQ(47:40) DQ8-DQ15 DQ8-DQ15 D6 D2 CS CS CB(7:0) LDQM LDQM DQ0-DQ7 DQ0-DQ7 UDQM UDQM Vcc Vcc DQ8-DQ15 DQ8-DQ15 D9 D8 CS2 CS3 CS CS CS CS DQMB2 LDQM LDQM DQMB6 LDQM LDQM DQ(23:16) DQ0-DQ7 DQ0-DQ7 DQ(55:48) DQ0-DQ7 DQ0-DQ7 DQMB3 UDQM UDQM DQMB7 UDQM UDQM DQ(31:24) DQ8-DQ15 DQ8-DQ15 D1 D5 DQ(63:56) DQ8-DQ15 DQ8-DQ15 D7 D3 E2PROM (256wordx8bit) A0-A11, BA0, BA1 D0 - D7, (D8,D9) VCC D0 - D7, (D8,D9) SA0 SA1 SA2 SCL C VSS SA0 SA1 SA2 SCL SDA WP 47k D0 - D7, (D8,D9) RAS, CAS, WE D0 - D7, (D8,D9) CKE0 Clock Wiring 8M x 64 8M x 72 D0 - D3, (D8) CLK0 CLK1 CLK2 CLK3 VDD 10k CKE1 D4 - D7,(D9) 2 SDRAM+15pF 2 SDRAM+15pF 2 SDRAM+15pF 2 SDRAM+15pF 3 SDRAM+10pF 3 SDRAM+10pF 2 SDRAM+15pF 2 SDRAM+15pF notes: 1) all resistors are 10 Ohms 2) D8 & D9 are only used in the x72 ECC version 3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous board layout to obtain minimum DQ trance length Semiconductor Group 5 HYS64(72)V4200/8220GU SDRAM-Modules DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values Unit min. max. Input high voltage VIH 2.0 Vcc+ 0.3 V Input low voltage VIL – 0.5 0.8 V Output high voltage (IOUT = – 2.0 mA) VOH 2.4 – V Output low voltage (IOUT = 2.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 10 10 µA Output leakage current (DQ is disabled, 0 V < VOUT < VCC) IO(L) – 10 10 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit max. 4M x 72 max. 8M x 72 Input capacitance (A0 to A11, RAS, CAS, WE) CI1 tbd. tbd. pF Input capacitance (CS0 -CS3, ) CI2 tbd. tbd. pF Input capacitance (CLK0 - CLK3) CICL tbd. tbd. pF Input capacitance (CKE0, CKE1) CI3 tbd. tbd. pF Input capacitance (DQMB0 - DQMB7) CI4 tbd. tbd. pF Input / Output capacitance CIO tbd. tbd. pF Input Capacitance (SCL,SA0-2) Csc 8 8 pF Input/Output Capacitance Csd 10 10 pF (DQ0-DQ63,CB0-CB7) Semiconductor Group 6 HYS64(72)V4200/8220GU SDRAM-Modules Operating Currents (TA = 0 to 70oC, Vdd = 3.3V ± 0.3V 1) (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. -8/-8B -10 Note max. OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) tck = min. tck = Infinity tck = min. tck = Infinity ICC1 130 90 mA 1 ICC2P 2 2 mA 1 ICC2PS 1 1 mA 1 ICC2N 35 30 mA 1 ICC2NS 5 5 mA 1 NO OPERATING CURRENT CKE>=VIH(min.) ICC3N 45 40 mA 1 tck = min., CS = VIH(min), active state ( max. 4 banks) CKE<=VIL(max.) ICC3P 8 8 mA 1 ICC4 100 70 mA 1,2 ICC5 130 90 mA 1 ICC6 1 1 mA 1 BURST OPERATING CURRENT tck = min., Read command cycling AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V Semiconductor Group standard version 7 HYS64(72)V4200/8220GU SDRAM-Modules AC Characteristics 3)4) TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Limit Values Symbol -8 PC100-222 Unit -8B PC100-323 Note -10 PC66 min. max. min. max. min. max. Clock and Clock Enable Clock Cycle Time tCK CAS Latency = 3 CAS Latency = 2 10 10 – – 10 12 – – 10 15 – – System Frequency fCK CAS Latency = 3 CAS Latency = 2 – – 100 100 – – 100 83 – – 100 66 Clock Access Time tAC CAS Latency = 3 CAS Latency = 2 – – 6 6 – – 6 7 – – 8 9 ns ns 4,5) Clock High Pulse Width tCH 3 – 3 – 3.5 – ns 6) Clock Low Pulse Width tCL 3 – 3 – 3.5 – ns 6) Input Setup time tCS 2 – 2 – 3 – ns 7) Input Hold Time tCH 1 – 1 – 1 – ns 7) CKE Setup Time tCKSP 2.5 – 2.5 – 3 – ns 8) tCKSR 8 – 10 – 8 – ns 9) tT 1 – 1 – 1 – ns RAS to CAS delay tRCD 20 – 20 – 30 – ns Precharge Time tRP 20 – 30 – 30 – ns Active Command Period tRAS 50 100k 60 100k 70 Cycle Time tRC 70 – 80 – 80 – ns Bank to Bank Delay Time tRRD 16 – 20 – 20 – ns CAS to CAS delay time (same bank) tCCD 1 – 1 – 1 – CLK ns ns MHz MHz (Power down mode) CKE Setup Time (Self Refresh Exit) Transition time (rise and fall) Common Parameters Semiconductor Group 8 100k ns HYS64(72)V4200/8220GU SDRAM-Modules Parameter Limit Values Symbol -8 PC100-222 -8B PC100-323 Unit Note -10 PC66 min. max. min. max. min. max. Refresh Cycle Refresh Period (4096 cycles) tREF – 64 – 64 – 64 ms 8) Self Refresh Exit Time tSREX 10 – 10 – 10 – ns 9) Data Out Hold Time tOH 3 – 3 3 – ns 4) Data Out to Low Impedance tLZ 0 – 0 0 – ns Data Out to High Impedance tHZ 3 8 3 10 3 10 ns DQM Data Out Disable Latency tDQZ – 2 – 2 – 2 CLK tDPL 2 – 2 – 2 – CLK Data In to Active/refresh tDAL 5 – 5 – 5 – CLK DQM Write Mask Latency tDQW 0 – 0 – 0 – CLK Read Cycle Write Cycle Data input to Precharge (write recovery) Semiconductor Group 9 10) HYS64(72)V4200/8220GU SDRAM-Modules Notes: 1. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8 and -8B and at 66 MHz for -10 modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. All values are shown per memory component. 2. These parameters are measured with continous data stream during read access and all DQ toggling. CL=3 and BL=4 assumed and the VDDQ current is excluded. 3. All AC characteristics are shown for device level. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit show. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. tCH + 1.4 V 2.4 V CLOCK 50 Ohm 0.4 V tCL tSETUP tT Z=50 Ohm tHOLD I/O 50 pF 1.4V INPUT tAC tAC tLZ I/O tOH 50 pF 1.4V OUTPUT Measurement conditions for tac and toh tHZ fig.1 5. If clock rising time is longer than 1ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5 V 7. If tT is longen than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up“ the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10.Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. Semiconductor Group 10 HYS64(72)V4200/8220GU SDRAM-Modules A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) SPD-Table for PC100 modules: Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Description Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for 16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-toback random column address Burst Length supported SPD Entry Value 128 256 SDRAM 12 4Mx64 4Mx64 4Mx72 8Mx64 8Mx64 8Mx72 -8 -8B -8 -8 -8B -8 80 80 80 80 80 80 08 08 08 08 08 08 04 04 04 04 04 04 0C 0C 0C 0C 0C 0C 8 08 08 08 08 08 08 1/2 64 0 LVTTL 10.0 ns 6.0 ns 01 40 00 01 A0 60 01 40 00 01 A0 60 01 48 00 01 A0 60 02 40 00 01 A0 60 02 40 00 01 A0 60 02 48 00 01 A0 60 none Self-Refresh, 15.6µs x16 n/a / x8 00 80 00 80 02 80 00 80 00 80 02 80 10 00 10 00 10 08 10 00 10 00 10 08 tccd = 1 CLK 01 01 01 01 01 01 8F 8F 8F 8F 8F 8F 04 06 01 01 00 04 06 01 01 00 04 06 01 01 00 04 06 01 01 00 04 06 01 01 00 04 06 01 01 00 06 06 06 06 06 06 A0 C0 A0 A0 C0 A0 60 70 60 60 70 60 FF FF FF FF FF FF FF FF FF FF FF FF 14 1E 14 14 1E 14 1, 2, 4, 8 & full page Number of SDRAM banks 4 Supported CAS Latencies CL = 2 & 3 CS Latencies CS latency = 0 WE Latencies WL = 0 SDRAM DIMM module attributes non buffered/ non reg. SDRAM Device Attributes :Gene- Vcc tol +/- 10% ral Minimum Clock Cycle Time at 10.0 / 12.0ns CAS Latency = 2 Maximum data access time from 6.0 / 7.0ns Clock for CL=2 Minimum Clock Cycle Time at CL not supported =1 Maximum Data Access Time not supported from Clock at CL=1 Minimum Row Precharge Time 20 / 30 ns Semiconductor Group Hex 11 HYS64(72)V4200/8220GU SDRAM-Modules Byte# Description 28 Minimum Row Active to Row Active delay tRRD 29 Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 62-61 Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information (optio125 nal) (FFh if not used) 126 Max. Frequency Specification 127 100 Mhz support details 128+ Unused storage locations Semiconductor Group SPD Entry Value Hex 4Mx64 4Mx64 4Mx72 8Mx64 8Mx64 8Mx72 -8 -8B -8 -8 -8B -8 10 14 10 10 14 10 16 ns 20 ns 14 14 14 14 14 14 45 ns 32 MByte 2 ns 1 ns 2 ns 1 ns 2D 08 20 10 20 10 FF 2D 08 20 10 20 10 FF 2D 08 20 10 20 10 FF 2D 08 20 10 20 10 FF 2D 08 20 10 20 10 FF 2D 08 20 10 20 10 FF Revision 1.2 12 D7 XX 12 15 XX 12 E9 XX 12 D8 XX 12 16 XX 12 EA XX 100 MHz 64 AF FF 64 AD FF 64 AF FF 64 FF FF 64 FD FF 64 FF FF 12 HYS64(72)V4200/8220GU SDRAM-Modules SPD-Table for PC66 modules: Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 16 SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported 17 18 19 20 21 Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes 22 23 SDRAM Device Attributes :General Minimum Clock Cycle Time at CAS Latency =2 Maximum data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD 24 25 26 27 28 Semiconductor Group SPD Entry Value Hex 4Mx64 -10 80 08 04 0C 08 4Mx72 -10 80 08 04 0C 08 8Mx64 -10 80 08 04 0C 08 8Mx72 -10 80 08 04 0C 08 1/2 64 0 LVTTL 10.0 ns 7.0 ns none Self-Refresh, 15.6µs x16 n/a / x8 tccd = 1 CLK 01 40 00 01 A0 70 00 80 01 48 00 01 A0 70 02 80 02 40 00 01 A0 70 00 80 02 48 00 01 A0 70 02 80 10 00 01 10 08 01 10 00 01 10 08 01 1, 2, 4, 8 & full page 4 CL = 2 & 3 CS latency = 0 WL = 0 non buffered/ non reg. Vcc tol +/- 10% 15.0 ns 8F 8F 8F 8F 04 06 01 01 00 04 06 01 01 00 04 06 01 01 00 04 06 01 01 00 06 F0 06 F0 06 F0 06 F0 8.0 ns 80 80 80 80 not supported not supported FF FF FF FF FF FF FF FF 24 ns 20 ns 18 14 18 14 18 14 18 14 128 256 SDRAM 12 8 13 HYS64(72)V4200/8220GU SDRAM-Modules SPD cont’d: Byte# Description Minimum RAS to CAS delay tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information (optional) 125 (FFh if not used) 126 Max. Frequency Specification 127 Support details 128+ Unused storage locations SPD Entry Value 4Mx64 -8 18 3C 08 25 10 25 10 FF 4Mx72 -8 18 3C 08 25 10 25 10 FF 8Mx72 -8 18 3C 08 25 10 25 10 FF 8Mx72 -8 18 3C 08 25 10 25 10 FF Revision 1.2 12 7C XX 12 8E XX 12 7D XX 12 8F XX 66 MHz 66 AF FF 66 AF FF 66 FF FF 66 FF FF 29 30 31 32 33 34 35 32-61 Semiconductor Group Hex 24 ns 60 ns 32 MByte 2.5 ns 1 ns 2.5 ns 1 ns 14 HYS64(72)V4200/8220GU SDRAM-Modules L-DIM-168-31 SDRAM DIMM Module package 133,35 127,35 3,0 1 10 11 40 84 41 17,78 x) 42,18 1,27+- 0.1 66,68 A 85 29.31 4,0 C B 124 94 95 125 168 x) 6,35 6,35 2,0 Detail A 1,0 + - 0.5 2,54 min. 3,125 3,125 1,27 2,0 0,2 +- 0,15 Detail C Detail B DM168-31.WMF x) on ECC modules only Semiconductor Group 15